Output frequency range: 1500 MHz to 2500 MHz
Modulation bandwidth: >500 MHz (3 dB)
1 dB output compression: 14 dBm @ 1900 MHz
Noise floor: −158 dBm/Hz
Sideband suppression: −45 dBc @ 1900 MHz
Carrier feedthrough: −45 dBm @ 1900 MHz
Single supply: 4.75 V to 5.25 V
24-lead LFCSP_VQ
APPLICATIONS
Cellular communication systems
CDMA2000/GSM/WCDMA
WiMAX/broadband wireless access systems
Satellite modems
GENERAL DESCRIPTION
The ADL5372 is a member of the fixed-gain quadrature modulator
(F-MOD) family designed for use from 1500 MHz to 2500 MHz.
Its excellent phase accuracy and amplitude balance enable high
performance intermediate frequency or direct radio frequency
modulation for communication systems.
The ADL5372 provides a >500 MHz, 3 dB baseband bandwidth,
making it ideally suited for use in broadband zero IF or low
IF-to-RF applications and in broadband digital predistortion
transmitters.
Quadrature Modulator
ADL5372
FUNCTIONAL BLOCK DIAGRAM
IBBP
IBBN
LOIP
LOIN
QBBN
QBBP
The ADL5372 accepts two differential baseband inputs and a
single-ended, local oscillator (LO) and generates a singleended output.
The ADL5372 is fabricated using the Analog Devices, Inc.
advanced silicon-germanium bipolar process. It is available in
a 24-lead, exposed-paddle, Pb-free, LFCSP. Performance is
specified over a −40°C to +85°C temperature range. A Pb-free
evaluation board is available.
QUADRATURE
PHASE
SPLITTER
Figure 1.
VOUT
06511-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VS = 5 V; TA = 25°C; LO = 0 dBm1 single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (f
Table 1.
Parameter Conditions Min Typ Max Unit
OPERATING FREQUENCY RANGE Low frequency 1500 MHz
High frequency 2500 MHz
LO = 1900 MHz
Output Power VIQ = 1.4 V p-p differential 7.1 dBm
Output P1dB 14.2 dBm
Carrier Feedthrough −45 dBm
Sideband Suppression −45 dBc
Quadrature Error 0.21 Degrees
I/Q Amplitude Balance 0.09 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Noise Floor
GSM 6 MHz carrier offset, P
WCDMA
LO = 2150 MHz
Output Power VIQ = 1.4 V p-p differential 7.2 dBm
OutputP1dB 14 dBm
Carrier Feedthrough −41 dBm
Sideband Suppression −44 dBc
Quadrature Error 0.27 Degrees
I/Q Amplitude Balance 0.12 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Noise Floor
WCDMA
LO = 2400 MHz
Output Power VIQ = 1.4 V p-p differential 5.6 dBm
OutputP1dB 12.4 dBm
Carrier Feedthrough −36 dBm
Sideband Suppression −40 dBc
Quadrature Error 0.6 Degrees
I/Q Amplitude Balance 0.13 dB
Second Harmonic P
Third Harmonic P
Output IP2 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Noise Floor
WiMAX
) = 1 MHz, unless otherwise noted.
BB
− (fLO + (2 × fBB)), P
OUT
− (fLO + (3 × fBB)), P
OUT
= 6.2 dBm −50 dBc
OUT
= 6.2 dBm −47 dBc
OUT
= 1 dBm per tone 54 dBm
OUT
= 1 dBm per tone 27 dBm
OUT
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset; LO = 1960 MHz
= 5 dBm, PLO = 6 dBm; LO = 1960 MHz −158 dBc/Hz
OUT
Single carrier, 20 MHz carrier offset, P
P
= 0 dBm; LO = 1966 MHz
LO
− (fLO + (2 × fBB)), P
OUT
− (fLO + (3 × fBB)), P
OUT
= 6.2 dBm −59 dBc
OUT
= 6.2 dBm −48 dBc
OUT
OUT
OUT
= −10 dBm,
OUT
= 1 dBm per tone 65 dBm
= 1 dBm per tone 26.5 dBm
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset
Single carrier, 20 MHz carrier offset, P
= −10 dBm, PLO = 0 dBm;
OUT
LO = 2140 MHz
− (fLO + (2 × fBB)), P
OUT
− (fLO + (3 × fBB)), P
OUT
= 6.2 dBm −54 dBc
OUT
= 6.2 dBm −48 dBc
OUT
= 1 dBm per tone 57 dBm
OUT
= 1 dBm per tone 24.5 dBm
OUT
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset; LO = 2350 MHz
I and Q Input Bias Level 500 mV
Input Bias Current Current sourcing from each baseband input with a bias of 500 mV dc2 45 μA
Input Offset Current 0.1 μA
Differential Input Impedance 2900 kΩ
Bandwidth (0.1 dB) LO = 1900 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 70 MHz
Bandwidth (1 dB) LO = 1900 MHz, baseband input = 700 mV p-p sine wave on 500 mV dc 350 MHz
POWER SUPPLIES Pin VPS1 and Pin VPS2
Voltage 4.75 5.25 V
Supply Current 165 mA
1
High LO drive reduces noise at a 6 MHz carrier offset in GSM applications.
2
See V-to-I Converter section for architecture information.
1
Characterization performed at typical level −6 0 +6 dBm
Rev. 0 | Page 4 of 24
ADL5372
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VPOS 5.5 V
IBBP, IBBN, QBBP, QBBN 0 V to 2 V
LOIP and LOIN 13 dBm
Internal Power Dissipation 1100 mW
θJA (Exposed Paddle Soldered Down) 54°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24
ADL5372
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
QBBP
COM4
QBBN
COM4
IBBN
IBBP
2422232120
19
COM1
COM1
VPS1
VPS1
VPS1
VPS1
1
2
3
4
5
6
F-MOD
TOP VIEW
(Not to Scale)
798
101112
LOIP
LOIN
COM2
COM2
COM3
VPS5
18
VPS4
17
VPS3
16
VPS2
15
VPS2
14
VOUT
13
COM3
06511-002
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 7, 10 to 12,
COM1 to COM4 Input Common Pins. Connect to ground plane via a low impedance path.
21, 22
3 to 6, 14 to 18 VPS1 to VPS5
Positive Supply Voltage Pins. All pins should be connected to the same supply (V
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 25).
8, 9 LOIP, LOIN
50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled.
AC-couple LOIN to ground and drive LO through LOIP.
13 VOUT
Device Output. Single-ended RF output. Pin should be ac-coupled to the load. The output
is ground referenced.
19, 20, 23, 24 IBBP, IBBN, QBBN, QBBP
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs
must be dc-biased to 500 mV dc and must be driven from a low impedance source.
Nominal characterized ac signal swing is 700 mV p-p on each pin. This results in a differential
drive of 1.4 V p-p with a 500 mV dc bias. These inputs are not self-biased and must be
externally biased.
Exposed Paddle Connect to ground plane via a low impedance path.
). To ensure
S
Rev. 0 | Page 6 of 24
ADL5372
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V; TA = 25°C; LO = 0 dBm single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (f