500 MHz to 1700 MHz Balanced Mixer,
LO Buffer, IF Amplifier, and RF Balun
FEATURES
RF frequency range of 500 MHz to 1700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.6 dB
SSB noise figure of 9.1 dB
SSB noise figure with 5 dBm blocker of 19.5 dB
Input IP3 of 26.6 dBm
Input P1dB of 10.2 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle 5 mm × 5 mm, 20-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
GENERAL DESCRIPTION
The ADL5357 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and LO balancing circuitry
to allow for single-ended operation. The ADL5357 incorporates
an RF balun, allowing for optimal performance over a 500 MHz to
1700 MHz RF input frequency range using high-side LO injection
for RF frequencies from 500 MHz to 1200 MHz and low-side
injection for frequencies from 900 MHz to 1700 MHz. The
balanced passive mixer arrangement provides good LO-to-RF
leakage, typically better than −46 dBm, and excellent intermodulation performance. The balanced mixer core also provides
extremely high input linearity, allowing the device to be used in
demanding cellular applications where in-band blocking signals
may otherwise result in the degradation of dynamic performance.
A high linearity IF buffer amplifier follows the passive mixer core
to yield a typical power conversion gain of 8.6 dB and can be used
with a wide range of output impedances.
ADL5357
FUNCTIONAL BLOCK DIAGRAM
IFGM
20 19 18 17 16
1
VPIF
2
RFIN
3
RFCT
4
COMM
5
COMM
6 7 8 9 10
VLO3 LGM3 VLO2 LOSW NC
NC = NO CONNECT
The ADL5357 provides two switched LO paths that can be
used in TDD applications where it is desirable to rapidly switch
between two local oscillators. LO current can be externally set
using a resistor to minimize dc current commensurate with the
desired level of performance. For low voltage applications, the
ADL5357 is capable of operation at voltages down to 3.3 V with
substantially reduced current. Under low voltage operation, an
additional logic pin is provided to power down (<200 μA) the
circuit when desired.
The ADL5357 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
500 to 1700 ADL5357
1200 to 2500 ADL5355
IFOP IFON PWDN LEXT
ADL5357
BIAS
GENERATOR
Figure 1.
Single
Mixer
Single Mixer +
IF Amp
15
LOI2
14
VPSW
13
VGS1
12
VGS0
11
LOI1
Dual Mixer +
IF Amp
8081-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
ADL5357
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Performance ........................................................................... 4
3.3 V Performance ........................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance ........................................................................... 7
3.3 V Performance ...................................................................... 14
Spur Tables .................................................................................. 15
Circuit Description......................................................................... 16
RF Subsystem .............................................................................. 16
LO Subsystem ............................................................................. 17
Applications Information .............................................................. 18
Basic Connections ...................................................................... 18
IF Port .......................................................................................... 18
Bias Resistor Selection ............................................................... 18
Mixer VGS Control DAC .......................................................... 18
Evaluation Board ............................................................................ 20
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5357
SPECIFICATIONS
V
= 5 V, IS = 190 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.
POS
Table 2.
Parameter Conditions Min Typ Max Unit
RF INPUT INTERFACE
Return Loss Tunable to >20 dB over a limited bandwidth 19 dB
Input Impedance 50 Ω
RF Frequency Range 500 1700 MHz
OUTPUT INTERFACE
Output Impedance Differential impedance, f = 200 MHz 240||0.4 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V
LO INTERFACE
LO Power −6 0 +10 dBm
Return Loss 12 dB
Input Impedance 50 Ω
LO Frequency Range 730 1670 MHz
POWER-DOWN (PWDN) INTERFACE
PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 220 ns
PWDN Input Bias Current Device enabled 0.0 μA
Device disabled 70 μA
1
Apply the supply voltage from the external circuit through the choke inductors.
2
The PWDN function is intended for use with V
2
≤ 3.6 V only.
POS
Rev. 0 | Page 3 of 24
ADL5357
5 V PERFORMANCE
V
= 5 V, IS = 190 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
POS
otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Gain Including 4:1 IF port transformer and PCB loss 7 8.6 9.5 dB
Voltage Conversion Gain Z
SSB Noise Figure 9.1 dB
SSB Noise Figure Under Blocking
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
Input 1 dB Compression Point (IP1dB) 10.2 dBm
LO-to-IF Leakage Unfiltered IF output −7 dBm
LO-to-RF Leakage −46.7 dBm
RF-to-IF Isolation −35 dBc
IF/2 Spurious −10 dBm input power −69.2 dBc
IF/3 Spurious −10 dBm input power −83.4 dBc
POWER SUPPLY
Positive Supply Voltage 4.5 5 5.5 V
Quiescent Current LO supply, resistor programmable 100 mA
IF supply, resistor programmable 90 mA
Total Quiescent Current V
= 50 Ω, differential Z
SOURCE
5 dBm blocker present ±10 MHz from wanted RF input,
= 200 Ω differential 14.9 dB
LOAD
19.5 dB
LO source filtered
= 899.5 MHz, f
f
RF1
= 900.5 MHz, fLO = 1103 MHz,
RF2
22 26.6 dBm
each RF tone at −10 dBm
= 950 MHz, f
f
RF1
= 900 MHz, fLO = 1103 MHz,
RF2
62.8 dBm
each RF tone at −10 dBm
= 5 V 190 mA
POS
3.3 V PERFORMANCE
V
= 3.3 V, IS = 125 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
POS
and Z
= 50 Ω, unless otherwise noted.
O
Table 4.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8.8 dB
Voltage Conversion Gain Z
SSB Noise Figure 9.0 dB
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
Input 1 dB Compression Point (IP1dB) 7.1 dBm
POWER INTERFACE
Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 125 mA
Power-Down Current Device disabled 150 μA
= 50 Ω, differential Z
SOURCE
= 899.5 MHz, f
f
RF1
= 900.5 MHz, fLO = 1103 MHz,
RF2
each RF tone at −10 dBm
= 950 MHz, f
f
RF1
= 900 MHz, fLO = 1103 MHz,
RF2
each RF tone at −10 dBm
= 200 Ω differential 15.1 dB
LOAD
21.4 dBm
55.7 dBm
Rev. 0 | Page 4 of 24
ADL5357
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage, V
RF Input Level 20 dBm
LO Input Level 13 dBm
IFOP, IFON Bias Voltage 6.0 V
VGS0, VGS1, LOSW, PWDN 5.5 V
Internal Power Dissipation 1.2 W
θJA 25°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering, 60 sec) 260°C
5.5 V
POS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24
ADL5357
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DN
IFON
IFOP
IFGM
20
1VPIF
2RFIN
ADL5357
3RFCT
TOP VIEW
4COMM
(Not to Scale)
5COMM
6
VLO3
NOTES
1.2 NC = NO CONNECT.
. EXPOSED PAD. MUST BE SOLDERED
TO GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 VPIF Positive Supply Voltage for IF Amplifier.
2 RFIN RF Input. Must be ac-coupled.
3 RFCT RF Balun Center Tap (AC Ground).
4, 5 COMM Device Common (DC Ground).
6, 8 VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
7 LGM3 LO Amplifier Bias Control.
9 LOSW LO Switch. LOI1 selected for 0 V, and LOI2 selected for 3 V.
10 NC No Connect.
11, 15 LOI1, LOI2 LO Inputs. Must be ac-coupled.
12, 13 VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
14 VPSW Positive Supply Voltage for LO Switch.
16 LEXT IF Return. This pin must be grounded.
17 PWDN Power Down. Connect this pin to ground for normal operation and connect this pin to 3.0 V for disable mode.
18, 19 IFON, IFOP Differential IF Outputs (Open Collectors). Each requires an external dc bias.
20 IFGM IF Amplifier Bias Control.
EPAD (EP) Exposed pad. Must be soldered to ground.
18
19
PIN 1
INDICATOR
8
7
VLO2
LGM3
LEXT
PW
17
16
15 LO I2
14 VPSW
13 VGS1
12 VGS0
11 LO I1
9
10
NC
LOSW
08081-002
Rev. 0 | Page 6 of 24
ADL5357
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
V
= 5 V, IS = 190 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
POS
and Z
= 50 Ω, unless otherwise noted.
O
220
210
200
= –40°C
T
190
180
T
= +85°C
A
170
SUPPLY CURRENT (mA)
160
A
TA = +25°C
80
70
60
50
40
30
INPUT IP2 (dBm)
20
10
= –40°C
T
A
TA = +25°C
T
= +85°C
A
150
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 3. Supply Current vs. RF Frequency
12
10
T
= –40°C
A
8
6
4
CONVERSION G AIN (dB)
2
0
700 750 800 850 900 950 1000 1050 1100 1150 1200
= +85°C
T
A
RF FREQUENCY (MHz)
TA = +25°C
Figure 4. Power Conversion Gain vs. RF Frequency
35
T
= –40°C
30
A
25
= +85°C
T
A
20
15
INPUT IP3 (dBm)
10
5
0
700 750 800 850 900 950 1000 1050 1100 1150 1200
TA = +25°C
RF FREQUENCY (MHz)
Figure 5. Input IP3 vs. RF Frequency
0
700 750 800 850 900 950 1000 1050 1100 1150 1200
08081-034
RF FREQUENCY (MHz)
8081-019
Figure 6. Input IP2 vs. RF Frequency
14
13
12
11
10
INPUT P1dB (dBm)
08081-015
= +85°C
T
A
9
8
7
6
700 750 800 850 900 950 1000 1050 1100 1150 1200
TA = +25°C
T
A
RF FREQUENCY (MHz)
= –40°C
08081-024
Figure 7. Input P1dB vs. RF Frequency
20
18
16
14
12
T
= +85°C
A
10
8
= –40°C
T
A
6
SSB NOISE FIGURE (dB)
4
2
0
700 750 800 850 900 950 1000 1050 1100 1150 1200
08081-021
RF FREQUENCY (MHz)
TA = +25°C
08081-027
Figure 8. SSB Noise Figure vs. RF Frequency
Rev. 0 | Page 7 of 24
ADL5357
250
200
150
100
SUPPLY CURRENT (mA)
50
V
V
POS
POS
= 5.25V
= 4.75V
80
V
= 5.0V
70
60
V
= 5V
POS
50
40
30
INPUT IP2 (dBm)
20
10
POS
V
= 5.25V
POS
V
= 4.75V
POS
0
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
Figure 9. Supply Current vs. Temperature
10
9
8
7
6
CONVERSION G AIN (dB)
5
4
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
V
V
V
Figure 10. Power Conversion Gain vs. Temperature
35
33
31
V
29
27
25
23
INPUT IP3 (dBm)
21
19
17
15
V
= 4.75V
POS
–40 –20 0 20 40 60 80
= 5.0V
POS
TEMPERATURE (°C)
V
POS
Figure 11. Input IP3 vs. Temperature
= 4.75V
POS
= 5.0V
POS
= 5.25V
POS
= 5.25V
0
–40 –20 0 20 40 60 80
08081-035
TEMPERATURE (°C)
08081-047
Figure 12. Input IP2 vs. Temperature
14
13
12
11
10
V
9
8
INPUT P1dB (dBm)
7
6
5
4
–40 –20 0 20 40 60 80
08081-046
POS
= 4.75V
TEMPERATURE (°C)
V
= 5.0V
POS
V
= 5.25V
POS
08081-049
Figure 13. Input P1dB vs. Temperature
12
11
V
= 5.0V
10
V
= 5.25V
POS
9
V
= 4.75V
POS
8
SSB NOISE FIGURE (dB)
7
6
–40 –20 0 20 40 60 80
08081-048
TEMPERATURE (°C)
POS
8081-028
Figure 14. SSB Noise Figure vs. Temperature
Rev. 0 | Page 8 of 24
ADL5357
220
210
200
190
180
170
SUPPLY CURRENT (mA)
160
TA = +25°C
TA = –40°C
TA = +85°C
80
70
60
50
40
30
INPUT IP2 (dBm)
20
10
= –40°C
T
A
TA = +25°C
= +85°C
T
A
150
30 80 130 180 230 280 330 380 430
IF FREQUENCY (MHz)
Figure 15. Supply Current vs. IF Frequency
12
12
T
10
10
8
8
6
6
4
4
CONVERSION GAIN (dB)
2
2
0
0
30 80 130 180 230 280 330 380 430
= –40°C
A
= +85°C
T
A
IF FREQUENCY (MHz)
TA = +25°C
Figure 16. Power Conversion Gain vs. IF Frequency
35
T
= –40°C
= +85°C
T
A
A
30
25
20
15
INPUT IP3 (dBm)
10
5
0
30 80 130 180 230 280 330 380 430
TA = +25°C
IF FREQUENCY (MHz)
Figure 17. Input IP3 vs. IF Frequency
0
30 80 130 180 230 280 330 380 430
08081-031
IF FREQUENCY (MHz)
08081-017
Figure 18. Input IP2 vs. IF Frequency
12
T
= +85°C
10
INPUT P1dB (dBm)
08081-013
A
T
= –40°C
A
8
6
4
2
0
30 80 130 180 230 280 330 380 430
TA = +25°C
IF FREQUENCY (MHz)
08081-022
Figure 19. Input P1dB vs. IF Frequency
15
14
13
12
11
10
9
8
SSB NOISE F IGURE (dB)
7
6
5
30 80 130 180 230 280 330 380 430
08081-020
IF FREQ UENCY (MHz)
08081-011
Figure 20. SSB Noise Figure vs. IF Frequency
Rev. 0 | Page 9 of 24
ADL5357
12
10
8
6
= –40°C
T
A
= +85°C
T
A
TA = +25°C
12
T
= +85°C
A
10
T
= –40°C
A
8
6
TA = +25°C
4
CONVERSION GAIN (dB)
2
0
–6 –4 –2 0 2 4 6 8 10
LO POWER LEVEL (dBm)
Figure 21. Power Conversion Gain vs. LO Power
30
25
20
15
INPUT IP3 (dBm)
10
5
0
= –40°C
T
A
T
= +85°C
A
6420246810
LO POWER LEVEL (dBm)
TA = +25°C
Figure 22. Input IP3 vs. LO Power
80
70
60
50
40
30
INPUT IP2 (dBm)
20
10
0
–6 –4 –2 0 2 4 6 8 10
T
= –40°C
A
T
= +85°C
A
TA = +25°C
LO POW ER (dBm)
Figure 23. Input IP2 vs. LO Power
4
INPUT P1dB (dBm)
2
0
–6 –4 –2 0 2 4 6 8 10
08081-014
LO POW ER (dBm)
08081-023
Figure 24. Input P1dB vs. LO Power
0
–10
–20
–30
–40
–50
–60
IF/2 SPURIOUS (dBc)
–70
–80
–90
700 750 800 850 900 950 1000 1050 1100 1150 1200
8081-016
T
= –40°C
A
T
A
RF FREQUENCY (MHz)
TA = +25°C
= +85°C
08081-007
Figure 25. IF/2 Spurious vs. RF Frequency
0
–10
–20
–30
–40
–50
–60
IF/3 SPURIOUS (dBc)
–70
–80
–90
–100
700 750 800 850 900 950 1000 1050 1100 1150 1200
08081-018
TA = +25°C
T
= –40°C
A
RF FREQ UENCY (MHz)
T
= +85°C
A
8081-008
Figure 26. IF/3 Spurious vs. RF Frequency
Rev. 0 | Page 10 of 24
ADL5357
100
80
MEAN: 8.59
SD: 0.14%
500
400
10
8
60
40
20
DISTRIBUTI ON PERCENTAGE (%)
0
8.38.48.58.68.78.88.9
CONVERSION G AIN (dB)
Figure 27. Power Conversion Gain Distribution
100
MEAN: 26.57
SD: 0.39%
80
60
40
20
DISTRIBUTI ON PERCENTAGE (%)
0
24 25 26 27 28 29
INPUT IP3 (dBm)
Figure 28. Input IP3 Distribution
100
MEAN: 10.22
SD: 0.50%
80
300
200
RESISTANCE (Ω)
100
0
30 80 130 280230180 330 380 430
08081-044
IF FREQUENCY (MHz)
6
4
CAPACITANCE (pF)
2
0
08081-050
Figure 30. IF Port Return Loss
0
5
10
15
20
25
RF RETURN LOSS (dB)
30
35
40
700 750 800 850 900 950 1000 1050 1100 1150 1200
08081-043
RF FREQUENCY (MHz)
08081-029
Figure 31. RF Port Return Loss, Fixed IF
0
5
60
40
20
DISTRIBUTI ON PERCENTAGE (%)
0
9.6 9.9 10. 2 10.5 10.8
INPUT P1dB (dBm)
08081-045
Figure 29. Input P1dB Distribution
10
15
20
LO RETURN LOSS (dB)
25
30
900 950 1000 1050 1100 1150 1200 125 0 1300 1350 1400
LO FREQUENCY ( MHz)
SELECTED
UNSELECTED
Figure 32. LO Return Loss, Selected and Unselected
08081-038
Rev. 0 | Page 11 of 24
ADL5357
A
A
70
0
65
T
= +25°C
60
TION (dB)
55
50
LO SWI TCH ISOL
45
40
900 950 1000 1050 1100 1150 1200 12 50 1300 1350 1400
= +85°C
T
A
LO FREQ UENCY (MHz)
A
TA = –40°C
Figure 33. LO Switch Isolation vs. LO Frequency
0
–5
–10
–15
TION (dBc)
–20
–25
–30
TA = +85°C
RF-TO-IF ISOL
–35
–40
–45
700 750 800 850 900 950 1000 1050 1100 1150 1200
TA = +25°C
TA = –40°C
RF FREQUENCY (MHz)
Figure 34. RF-to-IF Isolation vs. RF Frequency
0
= –40°C
T
A
–5
= +85°C
T
A
–10
TA = +25°C
–10
–20
–30
–40
LO-TO-RF LE AKAGE (dBm)
–50
–60
08081-041
TA = +85°C
TA = –40°C
TA = +25°C
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
LO FREQ UENCY (MHz)
8081-026
Figure 36. LO-to-RF Leakage vs. LO Frequency
0
–5
–10
–15
–20
–25
–30
2LO LEAKAGE (dBm)
–35
–40
–45
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
08081-030
LO FREQUENCY (MHz)
2LO TO RF
2LO TO IF
08081-039
Figure 37. 2LO Leakage vs. LO Frequency
0
–10
–20
–15
–20
LO-TO-IF LEAKAGE (dBm)
–25
–30
900 950 1000 1050 1100 1150 1200 12 50 1300 1350 1400
LO FREQ UENCY (MHz)
Figure 35. LO-to-IF Leakage vs. LO Frequency
08081-025
–30
–40
3LO LEAKAGE (dBm)
–50
–60
900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400
3LO TO IF
LO FREQ UENCY (MHz)
3LO TO RF
Figure 38. 3LO Leakage vs. LO Frequency
08081-040
Rev. 0 | Page 12 of 24
ADL5357
1200
15
14
13
12
11
10
9
8
SSB NOISE F IGURE (dB)
7
6
5
08081-037
30
25
20
15
10
NOISE FI GURE (dB)
5
0
–30 –25 –20 –15 –10 –5 0 5 10
BLOCKER POW ER (dBm)
08081-042
Figure 42. SSB Noise Figure vs.10 MHz Offset Blocker Level
30
28
26
140
120
R9 LO SET RESISTOR
100
10
9
8
CONVERSION
GAIN
800
850 900
RF FREQUENCY (MHz)
950
SSB NOISE
FIGURE
1050
1000
VGS = 00
VGS = 01
VGS = 10
VGS = 11
1100 115 0
CONVERSION GAIN (dB)
7
6
5
4
3
2
1
0
700 750
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency
20
18
16
VGS = 00
VGS = 01
VGS = 10
VGS = 11
INPUT IP3
14
12
INPUT P1dB (dBm)
10
8
6
700 750 800 850 900 950 1000 1050 1100 1150 1200
INPUT P1dB
RF FREQUENCY (MHz)
Figure 40. Input P1dB and Input IP3 vs. RF Frequency
12
INPUT IP3
11
10
SSB NOISE F IGURE
9
8
7
CONVERSION GAIN AND SSB NOISE FIGURE (dB)
6
0.60.81.01.21.41.61.8
CONVERSION GAIN
LO BIAS RESI STOR VALUE (kΩ)
Figure 41. Power Conversion Gain, SSB Noise Figure, and
Input IP3 vs. LO Bias Resistor Value
24
22
INPUT IP3 (dBm)
20
18
16
08081-036
80
60
40
SUPPLY CURRENT (mA)
20
0
600 800 1000 1200 1400 1600 1800
BIAS RESISTOR VALUE (Ω)
R14 IF SET RESISTOR
08081-033
Figure 43. IF or LO Supply Current vs. IF or LO Bias Resistor Value
30
25
20
15
INPUT IP3 (dBm)
10
5
0
08081-012
12
11
10
9
8
7
CONVERSION G AIN AND SSB NOISE FI GURE (dB)
6
0.6 0.7 0.8 0.9 1.0 1.1 1. 2 1.3 1.4 1.5
IF BIAS RESI STOR VALUE (kΩ)
INPUT IP3
SSB NOISE FIGURE
CONVERSION GAIN
30
25
20
15
INPUT IP3 (dBm)
10
5
0
08081-059
Figure 44. Power Conversion Gain, SSB Noise Figure, and
Input IP3 vs. IF Bias Resistor Value
Rev. 0 | Page 13 of 24
ADL5357
3.3 V PERFORMANCE
V
= 3.3 V, IS = 125 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
POS
and Z
= 50 Ω, unless otherwise noted.
O
160
150
140
130
120
110
100
90
SUPPLY CURRENT (mA)
80
70
60
700 750 800 850 900 950 1000 105 0 1100 1150 1200
TA = +25°C
RF FREQUENCY (MHz)
TA = –40°C
TA = +85°C
Figure 45. Supply Current vs. RF Frequency at 3.3 V
12
08081-064
80
T
= +85°C
70
60
50
40
30
INPUT IP2 (dBm)
20
10
0
700 750 800 850 900 950 1000 1050 1100 1150 1200
TA = +25°C
RF FREQ UENCY (MHz)
A
T
A
= –40°C
Figure 48. Input IP2 vs. RF Frequency at 3.3 V
12
08081-061
10
8
6
4
CONVERSION G AIN (dB)
2
0
700 750 800 850 900 950 1000 1050 1100 1150 1200
T
= –40°C
A
RF FREQUENCY (MHz)
TA = +25°C
= +85°C
T
A
Figure 46. Power Conversion Gain vs. RF Frequency at 3.3 V
25
20
15
10
INPUT IP3 (dBm)
5
= –40°C
T
A
T
A
= +85°C
TA = +25°C
10
T
8
6
4
INPUT P1dB (dBm)
2
0
700 750 800 850 900 950 1000 1050 1100 1150 1200
08081-060
= +85°C
A
RF FREQUENCY (MHz)
TA = +25°C
= –40°C
T
A
08081-063
Figure 49. Input P1dB vs. RF Frequency at 3.3 V
14
12
T
= +85°C
= –40°C
T
A
A
10
8
6
SSB NOISE FIGURE (dB)
4
TA = +25°C
0
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY (MHz)
Figure 47. Input IP3 vs. RF Frequency at 3.3 V
08081-062
2
700 750 800 850 900 950 1000 1050 1100 1150 1200
RF FREQUENCY ( MHz)
Figure 50. SSB Noise Figure vs. RF Frequency at 3.3 V
08081-051
Rev. 0 | Page 14 of 24
ADL5357
SPUR TABLES
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was only measured for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
V
= 5 V, IS = 190 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
POS
unless otherwise noted.
Table 7.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0 −4.8 −15.8 −33.5 −38.6 −55.7
1 −41.3 0.0 −47.1 −37.9 −57.9 −57.3 −74.9
2 −87.1 −65.5 −73.4 −78.8 −87.3 −93.1 −92.1 <−100
3 <−100 <−100 <−100 −94.0 <−100 <−100 <−100 <−100
4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
N
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
3.3 V Performance
V
= 3.3 V, IS = 125 mA, TA = 25°C, fRF = 900 MHz, fLO = 1103 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
POS
and Z
= 50 Ω, unless otherwise noted.
O
Table 8.
M
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0 −9.9 −20.0 −43.5 −40.8 −62.2
1
−50.8 0.0 −50.1 −37.1 −53.5 −56.0 −72.8
2 −75.0 −59.1 −69.6 −71.4 −81.6 −90.7 −86.7 <−100
3 <−100 −93.8 <−100 −82.0 −99.8 <−100 <−100 <−100
4 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
6
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
N
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
11
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
Rev. 0 | Page 15 of 24
ADL5357
CIRCUIT DESCRIPTION
The ADL5357 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated
into a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.
The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network, and IF
amplifier.
The LO subsystem consists of an SPDT-terminated FET switch
and a three-stage limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input.
A block diagram of the device is shown in Figure 51.
IFGM
20 19 18 17 16
1
VPIF
2
RFIN
3
RFCT
4
COMM
5
COMM
VLO3 LGM3 VLO2 LOSW NC
NC = NO CONNECT
6 7 8 9 10
IFOP IFON PWDN LEXT
ADL5357
BIAS
GENERATOR
Figure 51. Simplified Schematic
15
LOI2
14
VPSW
13
VGS1
12
VGS0
11
LOI1
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range
of 500 MHz to 1700 MHz.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input
of the IF amplifier, where high peak signal levels can compromise
the compression and intermodulation performance of the system.
This termination is accomplished by the addition of a sum
network between the IF amplifier and the mixer and also in
the feedback elements in the IF amplifier.
The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance that are
required to achieve the overall performance. The balanced opencollector output of the IF amplifier, with impedance modified
by the feedback within the amplifier, permits the output to be
connected directly to a high impedance filter, differential amplifier,
or an analog-to-digital input while providing optimum secondorder intermodulation suppression. The differential output
impedance of the IF amplifier is approximately 200 Ω. If operation
8081-001
in a 50 Ω system is desired, the output can be transformed to
50 Ω by using a 4:1 transformer.
The intermodulation performance of the design is generally
limited by the IF amplifier. The IP3 performance can be optimized
by adjusting the IF current with an external resistor.
Figure 43, and Figure 44 illustrate how various IF and LO bias
resistors affect the performance with a 5 V supply. Additionally,
dc current can be saved by increasing either or both resistors. It
is permissible to reduce the dc supply voltage to as low as 3.3 V,
further reducing the dissipated power of the part. (Note that no
performance enhancement is obtained by reducing the value of
these resistors, and excessive dc power dissipation may result.)
Figure 41,
Rev. 0 | Page 16 of 24
ADL5357
LO SUBSYSTEM
The LO amplifier is designed to provide a large signal level to
the mixer to obtain optimum intermodulation performance.
The resulting amplifier provides extremely high performance
centered on an operating frequency of 1100 MHz. The best
operation is achieved with either high-side LO injection for RF
signals in the 500 MHz to 1200 MHz range or high-side injection
for RF signals in the 900 MHz to 1700 MHz range. Operation
outside these ranges is permissible, and conversion gain is
extremely wideband, easily spanning 500 MHz to 1700 MHz,
but intermodulation is optimal over the aforementioned ranges.
The ADL5357 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the
LO amplifier by raising the value of the external bias control
resistor. For dc current critical applications, the LO chain
can operate with a supply voltage as low as 3.3 V, resulting in
substantial dc power savings.
In addition, when operating with supply voltages below 3.6 V,
the ADL5357 has a power-down mode that permits the dc
current to drop to <200 μA.
All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.
All pins, including the RF pins, are ESD protected and have
been tested up to a level of 1500 V HBM and 500 V CDM.
Rev. 0 | Page 17 of 24
ADL5357
APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5357 mixer is designed to downconvert radio
frequencies (RF) primarily between 500 MHz and 1700 MHz
to lower intermediate frequencies (IF) between 30 MHz and
450 MHz. Figure 52 depicts the basic connections of the mixer.
It is recommended to ac couple RF and LO input ports to prevent
non-zero dc voltages from damaging the RF balun or LO input
circuit. The RFIN capacitor value of 8 pF is recommended to
provide the optimized RF input return loss for the desired
frequency band.
IF PORT
The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.
The real part of the output impedance is approximately
200 Ω, as seen in Figure 30, which matches many commonly
used SAW filters without the need for a transformer. This results in
a voltage conversion gain that is approximately 6 dB higher than
the power conversion gain, as shown in Tabl e 3. When a 50 Ω
output impedance is needed, use a 4:1 impedance transformer,
as shown in Figure 52.
BIAS RESISTOR SELECTION
Two external resistors, R
bias current of the integrated amplifiers at the IF and LO terminals.
It is necessary to have a sufficient amount of current to bias both
the internal IF and LO amplifiers to optimize dc current vs.
optimum IIP3 performance. Figure 41, Figure 43, and Figure 44
provide the reference for the bias resistor selection when lower
power consumption is considered at the expense of conversion
gain and IP3 performance.
BIAS IF
and R
, are used to adjust the
BIAS LO
MIXER VGS CONTROL DAC
The ADL5357 features two logic control pins, VGS0 (Pin 12) and
VGS1 (Pin 13), that allow programmability for internal gate-tosource voltages for optimizing mixer performance over desired
frequency bands. The evaluation board defaults both VGS0 and
VGS1 to ground. Power conversion gain, IIP3, NF, and IP1dB
can be optimized, as is shown in Figure 39 and Figure 40.
Rev. 0 | Page 18 of 24
ADL5357
V
100pF
470nH 470nH
R
BIAS IF
+5V
4.7µF
10pF
10pF
+5V
8pF
RF IN
0.1µF
20
1
2
3
4
+5
150pF
10kΩ
19 18 17 16
ADL5357
BIAS
GENERATOR
4:1
15
14
13
12
IF OUT
22pF
LO2 IN
+5V
10pF
22pF
LO1 IN
08081-005
+5V
5
6 7 8 9 10
R
BIAS LO
10pF10pF
11
10kΩ
Figure 52. Typical Application Circuit
Rev. 0 | Page 19 of 24
ADL5357
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 53. The evaluation board is fabricated using Rogers®
RO3003 material. Tab le 9 describes the various configuration
options of the evaluation board. Evaluation board layout is shown
in Figure 54 to Figure 57.
L5
VPOS
C18
100pF
470nH
T1
IF1-OUT
RF-IN
VPOS
C1
8pF
100pF
C2
10µF
C5
0.01µFC410pF
C19
C21
10pF
VPOS
10pF
L4
470nH
R14
910Ω
VPIF
RFIN
RFCT
COMM
COMM
C6
R25
0Ω
GM
IF
VLO3
R9
1.1kΩ
R24
0Ω
IFOP
IFON
ADL5357
LO2
LGM3
V
C8
10pF
DN
W
P
LOSW
C17
150pF
VPOS
LEXT
NC
L3
0Ω
LOI2
VPSW
VGS1
VGS0
LOI1
R4
10kΩ
R1
0Ω
R21
10kΩ
VGS0
C12
22pF
LOSEL
PWR_UP
VGS1
C10
22nF
LO2_IN
C20
10pF
C22
1nF
VPOS
LO1_IN
R22
10kΩ
R23
15kΩ
8081-006
Figure 53. Evaluation Board Schematic
Rev. 0 | Page 20 of 24
ADL5357
Table 9. Evaluation Board Configuration
Components Description Default Conditions
C2, C6, C8, C18, C19,
C20, C21
C1, C4, C5
T1, C17, L4, L5,
R1, R24, R25
C10, C12, R4
R21
C22, L3, R9, R14, R22,
R23, VGS0, VGS1
Power Supply Decoupling. Nominal supply decoupling consists of
a 10 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
RF Input Interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.
IF Output Interface. The open-collector IF output interfaces are
biased through pull-up choke inductors L4 and L5. T1 is a 4:1
impedance transformer used to provide a single-ended IF output
interface, with C17 providing center-tap bypassing. Remove R1 for
balanced output operation.
LO Interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO
input for both mixer cores. R4 provides a pull-down to ensure that
LO1_IN is enabled when the LOSEL test point is logic low.
LO2_IN is enabled when LOSEL is pulled to logic high.
PWDN Interface. R21 pulls the PWDN logic low and enables the
device. The PWR_UP test point allows the PWDN interface to be
exercised using the external logic generator. Grounding the
PWDN pin for nominal operation is allowed. Using the PWDN pin
when supply voltages exceed 3.3 V is not allowed.
Bias Control. R22 and R23 form a voltage divider to provide 3 V
for logic control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins. It is
recommended to pull these two pins to ground for nominal
operation. R9 sets the bias point for the internal LO buffers.
R14 sets the bias point for the internal IF amplifier.
C2 = 10 μF (size 0603),
C6, C8, C20, C21 = 10 pF (size 0402),
C18, C19 = 100 pF (size 0402)
C1 = 8 pF (size 0402), C4 = 10 pF (size 0402),
C5 = 0.01 μF (size 0402)
T1 = TC4-1W+ (Mini-Circuits),
C17 = 150 pF (size 0402),
L4, L5 = 470 nH (size 1008),
R1, R24, R25 = 0 Ω (size 0402)
C10, C12 = 22 pF (size 0402),
R4 = 10 kΩ (size 0402)
R21 = 10 kΩ (size 0402)
C22 = 1 nF (size 0402), L3 = 0 Ω (size 0603),
R9 = 1.1 kΩ (size 0402), R14 = 910 Ω (size 0402),
R22 = 10 kΩ (size 0402), R23 = 15 kΩ (size 0402),
VGS0 = VGS1 = 3-pin shunt
Rev. 0 | Page 21 of 24
ADL5357
Figure 54. Evaluation Board Top Layer
Figure 55. Evaluation Board Ground Plane, Internal Layer 1
08081-055
08081-057
Figure 56. Evaluation Board Power Plane, Internal Layer 2
08081-056
08081-058
Figure 57. Evaluation Board Bottom Layer
Rev. 0 | Page 22 of 24
ADL5357
C
OUTLINE DIMENSIONS
0.05
0.65
BSC
0.75
0.60
0.50
0.60 MAX
15
16
10
11
20
EXPOSED
PAD
(BOTTOM VIEW)
6
2.60 BSC
FOR PROPER CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRIPTIO NS
SECTION OF THIS DATA SHEET.
N
I
1
P
R
O
T
N
D
C
I
A
I
1
3.20
3.10 SQ
3.00
5
042209-B
5.00
INDI
ATO R
0.90
0.85
0.80
SEATING
PLANE
PIN 1
12° MAX
BSC SQ
TOP VIEW
0.70
0.65
0.60
0.35
0.28
0.23
COMPLIANTTOJEDEC STANDARDS MO-220-VHHC
4.75
BSC SQ
0.20 REF
0.60 MAX
0.05 MAX
0.01 NOM
COPLANARITY
Figure 58. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad (CP-20-5)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model Temperature Range Package Description
ADL5357ACPZ-R71 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-5 1,500, 7” Tape and Reel
ADL5357ACPZ-WP1 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-5 36, Waffle Pack
ADL5357-EVALZ1 Evaluation Board 1
1
Z = RoHS Compliant Part.
Option Ordering Quantity
Rev. 0 | Page 23 of 24
ADL5357
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08081-0-7/09(0)
Rev. 0 | Page 24 of 24
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