ANALOG DEVICES ADL5356 Service Manual

1200 MHz to 2500 MHz, Dual-Balanced

Mixer, LO Buffer, IF Amplifier, and RF Balun

FEATURES

RF frequency range of 1200 MHz to 2500 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.2 dB
SSB noise figure of 9.9 dB
SSB noise figure with 5 dBm blocker of 21 dB
Input IP3 of 31 dBm
Input P1dB of 11 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP

APPLICATIONS

Cellular base station receivers
Transmit observation receivers
Radio link downconverters

GENERAL DESCRIPTION

The ADL5356 uses a highly linear, doubly balanced, passive mixer
core along with integrated RF and local oscillator (LO) balancing
circuitry to allow single-ended operation. The ADL5356
incorporates the RF baluns, allowing for optimal performance over
a 1200 MHz to 2500 MHz RF input frequency range. Performance
is optimized for RF frequencies from 1700 MHz to 2500 MHz
using a low-side LO and RF frequencies from 1200 MHz to
1700 MHz using a high-side LO. The balanced passive mixer
arrangement provides good LO-to-RF leakage, typically better
than −35 dBm, and excellent intermodulation performance. The
balanced mixer core also provides extremely high input linearity,
allowing the device to be used in demanding cellular applications
where in-band blocking signals may otherwise result in the
degradation of dynamic performance. A high linearity IF buffer
amplifier follows the passive mixer core to yield a typical power
conversion gain of 8.2 dB and can be used with a wide range of
output impedances.

The ADL5356 provides two switched LO paths that can be used
in TDD applications where it is desirable to ping-pong between
two local oscillators. LO current can be externally set using a
resistor to minimize dc current commensurate with the desired
level of performance. For low voltage applications, the ADL5356 is
capable of operation at voltages down to 3.3 V with substantially
reduced current. Under low voltage operation, an additional logic
pin is provided to power down (<300 µA) the circuit when desired.

ADL5356

FUNCTIONAL BLOCK DIAGRAM

N

M

M

S

G

M

N

O
C

M

M

M

G

M

V

O

D

C

MNIN

MNCT

COMM

VPOS

COMM

VPOS

COMM

DVCT

DVIN

O
P
V

36 35 34 33 32 31 30 29 28

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

S
O
P
V

The ADL5356 is fabricated using a BiCMOS high performance
IC process. The device is available in a 6 mm × 6 mm, 36-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.

Table 1. Passive Mixers

RF Frequency
(MHz)

Single
Mixer

500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500 ADL5365 ADL5355 ADL5356

P

O

O

N

N
M

M

P

N

O

O

V

V

D

D

Figure 1.

Single Mixer
and IF Amp

E
L
N

M

ADL5356

E
L
V
D

G

S

L

O

N

P
V

S
O
P
V

C

M

N

27

LOI2

26

VGS2

25

VGS1

24

VGS0

23

LOSW

22

PWDN

21

VPOS

20

COMM

19

LOI1

C

G
L

N
V
D

Dual Mixer
and IF Amp

07883-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADL5356

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

5 V Performance ........................................................................... 4

3.3 V Performance ........................................................................ 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

5 V Performance ........................................................................... 7

3.3 V Performance ...................................................................... 15

Spur Tables .................................................................................. 16

Circuit Description......................................................................... 17

RF Subsystem .............................................................................. 17

LO Subsystem ............................................................................. 18

Applications Information .............................................................. 19

Basic Connections ...................................................................... 19

IF Port .......................................................................................... 19

Bias Resistor Selection ............................................................... 19

Mixer VGS Control DAC .......................................................... 19

Evaluation Board ............................................................................ 21

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADL5356

SPECIFICATIONS

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 =
R5 = 1 k, Z

Table 2.

Parameter Conditions Min Typ Max Unit

RF INPUT INTERFACE

Return Loss Tunable to >20 dB over a limited bandwidth 15 dB
Input Impedance 50 Ω
RF Frequency Range 1200 2500 MHz

OUTPUT INTERFACE

Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V

LO INTERFACE

LO Power −6 0 +10 dBm
Return Loss 13 dB
Input Impedance 50 Ω
LO Frequency Range 1230 2470 MHz

POWER-DOWN (PWDN) INTERFACE2

PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 230 ns
PWDN Input Bias Current Device enabled 0 μA

Device disabled 70 μA

1

Apply supply voltage from external circuit through choke inductors.

2

PWDN function is intended for use with VS ≤ 3.6 V only.

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

Rev. 0 | Page 3 of 24

ADL5356

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k,
VGS0 = VGS1 = VGS2 = 0 V, and Z

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 7.5 8.2 8.5 dB
Voltage Conversion Gain Z
SSB Noise Figure 9.9 dB
SSB Noise Figure Under Blocking

Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 11 dBm
LO-to-IF Leakage Unfiltered IF output −24 dBm
LO-to-RF Leakage −35 dBm
RF-to-IF Isolation −33 dBc
IF/2 Spurious −10 dBm input power −75 dBc
IF/3 Spurious −10 dBm input power −73 dBc
IF Channel-to-Channel Isolation 50 dB

POWER SUPPLY

Positive Supply Voltage 4.75 5 5.25 V
Quiescent Current LO supply 170 mA
IF supply 180 mA
Total Quiescent Current VS = 5 V 350 mA

= 50 Ω, unless otherwise noted.

O

= 50 Ω, differential Z

SOURCE

5 dBm blocker present ±10 MHz from wanted RF input,
LO source filtered

= 1899.5 MHz, f

f

RF1

RF2

each RF tone at −10 dBm

= 1900 MHz, f

f

RF1

= 1950 MHz, fLO = 1697 MHz,

RF2

each RF tone at −10 dBm

= 200 Ω differential 14.5 dB

LOAD

= 1900.5 MHz, fLO = 1697 MHz,

21 dB

25 31 dBm

50 dBm

3.3 V PERFORMANCE

VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 k, R2 =
R5 = 400 , VGS0 = VGS1 = VGS2 = 0 V, and Z

Table 4.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8.3 dB
Voltage Conversion Gain Z
SSB Noise Figure 8.9 dB
Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 7 dBm

POWER INTERFACE

Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 200 mA
Total Quiescent Current Device disabled 300 μA

= 50 , unless otherwise noted.

O

= 50 Ω, differential Z

SOURCE

= 1899.5 MHz, f

f

RF1

RF2

LOAD

= 1900.5 MHz, fLO = 1697 MHz,

each RF tone at −10 dBm

= 1950 MHz, f

f

RF1

= 1900 MHz, fLO = 1697 MHz,

RF2

each RF tone at −10 dBm

= 200 Ω differential 14.6 dB

21.2 dBm

48 dBm

Rev. 0 | Page 4 of 24

ADL5356

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Supply Voltage, VS 5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
MNOP, MNON, DVOP, DVON Bias 6.0 V
VGS2,VGS1,VGS0, LOSW, PWDN 5.5 V
Internal Power Dissipation 2.2 W
θJA 22°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 24

ADL5356

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

N

M

M

P

E

S

O

G

M

O

N

N

O

P

M

C

M

V

6

5

4

3

3

3

3

3

1

MNIN

2

MNCT

3

COMM

4

VPOS

5

COMM

6

VPOS

7

COMM

DVCT

8
9

DVIN

NOTES

12. NC = NO CONNECT .
. EXPOSED P AD M US T BE CONNECTED T O GROUND.

ADL5356

TOP VIEW

(Not to S cale)

0

1

2

1

1

1

S

M

M

O

G

M

P

V

O

V

D

C

3

1

P
O
V
D

Figure 2. Pin Configuration

G

S

O

L

L

O

N

N

N

C

P

M

M

V

M

2

3

4

1

N
O
V
D

N

1

0

9

8

3

3

2

2

27

LOI2
VGS2

26

VGS1

25

VGS0

24

LOSW

23
22

PWDN

21

VPOS

20

COMM
LOI1

19

5

6

7

8

1

1

1

1

S

E

C

G

L

L

N

O

V

V

P

D

V

D

7883-002

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 MNIN RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled.
2 MNCT Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor.
3, 5, 7, 12, 20, 34 COMM Device Common (DC Ground).
4, 6, 10, 16,

VPOS Positive Supply Voltage.

21, 30, 36
8 DVCT Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.
9 DVIN RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled.
11 DVGM Diverstiy Amplifier Bias Setting. Connect 1.3 kΩ resistor to ground for typical operation.
13, 14 DVOP, DVON

Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to

VCC using external inductors.
15 DVLE Diversity Channel IF Return. This pin must be grounded.
17 DVLG Diverstiy Channel LO Buffer Bias Setting. Connect 1 kΩ resistor to ground for typical operation.
18, 28 NC No Connect.
19 LOI1 Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled.
22 PWDN

Connect to Ground for Normal Operation. Connect pin to 3 V for disable mode when using

VPOS < 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.
23 LOSW Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.
24, 25, 26 VGS0, VGS1, VGS2 Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to low logic level.
27 LOI2 Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled.
29 MNLG Main Channel LO Buffer Bias Setting. Connect 1 kΩ resistor to ground for typical operation.
31 MNLE Main Channel IF Return. This pin must be grounded.
32, 33 MNOP, MNON

Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to

VCC using external inductors.
35 MNGM Main Amplifier Bias Setting. Connect 1.3 kΩ resistor to ground for typical operation.
Paddle EPAD Exposed pad must be connected to ground.

Rev. 0 | Page 6 of 24

ADL5356

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

400

61

380

TA = –40°C

360

TA = +25°C

340

SUPPLY CURRENT (mA)

320

300

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = +85°C

RF FREQUENCY (M Hz )

Figure 3. Supply Current vs. RF Frequency

11

10

TA = –40°C

9

TA = +25°C

8

7

CONVERSION GAIN (dB)

6

TA = +85°C

59

57

55

INPUT IP2 (dBm)

53

51

49

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

7883-003

TA = +25°C

TA = +85°C

RF FREQUENCY ( MHz)

TA = –40°C

7883-006

Figure 6. Input IP2 vs. RF Frequency

13.0

12.5

12.0

TA = +85°C

11.5

11.0

10.5

INPUT P1dB (dBm)

10.0

9.5

TA = –40°C

TA = +25°C

5
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

RF FREQUENCY (MHz )

Figure 4. Power Conversion Gain vs. RF Frequency

45

40

TA = –40°C

35

30

INPUT IP3 (dBm)

25

20

15

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = +85°C

RF FREQUENCY ( M Hz )

Figure 5 .Input IP3 vs. RF Frequency

TA = +25°C

7883-004

7883-005

Rev. 0 | Page 7 of 24

9.0
1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

RF FREQUENCY ( M Hz )

Figure 7. Input P1dB vs. RF Frequency

14

13

12

11

10

9

8

SSB NOISE F IGURE (dB)

7

6

5

1700 1750 1800 1850 1900 1950 2000 2050 2100 2150 2200

TA = +25°C

TA = –40°C

RF FREQUENCY (M Hz )

TA = +85°C

Figure 8. SSB Noise Figure vs. RF Frequency

7883-007

7883-008

ADL5356

VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z

= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.

O

400

V

= 5.25V

380

360

340

SUPPLY CURRENT (mA)

320

300

–40 –20 –10–30 0 10 20 30 40 50 60 70 80

POS

V

= 5.00V

POS

V

= 4.75V

POS

TEMPERATURE ( °C)

Figure 9. Supply Current vs. Temperature

10.0

9.5

9.0

4.75V

5.00V

5.25V

07883-009

58

57

56

55

54

53

INPUT IP2 (dBm)

52

51

50

49

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

TEMPERATURE ( °C)

V

= 5.25V

POS

V

= 5.0V

POS

V

= 4.75V

POS

Figure 12. Input IP2 vs. Temperature

14

13

V

= 5.25V

12

POS

V

= 5.0V

POS

07883-012

9.5

8.0

CONVERSION GAIN (dB)

7.5

7.0
–40 –30 –20 –10 0 2010 30 40 50 60 70 80

TEMPERATURE (°C)

Figure 10. Power Conversion Gain vs. Temperature

40

38

36

V

= 5.25V

34

32

30

INPUT IP3 (dBm)

28

26

24

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

= 5.0V

V

POS

POS

V

= 4.75V

POS

TEMPERATURE (°C)

Figure 11. Input IP3 vs. Temperature

11

10

INPUT P1dB (dBm)

9

8

–40 –30 –20 –10 0 2010 30 40 50 60 70 80

07883-010

V

= 4.75V

POS

TEMPERATURE ( °C)

07883-013

Figure 13. Input P1dB vs. Temperature

12.0

11.5

11.0

10.5

10.0

9.5

9.0

8.5

SSB NOISE FIGURE (dB)

8.0

7.5

7.0
–40 –20 0

07883-011

= 5.25V

V

POS

V

POS

V

= 4.75V

= 5.0V

TEMPERATURE (°C)

POS

20

30

40 60–30 –10 10

50 70 80

07883-014

Figure 14. SSB Noise Figure vs. Temperature

Rev. 0 | Page 8 of 24