ANALOG DEVICES ADL5355 Service Manual

1200 MHz to 2500 MHz Balanced Mixer,

LO Buffer, IF Amplifier, and RF Balun

FEATURES

RF frequency range of 1200 MHz to 2500 MHz IF frequency range of 30 MHz to 450 MHz Power conversion gain: 8.4 dB SSB noise figure of 9.2 dB SSB noise figure with 5 dBm blocker of 20 dB Input IP3 of 27 dBm Input P1dB of 10.4 dBm Typical LO drive of 0 dBm Single-ended, 50 Ω RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V Exposed paddle 5 mm × 5 mm, 20-lead LFCSP 1500 V HBM/500 V FICDM ESD performance

APPLICATIONS

Cellular base station receivers Transmit observation receivers Radio link downconverters

GENERAL DESCRIPTION

The ADL5355 uses a highly linear, doubly balanced passive mixer core along with integrated RF and LO balancing circuitry to allow for single-ended operation. The ADL5355 incorporates an RF balun, allowing for optimal performance over a 1200 MHz to 2500 MHz RF input frequency range using low-side LO injection for RF frequencies from 1700 MHz to 2500 MHz and high-side LO injection for RF frequencies from 1200 MHz to 1700 MHz. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than −39 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where inband blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8.4 dB and can be used with a wide range of output impedances.

ADL5355

FUNCTIONAL BLOCK DIAGRAM

IFGM

20 19 18 17 16

1

VPIF

2

RFIN

3

RFCT

4

COMM

5

COMM

6 7 8 9 10

VLO3 LGM3 VLO2 LOSW NC

NC = NO CONNECT

The ADL5355 provides two switched LO paths that can be used in TDD applications where it is desirable to rapidly switch between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5355 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (<200 μA) the circuit when desired.

The ADL5355 is fabricated using a BiCMOS high performance IC process. The device is available in a 5 mm × 5 mm, 20-lead LFCSP and operates over a −40°C to +85°C temperature range. An evaluation board is also available.

IFOP IFON PWDN LEXT

ADL5355

BIAS

GENERATOR

Figure 1.

15

LOI2

14

VPSW

13

VGS1

12

VGS0

11

LOI1

8080-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADL5355

REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADL5355

SPECIFICATIONS

VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

RF INPUT INTERFACE

Return Loss Tunable to >20 dB over a limited bandwidth 20 dB Input Impedance 50 Ω RF Frequency Range 1200 2500 MHz

OUTPUT INTERFACE

Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF IF Frequency Range 30 450 MHz DC Bias Voltage

LO INTERFACE

LO Power −6 0 +10 dBm Return Loss 15 dB Input Impedance 50 Ω LO Frequency Range 1230 2470 MHz

POWER-DOWN (PWDN) INTERFACE

PWDN Threshold 1.0 V Logic 0 Level 0.4 V Logic 1 Level 1.4 V PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns Device disabled, supply current < 5 mA 220 ns PWDN Input Bias Current Device enabled 0.0 μA

Device disabled 70 μA

1

Apply the supply voltage from the external circuit through the choke inductors.

2

PWDN function is intended for use with VS ≤ 3.6 V only.

1

2

Externally generated 3.3 5.0 5.5 V

Rev. 0 | Page 3 of 24

ADL5355

5 V PERFORMANCE

VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 7 8.4 9.5 dB Voltage Conversion Gain Z SSB Noise Figure 9.2 dB SSB Noise Figure Under Blocking

Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 10.4 dBm LO-to-IF Leakage Unfiltered IF output −12.6 dBm LO-to-RF Leakage −39 dBm RF-to-IF Isolation −33 dBc IF/2 Spurious −10 dBm input power −69 dBc IF/3 Spurious −10 dBm input power −73 dBc

POWER SUPPLY

Positive Supply Voltage 4.5 5 5.5 V Quiescent Current LO supply, resistor programmable 100 mA IF supply, resistor programmable 90 mA Total Quiescent Current VS = 5 V 190 mA

= 50 Ω, differential Z

SOURCE

= 200 Ω differential 14.7 dB

LOAD

5 dBm blocker present ±10 MHz from wanted RF input, LO source filtered

= 1949.5 MHz, f

f

RF1

= 1950.5 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

= 1950 MHz, f

f

RF1

= 1900 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

20 dB

22 27 dBm

50 dBm

3.3 V PERFORMANCE

VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V, and Z

= 50 Ω, unless otherwise noted.

O

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Power Conversion Gain Including 4:1 IF port transformer and PCB loss 9 dB Voltage Conversion Gain Z SSB Noise Figure 8.75 dB Input Third-Order Intercept (IIP3)

Input Second-Order Intercept (IIP2)

Input 1 dB Compression Point (IP1dB) 7 dBm

POWER INTERFACE

Supply Voltage 3.0 3.3 3.6 V Quiescent Current Resistor programmable 125 mA Power-Down Current Device disabled 150 μA

= 50 Ω, differential Z

SOURCE

= 1949.5 MHz, f

f

RF1

= 1950.5 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

= 1950 MHz, f

f

RF1

= 1900 MHz, fLO = 1750 MHz,

RF2

each RF tone at −10 dBm

= 200 Ω differential 15.3 dB

LOAD

22 dBm

52 dBm

Rev. 0 | Page 4 of 24

ADL5355

SPUR TABLES

All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was only measured for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm.

5 V Performance

VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted.

Table 4.

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −10.0 −21.1 −53.8 1 −42.3 0.0 −57.1 −51.4 −75.9 2 −66.7 −65.3 −57.0 −67.0 −88.4 <−100 3 <−100 <−100 −97.6 −61.6 <−100 <−100 <−100 4 <−100 <−100 <−100 −97.9 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 14 <−100 <−100 15 <−100

3.3 V Performance

VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V, and Z

= 50 Ω, unless otherwise noted.

O

Table 5.

M

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 −15.3 −27.3 −65.5 1 −42.9 0.0 −58.3 −52.2 −78.0 2 −64.4 −67.3 −56.6 −73.6 −75.7 <−100 3 <−100 <−100 −95.5 −60.4 <−100 <−100 <−100 4 <−100 <−100 <−100 −97.0 <−100 <−100 <−100 <−100 5 <−100 <−100 <−100 <−100 <−100 <−100 <−100 6 <−100 <−100 <−100 <−100 <−100 <−100 <−100 7 <−100 <−100 <−100 <−100 <−100 <−100 <−100

N

8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 11 <−100 <−100 <−100 <−100 <−100 <−100 12 <−100 <−100 <−100 <−100 <−100 13 <−100 <−100 <−100 14 <−100 <−100 15 <−100

Rev. 0 | Page 5 of 24

ADL5355

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Supply Voltage, VS 5.5 V RF Input Level 20 dBm LO Input Level 13 dBm IFOP, IFON Bias Voltage 6.0 V VGS0, VGS1, LOSW, PWDN 5.5 V Internal Power Dissipation 1.2 W θJA 25°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature Range (Soldering, 60 sec) 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 24

ADL5355

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DN

IFON

IFOP

IFGM

20

1VPIF 2RFIN

ADL5355

3RFCT

TOP VIEW

4COMM

(Not to Scale)

5COMM

6

VLO3

NOTES

1.2 NC = NO CONNECT. . EXPOSED PAD. MUST BE SOLDERED

TO GROUND.

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 VPIF Positive Supply Voltage for IF Amplifier. 2 RFIN RF Input. Must be ac-coupled. 3 RFCT RF Balun Center Tap (AC Ground). 4, 5 COMM Device Common (DC Ground). 6, 8 VLO3, VLO2 Positive Supply Voltages for LO Amplifier. 7 LGM3 LO Amplifier Bias Control. 9 LOSW LO Switch. LOI1 selected for 0 V, and LOI2 selected for 3 V. 10 NC No Connect. 11, 15 LOI1, LOI2 LO Inputs. Must be ac-coupled. 12, 13 VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting. 14 VPSW Positive Supply Voltage for LO Switch. 16 LEXT IF Return. This pin must be grounded. 17 PWDN Power Down. Connect this pin to ground for normal operation and connect this pin to 3.0 V for disable mode. 18, 19 IFON, IFOP Differential IF Outputs (Open Collectors). Each requires an external dc bias. 20 IFGM IF Amplifier Bias Control. EPAD (EP) Exposed pad. Must be soldered to ground.

PW

17

18

19

PIN 1 INDICATOR

9

8

7

VLO2

LGM3

LOSW

LEXT

16

10

NC

15 LO I2 14 VPSW 13 VGS1 12 VGS0 11 LO I1

08080-002

Rev. 0 | Page 7 of 24

ADL5355

m

A

3

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE

VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V, and Z

= 50 Ω, unless otherwise noted.

O

240

220

)

200

180

160

SUPPLY CURRENT (

140

TA = –40°C

T

= +85°C

A

= +25°C

T

A

70

TA = –40°C

T

= +85°C

A

= +25°C

A

60

50

T

40

30

INPUT IP2 (dBm)

20

120

100

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20 RF FREQUENCY (GHz)

Figure 3. Supply Current vs. RF Frequency

20

18

16

14

12

10

8

6

CONVERSION G AIN (dB)

4

2

0

1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20

TA = –40°C

= +85°C

T

A

RF FREQUENCY ( GHz)

T

= +25°C

A

Figure 4. Power Conversion Gain vs. RF Frequency

35

TA = –40°C

30

25

20

(dBm)

15

INPUT IP

10

5

0

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20

T

= +25°C

A

T

= +85°C

A

RF FREQUENCY (GHz)

Figure 5. Input IP3 vs. RF Frequency

10

0

08080-007

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20 RF FREQUENCY (GHz)

08080-015

Figure 6. Input IP2 vs. RF Frequency

15

14

13

12

11

10

9

INPUT P1dB (dBm)

8

7

6

5

08080-011

T

= +85°C

A

TA = –40°C

1.70 1.75 1. 80 1.85 1. 90 1.95 2.00 2.05 2.10 2.15 2.20

TA = +25°C

RF FREQUENCY (GHz)

08080-023

Figure 7. Input P1dB vs. RF Frequency

20

18

16

14

= +85°C

T

12

10

8

6

SSB NOISE F IGURE (dB)

4

2

0

1.70 1.75 1.80 1.85 1. 90 1.95 2. 00 2.05 2.10 2.15 2.20

08080-019

A

TA = –40°C

RF FREQUENCY (GHz)

T

= +25°C

A

08080-033

Figure 8. SSB Noise Figure vs. RF Frequency

Rev. 0 | Page 8 of 24

ANALOG DEVICES ADL5355 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

5 V PERFORMANCE

3.3 V PERFORMANCE

SPUR TABLES

5 V Performance

3.3 V Performance

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

5 V PERFORMANCE