ANALOG DEVICES ADL5354 Service Manual
2200 MHz to 2700 MHz, Dual-Balanced
Mixer, LO Buffer, IF Amplifier, and RF
Balun
FEATURES
RF frequency range of 2200 MHz to 2700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.6 dB
SSB noise figure of 10.6 dB
Input IP3 of 26.1 dBm
Input P1dB of 10.6 dBm
Typical LO power of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
GENERAL DESCRIPTION
The ADL5354 uses a highly linear, doubly balanced, passive mixer
core along with integrated RF and local oscillator (LO) balancing
circuitry to allow single-ended operation. The ADL5354 incorporates the RF baluns, allowing for optimal performance over a
2200 MHz to 2700 MHz RF input frequency range. The balanced
passive mixer arrangement provides good LO-to-RF leakage,
typically better than −37 dBm, and excellent intermodulation
performance. The balanced mixer core also provides extremely
high input linearity, allowing the device to be used in demanding
cellular applications where in-band blocking signals may otherwise result in the degradation of dynamic performance. A high
linearity IF buffer amplifier follows the passive mixer core to yield
a typical power conversion gain of 8 dB and can be used with a
wide range of output impedances.
The ADL5354 provides two switched LO paths that can be used
in time division duplex (TDD) applications where it is desirable
to ping-pong between two local oscillators. LO current can be
externally set using a resistor to minimize dc current
ADL5354
FUNCTIONAL BLOCK DIAGRAM
N
M
M
S
G
M
N
O
C
M
35
34
11
12
M
M
G
M
V
O
D
C
MNIN
MNCT
COMM
VPOS
COMM
VPOS
COMM
DVCT
DVIN
O
P
V
36
1
2
3
4
5
6
7
8
9
10
S
O
P
V
commensurate with the desired level of performance. For low
voltage applications, the ADL5354 is capable of operation at
voltages as low as 3.3 V with substantially reduced current. For
low voltage operation, an additional logic pin is provided to
power down (~300 µA) the circuit when desired.
The ADL5354 is fabricated using a BiCMOS high performance
IC process. The device is available in a 6 mm × 6 mm, 36-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
Single
Mixer
500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500 ADL5365 ADL5355 ADL5356
2200 to 2700 ADL5353 ADL5354
P
O
O
N
N
M
M
33
32
13
14
P
N
O
O
V
V
D
D
Figure 1.
Single Mixer
and IF Amp
E
L
N
M
31
ADL5354
15
E
L
V
D
S
O
P
V
30
16
S
O
P
V
G
L
N
C
M
N
29
28
17
18
C
G
L
N
V
D
Dual Mixer
and IF Amp
27
26
25
24
23
22
21
20
19
LOI2
VGS2
VGS1
VGS0
LOSW
PWDN
VPOS
COMM
LOI1
09118-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
ADL5354
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Performance........................................................................... 4
3.3 V Performance........................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance........................................................................... 7
3.3 V Performance...................................................................... 14
Spur Tables ...................................................................................... 15
5 V Performance......................................................................... 15
3.3 V Performance...................................................................... 15
Circuit Description......................................................................... 16
RF Subsystem.............................................................................. 16
LO Subsystem ............................................................................. 16
Applications Information.............................................................. 18
Basic Connections...................................................................... 18
IF Port.......................................................................................... 18
Bias Resistor Selection ............................................................... 18
Mixer VGS Control DAC.......................................................... 18
Evaluation Board............................................................................ 20
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
2/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5354
SPECIFICATIONS
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 =
R5 = 1 k, Z
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RF INPUT INTERFACE
Return Loss Tunable to >20 dB over a limited bandwidth 20 dB
Input Impedance 50 Ω
RF Frequency Range 2200 2700 MHz
OUTPUT INTERFACE
Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage1 Externally generated 3.3 5.0 5.5 V
LO INTERFACE
LO Power −6 0 +10 dBm
Return Loss 13 dB
Input Impedance 50 Ω
LO Frequency Range 1750 2670 MHz
POWER-DOWN (PWDN) INTERFACE2
PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 230 ns
PWDN Input Bias Current Device enabled 0 µA
Device disabled 70 µA
1
Apply supply voltage from external circuit through choke inductors.
2
PWDN function is intended for use with VS ≤ 3.6 V only.
= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
O
Rev. 0 | Page 3 of 24
ADL5354
5 V PERFORMANCE
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k,
VGS0 = VGS1 = VGS2 = 0 V, and Z
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8.6 dB
Voltage Conversion Gain Z
SSB Noise Figure 10.6 dB
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
Input 1 dB Compression Point (IP1dB) 10.6 dBm
LO-to-IF Leakage Unfiltered IF output −20.7 dBm
LO-to-RF Leakage −37 dBm
RF-to-IF Isolation −34 dBc
IF/2 Spurious −10 dBm input power −73 dBc
IF/3 Spurious −10 dBm input power −71 dBc
IF Channel-to-Channel Isolation 52 dB
POWER SUPPLY
Positive Supply Voltage 4.75 5 5.25 V
Quiescent Current LO supply 170 mA
IF supply 180 mA
Total Quiescent Current VS = 5 V 350 mA
= 50 Ω, unless otherwise noted.
O
= 50 Ω, differential Z
SOURCE
= 2534.5 MHz, f
f
RF1
each RF tone at −10 dBm
= 2535 MHz, f
f
RF1
RF2
each RF tone at −10 dBm
= 200 Ω differential 14.6 dB
LOAD
= 2535.5 MHz, fLO = 2332 MHz,
RF2
= 2585 MHz, fLO = 2332 MHz,
26.1 dBm
50 dBm
3.3 V PERFORMANCE
VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, R9 = 226 , R14 = 604 , VGS0 = VGS1 = 0 V,
and Z
= 50 , unless otherwise noted.
O
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Gain Including 4:1 IF port transformer and PCB loss 8 dB
Voltage Conversion Gain Z
SSB Noise Figure 9.9 dB
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
Input 1 dB Compression Point (IP1dB) 7 dBm
POWER INTERFACE
Supply Voltage 3.0 3.3 3.6 V
Quiescent Current Resistor programmable 200 mA
Power-Down Current Device disabled 300 A
= 50 Ω, differential Z
SOURCE
= 2534.5 MHz, f
f
RF1
RF tone at −10 dBm
= 2535 MHz, f
f
RF1
RF2
tone at −10 dBm
= 200 Ω differential 14 dB
LOAD
= 2535.5 MHz, fLO = 2332 MHz, each
RF2
= 2585 MHz, fLO = 2332 MHz, each RF
17.5 dBm
49 dBm
Rev. 0 | Page 4 of 24
ADL5354
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage, VS 5.5 V
RF Input Level 20 dBm
LO Input Level 13 dBm
MNOP, MNON, DVOP, DVON Bias 6.0 V
VGS2,VGS1,VGS0, LOSW, PWDN 5.5 V
Internal Power Dissipation 2.2 W
Thermal Characteristic θJA 22°C/W
Maximum Junction Temperature 150°C
Temperature Range
Operating −40°C to +85°C
Storage −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 24
ADL5354
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
N
M
M
P
E
S
O
G
M
O
N
N
O
P
M
C
M
V
6
5
4
3
3
3
3
3
1
MNIN
2
MNCT
3
COMM
4
VPOS
5
COMM
6
VPOS
7
COMM
DVCT
8
9
DVIN
NOTES
12. NC = NO CONNECT.
. EXPOSED P AD MUST BE CONNECTED TO GRO UND.
ADL5354
TOP VIEW
(Not to Scale)
0
1
2
1
1
1
S
M
M
O
G
M
P
V
O
V
D
C
3
1
P
O
V
D
Figure 2. Pin Configuration
G
S
O
L
L
O
N
N
N
C
P
M
M
V
M
2
3
4
1
N
O
V
D
N
1
0
9
8
3
3
2
2
5
6
7
8
1
1
1
1
S
E
C
G
L
L
N
O
V
V
P
D
V
D
27
LOI2
VGS2
26
VGS1
25
VGS0
24
LOSW
23
22
PWDN
21
VPOS
20
COMM
LOI1
19
09118-002
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 MNIN RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled.
2 MNCT Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor.
3, 5, 7, 12, 20, 34 COMM Device Common (DC Ground).
4, 6, 10, 16, 21, 30, 36 VPOS Positive Supply Voltage.
8 DVCT Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.
9 DVIN RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled.
11 DVGM Diversity Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.
13, 14 DVOP, DVON
Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled up to
VCC using external inductors, see Figure 53 for details.
15 DVLE Diversity Channel IF Return. This pin must be grounded.
17 DVLG Diversity Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.
18, 28 NC No Connect. Do not connect to this pin.
19 LOI1 Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled.
22 PWDN
Power Down. Connect this pin to ground for normal operation. Connect pin to 3 V for disable
mode when using VPOS ≤ 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.
23 LOSW Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.
24, 25, 26
VGS0, VGS1,
VGS2
Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to a low logic
level.
27 LOI2 Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled.
29 MNLG Main Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.
31 MNLE Main Channel IF Return. This pin must be grounded.
32, 33 MNOP, MNON
Main Channel Differential Open-Collector Outputs. Pull up MNOP and MNON to VCC by using
external inductors, see Figure 53 for details.
35 MNGM Main Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.
EPAD Exposed Paddle. Exposed pad must be connected to ground.
Rev. 0 | Page 6 of 24
ADL5354
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z
= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
O
400
390
380
370
360
350
340
330
SUPPLY CURRENT (mA)
320
310
300
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
TA = –40°C
T
= +25°C
A
T
= +85°C
A
RF FREQUENCY ( GHz)
Figure 3. Supply Current vs. RF Frequency
12
09118-003
60
58
56
54
52
50
48
INPUT IP2 (dBm)
46
44
42
40
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
T
= +25°C
A
RF FREQUENCY ( GHz)
TA = –40°C
= +85°C
T
A
Figure 6. Input IP2 vs. RF Frequency
18
09118-006
11
10
9
8
7
CONVERSION GAIN (dB)
6
5
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
TA = –40°C
T
= +25°C
A
T
= +85°C
A
RF FREQUENCY ( GHz)
Figure 4. Power Conversion Gain vs. RF Frequency
35
30
25
T
= +25°C
20
INPUT IP3 (dBm)
15
10
A
TA = –40°C
T
= +85°C
A
16
14
12
10
INPUT P1dB (dBm)
8
6
4
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
09118-004
T
TA = –40°C
= +85°C
A
T
= +25°C
A
RF FREQUENCY ( GHz)
09118-007
Figure 7. Input P1dB vs. RF Frequency
14
13
12
11
10
9
SSB NOISE FIGURE (dB)
8
7
= +85°C
T
A
= +25°C
T
A
TA = –40°C
5
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY ( GHz)
Figure 5. Input IP3 vs. RF Frequency
09118-005
6
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY ( GHz)
Figure 8. SSB Noise Figure vs. RF Frequency
09118-008
Rev. 0 | Page 7 of 24
ADL5354
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
Z
= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
O
400
390
380
370
360
350
340
330
SUPPLY CURRENT (mA)
320
310
300
–40 806040200–20 70503010–10–30
TEMPERATURE (°C)
VS = 5.25V
= 5.00V
V
S
= 4.75V
V
S
09118-009
Figure 9. Supply Current vs. Temperature
9.4
9.2
9.0
8.8
8.6
8.4
CONVERSION GAIN (dB)
8.2
8.0
7.8
–40 806040200–20 70503010–10–30
TEMPERATURE (°C)
V
S
= 4.75V
VS = 5.25V
V
= 5.00V
S
09118-010
Figure 10. Power Conversion Gain vs. Temperature
29
28
= 5.00V
VS = 5.25V
09118-011
27
26
25
24
INPUT IP3 (dBm)
23
22
21
–40 806040200–20 70503010–10–30
V
S
= 4.75V
V
S
TEMPERATURE (°C)
Figure 11. Input IP3 vs. Temperature
53
52
51
50
49
INPUT IP2 (dBm)
48
47
46
–40 806040200–20 70503010–10–30
VS = 5.25V
= 5.00V
V
S
= 4.75V
V
S
TEMPERATURE (°C)
Figure 12. Input IP2 vs. Temperature
15
14
13
12
11
10
9
INPUT P1dB (dBm)
8
7
6
5
–40 806040200–20 70503010–10–30
VS = 5.25V
V
= 4.75V
S
TEMPERATURE (°C)
V
S
= 5.00V
Figure 13. Input P1dB vs. Temperature
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
SSB NOISE FIGURE (dB)
8.0
7.5
7.0
–40 806040200–20 70503010–10–30
VS = 5.25V
V
= 4.75V
S
TEMPERATURE (°C)
V
S
= 5.00V
Figure 14. SSB Noise Figure vs. Temperature
09118-012
09118-013
09118-014
Rev. 0 | Page 8 of 24
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