Analog Devices ADL5330 prk Datasheet
1 MHz - 3 GHz VGA with
a
60dB Gain Control Range
Preliminary Technical Data ADL5330
FEATURES
Voltage-Controlled Amplifier/Attenuator
Operating Frequency 1 MHz to 3 GHz
Optimized for Controlling Output Power
High Linearity: OIP3 31 dBm @ 900 MHz
Output Noise Floor -150 dBm/Hz @ 900 MHz
Fully-Balanced Differential Signal Path
Differential Input at 50 Ω
Wide Gain-Control Range: -34 dB to +22 dB @ 900 MHz
Linear-in-dB Gain Control Function, 20 mV/dB
Single Supply 4.75 – 6 V
APPLICATIONS
Output Power Control for Wireless Infrastructure
PRODUCT DESCRIPTION
The ADL5330 is a high-performance voltage-controlled variablegain amplifier/attenuator, for use up to 3 GHz. The signal path is
fully differential; the balanced structure minimizes distortion, and
reduces the risk of spurious feed-forward at low gains and high
frequencies due to substrate coupling. While operation between a
balanced source and load is recommended, a single-sided input is
internally converted to differential from. The input impedance is
50-Ω from INHI to INLO. The outputs will usually be coupled
into a 50-Ω grounded load via a 1:1 balun. However, the output
pins, OPHI and OPLO, may also be used separately, with some
noise degradation. A single supply of 4.75 to 6 V is required.
With a 2140 MHz W-CDMA 3GPP forward path signal, the
ADL5330 is capable of producing greater than –3 dBm output
power while maintaining ACPR greater than 55 dB, and an output
noise floor less than -144 dBm/Hz.
RF I/P
RF input, 50Ω
Three cascaded sections are used. The 50-Ω input system converts the
applied voltage to a pair of differential currents with high linearity and
good common rejection if driven by a single-sided source. The signal
currents are then applied to a proprietary voltage-controlled attenuator,
which provides precise definition of the overall gain, under the control
of the Linear-in-dB interface. Pin GAIN accepts a voltage from 0 V at
minimum gain to 1.4 V at full gain. The scaling factor is 20 mV/dB.
Optional external control of the input-stage and/or output-stage biasing
is provided using pins IPBS and OPBS respectively.
The output of the high-accuracy wideband attenuator is applied to a
differential trans-impedance output stage. Higher output power is
attainable at the lower operating frequencies by raising the supply
voltage to 6 V. When powered-down by a logic LO input on the ENBL
pin, the current consumption is < TBD µA.
The ADL5330 is available in a 24-lead (4 x 4mm) CSP package and is
specified for operation from ambient temperatures of −40°C to +85°C.
GAIN
VPS1
COM1
INHI
INLO
COM1
VPS1
VREF
ENBL VPS2
GAIN
CONTROL
Input
gm
Stage
BIAS
&
VREF
IPBS
Continuously
Variable
Attenuator
VPS2VPS2
COM2
O/P
(TZ)
Stage
VPS2
VPS2
COM2
OPHI
OPLO
COM2
VPS2
COM2COM2OPBS
Figure 1. Functional Block Diagram
RF to PA
BALUN
Rev. PrK
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use;
nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
Multiple Patents Pending
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 ©2004 Analog Devices, Inc. All Rights Reserved
Preliminary Technical Data ADL5330
ADL5330 SPECIFICATIONS
Table 1. VS = 5 V; TA = 25°C; 800 MHz < f < 2.2GHz.1:1 balun at input and output for single-ended 50 Ω match
Parameter Conditions Min Typ Max Unit
General
Usable Frequency Range 0.001 3 GHz
Nominal Input Impedance via 1:1 Single-Sided to Differential Balun 50
Nominal Output Impedance via 1:1 Differential to Single-Sided Balun 50
100 MHz
Gain Control Span +/-3 dB Gain Law Conformance 58 dB
Max Gain V
Min Gain V
Gain Control Slope 21
Input Compression Point V
Output Compression Point - P1dB V
Third-Order Intercept - OIP3 V
900 MHz
Gain Control Span +/-3 dB Gain Law Conformance 52 dB
Max Gain V
Min Gain V
Gain Control Slope 20
Input Compression Point V
Output Compression Point - P1dB V
Third-Order Intercept - OIP3 V
Output Noise Floor 20 MHz Carrier Offset, V
1900 MHz
Gain Control Span +/-3 dB Gain Law Conformance 47 dB
Max Gain V
Min Gain V
Gain Control Slope 18
Input Compression Point V
Output Compression Point - P1dB V
Third-Order Intercept - OIP3 V
Output Noise Floor 20 MHz Carrier Offset, V
2200 MHz
Gain Control Span +/-3 dB Gain Law Conformance 48 dB
Max Gain V
Min Gain V
Gain Control Slope 17
Input Compression Point V
Output Compression Point - P1dB V
Third-Order Intercept - OIP3 V
GAIN CONTROL INPUT
Gain Control Voltage Range 0
Incremental Input Resistance Pin GAIN to COM1 TBD
Full-Scale Response Time V
POWER SUPPLIES
Voltage 4.75
Current, Nominal Active V
V
Current, Disabled
Ω
Ω
= 1.4 V +23 dB
GAIN
= 0.1 V
GAIN
-35
dB
mV/dB
= 1.3 V +2 dBm
GAIN
= 1.3 V +22 dBm
GAIN
= 1.3 V +36 dBm
GAIN
= 1.4 V 22 dB
GAIN
= 0.1 V -34 dB
GAIN
mV/dB
= 1.3 V +3 dBm
GAIN
= 1.3 V +22 dBm
GAIN
= 1.3 V +31 dBm
GAIN
GAIN
= 1.3 V,
-144 dBm/Hz
Pout = -2 dBm
= 1.4 V 19 dB
GAIN
= 0.5 V -27 dB
GAIN
mV/dB
= 1.3 V +1 dBm
GAIN
= 1.3 V +17 dBm
GAIN
= 1.3 V +24 dBm
GAIN
GAIN
= 1.3 V,
-148 dBm/Hz
Pout = -7 dBm
= 1.4 V 17 dB
GAIN
= 0.5 V -31 dB
GAIN
mV/dB
= 1.3 V +1 dBm
GAIN
= 1.3 V +14 dBm
GAIN
= 1.3 V +20 dBm
GAIN
Pin GAIN
1.4 V
0 - 1.6V, to within 0.25 dB of final gain
GN
Pins VPS1, VPS2, COM1, COM2, ENBL
= 0 V
GN
= 1.4 V 240 mA
GN
ENBL = LO
TBD TBD
500
5
6
TBD mA
MΩ
ns
V
µA
REV. PrK | Page 2 of 5
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