Operation: 2.3 GHz to 4.0 GHz
Gain of 14 dB at 2.6 GHz
OIP3 of 41 dBm at 2.6 GHz
P1dB of 25.7 dBm at 2.6 GHz
Noise figure: 4.0 dB at 2.6 GHz
Power supply: 5 V
Power supply current: 90 mA typical
Internal active biasing
Thermally efficient SOT-89 package
ESD rating of ±2 kV (Class 3A)
GENERAL DESCRIPTION
The ADL5321 is a broadband, linear driver RF amplifier that
operates at frequencies from 2.3 GHz to 4.0 GHz. The device
can be used in a wide variety of wired and wireless applications,
including ISM, WLL, PCS, GSM, CDMA, and W-CDMA.
The ADL5321 operates with a 5 V supply voltage and a supply
current of 90 mA.
RF Driver Amplifier
ADL5321
FUNCTIONAL BLOCK DIAGRAM
GND
(2)
ADL5321
BIAS
12
RFINGND RFOUT
Figure 1.
The ADL5321 is fabricated on the GaAs HBT process. The
device is packaged in a low cost SOT-89 that uses an exposed
paddle for excellent thermal impedance. It operates from −40°C
to +105°C, and a fully populated evaluation board is available.
The ADL5320 is a companion part to the ADL5321 that operates at
similar performance from 400 MHz to 2700 MHz.
3
07307-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Supply Voltage, VCC 6.5 V
Input Power, 50 Ω Impedance 20 dBm
Internal Power Dissipation, Paddle Soldered 683 mW
θJC, Junction to Paddle 28.5°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 5 of 16
ADL5321
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RFIN
1
ADL5321
TOP VIEW
2
GND
(Not to Scale)
3
RFOUT
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 RFIN RF Input. This pin requires a dc blocking capacitor.
2 GND Ground. Connect this pin to a low impedance ground plane.
3 RFOUT
RF Output and Supply Voltage. DC bias is provided to this pin through an inductor that is connected
to the external power supply. RF path requires a dc blocking capacitor.
Exposed Paddle Expose Paddle. Internally connected to GND. Solder to a low impedance ground plane.
Figure 18. Noise Figure (NF) Distribution at 2.6 GHz
110
105
100
95
90
85
SUPPLY CURRENT (mA)
80
75
70
–40 –30 –20 –10010 20 30 40 50 60 70 80
5.25V
5.0V
4.75V
TEMPERATURE ( °C)
Figure 19. Supply Current vs. Temperature and Supply Voltage
07307-018
07307-019
(Using 2.6 GHz Matching Components)
35
30
25
20
15
PERCENTAGE (%)
10
5
0
13.70
13.80
13.75
13.85
13.90
13.95
GAIN (dB)
14.00
14.10
14.05
14.15
14.25
14.20
07307-017
Figure 17. Gain Distribution at 2.6 GHz
Rev. B | Page 9 of 16
ADL5321
VCC
BASIC LAYOUT CONNECTIONS
The basic connections for operating the ADL5321 are shown in
Figure 20.
Tabl e 5 lists the required matching components. Capacitors
C1, C2, C3, C4, and C7 are Murata GRM155 series (0402 size)
and Inductor L1 is a Coilcraft 0603CS series (0603 size). For all
frequency bands, the placement of C3 and C7 is critical. From
2500 MHz to 2700 MHz, the placement of C1 is also important.
Tabl e 6 lists the recommended component placement for
various frequencies.
A 5 V dc bias is supplied through L1 that is connected to RFOUT
(Pin 3). In addition to C4, 10 nF and 10 μF power supply
decoupling capacitors are also required. The typical current
consumption for the ADL5321 is 90 mA.
GND
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 21 shows the recommended land pattern for the ADL5321.
To minimize thermal impedance, the exposed paddle on the
SOT-89 package underside is soldered down to a ground plane
along with (GND) Pin 2. If multiple ground layers exist, they
should be stitched together using vias. For more information on
land pattern design and layout, refer to the AN-772 application
note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
1.80mm
C6 10µF
GND
(2)
C5 10nF
1
C4
5.56mm
0.20mm
3.48mm
ADL5321
1
L1
1
RF
C1
IN
1
SEE TABLE 5 FOR F REQUENCY SPECIFIC COMPO NENTS.
2
SEE TABLE 6 FOR RECO M M E NDE D COMPONENT S PACING.
2
λ
1
1
C7
2
1
RFIN
3
2
λ
3
λ
GND
2
RFOUT
Figure 20. Basic Connections
1
C2
2
2
λ
4
1
C3
RF
OUT
07307-026
0.86mm
1.50mm
3.00mm
0.62mm
1.27mm
07307-027
Figure 21. Recommended Land Pattern
Table 5. Recommended Components for Basic Connections
2500 to 2700 1.0 10 1.2 10 Open 9.5
3400 to 3850 10 10 1.2 10 1.0 9.5
Table 6. Matching Component Spacing
Frequency (MHz) λ1 (mils) λ2 (mils) λ3 (mils) λ4 (mils)
2500 to 2700 240 75 89 325
3400 to 3850 90 35 40 416
Rev. B | Page 10 of 16
ADL5321
A
0
G
0
S
MATCHING PROCEDURE
The ADL5321 is designed to achieve excellent gain and IP3
performance. To achieve this, both input and output matching
networks must present specific impedance to the device. The
matching components listed in Tab le 5 were chosen to provide
−14 dB input return loss while maximizing OIP3. The load-pull
plots (see Figure 22, Figure 23, and Figure 24) show the load
impedance points on the Smith chart where optimum OIP3,
gain, and output power can be achieved. These load impedance
values (that is, the impedance that the device sees when looking
into the output matching network) are listed in Tabl e 7 and Ta bl e 8
for maximum gain and maximum OIP3, respectively. The contours
show how each parameter degrades as it is moved away from
the optimum point.
From the data shown in Table 7 and Tabl e 8, it becomes clear that
maximum gain and maximum OIP3 do not occur at the same
impedance. This can also be seen on the load-pull contours in
Figure 22 through Figure 24. Therefore, output matching generally
involves compromising between gain and OIP3. In addition, the
load-pull plots demonstrate that the quality of the output
impedance match must be compromised to optimize gain and/
or OIP3. In most applications where line lengths are short and
where the next device in the signal chain presents a low input
return loss, compromising on the output match is acceptable.
To adjust the output match for operation at a different frequency or
if a different trade-off between OIP3, gain, and output impedance
is desired, the following procedure is recommended.
For example, to optimize the ADL5321 for optimum OIP3 and
gain at 2300 MHz, use the following steps:
1. Install the recommended tuning components for a 2500 MHz
to 2700 MHz tuning band, but do not install C3 and C7.
2. Connect the evaluation board to a vector network analyzer
so that input and output return loss can be viewed simultaneously.
3. Starting with the recommended values and positions for
C3 and C7, adjust the positions of these capacitors along
the transmission line until the return loss and gain are
acceptable. Push-down capacitors that are mounted on
small sticks can be used in this case as an alternative to
soldering. If moving the component positions does not
yield satisfactory results, then the values of C3 and C7
should be increased or decreased (most likely increased
in this case because the user is tuning for a lower frequency).
Repeat the process.
4. Once the desired gain and return loss are realized, OIP3
should be measured. It may be necessary to go back and
forth between return loss/gain and OIP3 measurements
(probably compromising most on output return loss) until
an acceptable compromise is achieved.
FREQ = 2.6000 GHz
IP3 MAX = 41.70dBm
AT 0.4705< 86.63
10 CONTOURS, 1.00dBm STEP
(32.00 TO 41.00dBm)
POUT MAX = 14.16dBm
T 0.6100< 136.24
10 CONTOURS, 1.00dBm STEP
(5.0
TO 14.00dBm)
T M AX = 15.02dBm
AT 0.6100< 136.24
10 CONTOURS, 1.00dBm STEP
(6.0
TO 15.00dB)
PECS: OFF
Figure 22. Load-Pull Contours, 2600 MHz
FIXED LOAD PUL L
FREQ = 3.5000 GHz
IP3 MAX = 41.37dBm
AT 0.6911< 142.11
10 CONTOURS, 1.00dBm STEP
(32.00 TO 41.00dBm)
POUT MAX = 14.96dBm
AT 0.7686< 162.58
10 CONTOURS, 1.00dBm STEP
(5.00 TO 14.00dBm)
GT MAX = 14.02dBm
AT 0.7686< 162.58
10 CONTOURS, 1.00dBm STEP
(5.00 TO 14.00dB)
SPECS: OFF
Figure 23. Load-Pull Contours, 3500 MHz
FIXED LOAD PULL
FREQ = 3.6000 GHz
IP3 MAX = 41.29dBm
AT 0.7070< 140.65
10 CONTOURS, 1.00dBm STEP
(32.00 TO 41.00dBm)
POUT MAX = 15.63dBm
AT 0.7057< 161.81
10 CONTOURS, 1.00dBm STEP
(6.00 TO 15.00dBm)
GT MAX = 13.44dBm
AT 0.7057< 161.81
10 CONTOURS, 1.00dBm STEP
(4.00 TO 13.00dB)
Figure 25 shows a plot of adjacent channel leakage ratio (ACLR)
vs. P
for the ADL5321. The signal type used is a WiMAX,
OUT
64 QAM, single carrier with a 10 MHz channel bandwidth. This
signal is generated by a WiMAX-enabled source and followed
with suitable band-pass filtering. The band-pass filter helps reduce
the adjacent and alternate channel noise and distortion out of
the signal generator down to −63 dB in the adjacent channels
and −76 dB in the alternate channels at 2.6 GHz and −60 dB
at 3.5 GHz.
Below an output power of 7 dBm, measured ADL5321 output
spectral performance is limited by the signal quality from the
signal source used (−63 dB at 2.6 GHz and −60 dB at 3.5 GHz).
At high power operation, input power to the ADL5321 is 1 dBm
for 15 dBm output power and the source ACLR is −60.2 dB. It is
expected that with a better signal source, the ADL5321 output
spectral quality improves further, especially at output power
levels ≤10 dBm. For instance, the ADL5373 quadrature modulator
measured ACLR is −69 dB for an output power of −10 dBm.
For output powers up to 10 dBm rms, the ADL5321 adds very
little distortion to the output spectrum. At 2.6 GHz, the ACLR is
−59 dB and a relative constellation error of −46.6 dB (<0.5% EVM)
at an output power of 10 dBm rms.
–60
ACLR (dB)
–70
–80
–90
–10–505101520
Figure 25. ACLR vs. P
0
–5
–10
–15
–20
–25
–30
RCE/EVM (dB)
–35
–40
–45
–50
–20–15–10–505101520
Figure 26. RCE/EVM vs. P
P
(dBm)
OUT
, WiMAX 64 QAM, 10 MHz Bandwidth, Single Carrier
OUT
3.5 GHz
2.6 GHz
P
(dBm)
OUT
, WiMAX 64 QAM, 10 MHz Bandwidth, Single Carrier
OUT
07307-025
07307-126
Rev. B | Page 12 of 16
ADL5321
HIGH TEMPERATURE OPERATION
The ADL5321 has excellent performance at temperatures above
85°C. At 105°C, the gain and P1dB decrease by 0.2 dB, the OIP3
decreases by 0.1 dB, and the noise figure increases by 0.31 dB
compared with the data at 85°C. Figure 27, Figure 28, and Figure 29
show the performance at 105°C.
16.0
15.5
15.0
14.5
14.0
13.5
GAIN (dB)
13.0
12.5
12.0
11.5
2.5002.7002.6752.6502.6252.6002.5752.5502.525
FREQUENCY (G Hz )
Figure 27. Gain vs. Frequency and Temperature, 2.5 GHz to 2.7 GHz
25°C
85°C
105°C
07307-030
42
41
40
39
38
OIP3 (dBm)
37
36
35
34
25°C
85°C
105°C
2.5002.7002.6752.6502.6252.6002.5752.5502.525
OIP3
P1dB
FREQUENCY (G Hz )
32
31
30
29
28
27
26
25
24
Figure 28. OIP3 and P1dB vs. Frequency and Temperature,
2.5 GHz to 2.7 GHz
5.5
5.0
4.5
4.0
NOISE FIGURE (dB)
3.5
3.0
2.502.702.652.602.55
FREQUENCY (G Hz )
25°C
85°C
105°C
Figure 29. Noise Figure vs. Frequency and Temperature, 2.5 GHz to 2.7 GHz
P1dB (dBm)
07307-031
07307-032
Rev. B | Page 13 of 16
ADL5321
VCC
EVALUATION BOARD
The schematic of the ADL5321 evaluation board is shown in
Figure 30. This evaluation board uses 25 mil wide traces and is
made from IS410 material (lead-free version of FR4). The
evaluation board comes tuned for operation in the 2500 MHz to
2700 MHz tuning band. Tuning options for other frequency bands
are also provided in Ta ble 9 . The recommended placement for
these components is provided in Tab le 1 0. The inputs and outputs
should be ac-coupled with appropriately sized capacitors. DC
bias is provided to the amplifier via an inductor connected to
the RFOUT pin. A bias voltage of 5 V is recommended.
GND
C6 10µF
GND
(2)
C5 10nF
C4 10pF
ADL5321
L1
C1
RF
IN
1.0pF
1
λ
C7
OPEN
2
1
RFIN
3
GND
RFOUT
9.5nH
λ
3
λ
2
λ
4
C3
1.2pF
C2
10pF
RF
OUT
07307-127
Figure 30. Evaluation Board, 2500 MHz to 2700 MHz
Table 9. Evaluation Board Configuration Options
Component Function 2500 MHz to 2700 MHz 3400 MHz to 3850 MHz
C1, C2 AC coupling capacitors C1 = 0402, 1.0 pF C1 = 0402, 10 pF
C2 = 0402, 10 pF C2 = 0402, 10 pF
C4, C5, C6 Power supply bypassing capacitors C4 = 0603, 10 pF C4 = 0603, 10 pF
C5 = 0603, 10 nF C5 = 0603, 10 nF
C6 = 1206, 10 μF C6 = 1206, 10 μF
L1 DC bias inductor 0603, 9.5 nH 0603, 9.5 nH
C3, C7 Tuning capacitors C3 = 0402, 1.2 pF C3 = 0402, 1.2 pF
C7 = 0402, open C7 = 0402, 1.0 pF
VCC, GND Power supply connections VCC, red test loop VCC, red test loop
GND, black test loop GND, black test loop
Table 10. Recommended Component Spacing on Evaluation Board
Frequency (MHz) λ1 (mils) λ2 (mils) λ3 (mils) λ4 (mils)
2500 to 2700 240 75 89 325
3400 to 3850 90 35 40 416
Rev. B | Page 14 of 16
ADL5321
10µF
C1
1.0 pF
(2)
2
1
3
9.5 nH
10 nF
10 pF
C2
10pF
C3
1.2 pF
Figure 31. Evaluation Board Layout and Default Component Placement for
Operation from 2500 MHz to 2700 MHz (Note: C7 Is Not Placed)
10µF
C1
10 pF
(2)
2
1
C3
1.2 pF
3
9.5 nH
10 nF
10 pF
C2
10 pF
C7
07307-028
07307-029
Figure 32. Evaluation Board Layout and Component Placement for
Operation from 3400 MHz to 3850 MHz
Rev. B | Page 15 of 16
ADL5321
OUTLINE DIMENSIONS
*
1.75
1.55
4.25
3.94
1.50 TYP
(2)
12
3.00 TYP
4.60
4.40
*
0.56
0.36
*
COMPLIANT TO JEDEC STANDARDS TO-243 WITHTHE
EXCEPTION OF DIMENSIONS INDICATED BY AN ASTERISK.
2.60
2.30
3
1.20
0.75
2.29
2.14
0.44
0.35
*
0.52
0.32
END VIEW
1.60
1.40
12-18-2008-B
Figure 33. 3-Lead Small Outline Transistor Package [SOT-89]
(RK-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADL5321ARKZ-R7 −40°C to +105°C 3-Lead SOT-89, 7“ Tape and Reel RK-3
ADL5321-EVALZ Evaluation Board