Analog Devices ADL5317 pre Datasheet

Avalanche Photodiode Bias Controller and

Wide-range (5 nA - 5 mA) Current Monitor

PRELIMINARY TECHNICAL DATA

FEATURES

Accurately sets avalanche photodiode bias voltage

Wide bias range from 6 V to 75 V set Using 3V-compatible control interface

Monitors photodiode current (5:1 ratio) over 6 decades

Linearity 0.5% from 10 nA to 1 mA, 1% from 5 nA to 5 mA

Over-current protection and over-temperature shutdown

Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm)

APPLICATIONS

Optical power monitoring and biasing in APD systems Wide dynamic range voltage sourcing and current

monitoring in high-voltage systems

GENERAL DESCRIPTION

The ADL5317 is a high-voltage, wide dynamic range biasing and current monitoring device optimized for use with avalanche photodiodes. With the provision of a stable high-voltage supply up to 80 V, the bias voltage at the VAPD pin can be varied from 6 V to 75 V using the 3 V-compatible VSET pin. The current sourced from the VAPD pin, over a range of 5 nA to 5 mA, is accurately mirrored with an attenuation of 5 and sourced from the IPDM monitor output. In a typical application, the monitor output drives a current-input logarithmic amplifier to produce an output representing the optical power incident upon the photodiode. The photodiode anode may be connected to a high-speed transimpedance amplifier for the extraction of the data stream.

A signal applied at the VSET pin of 0.2 V to 2.5 V with respect to COMM is amplified by a fixed gain of 30 to produce the 6 V to 75 V bias at pin VAPD. The accuracy of the ADL5317’s bias control interface allows for straightforward calibration to maintain constant avalanche multiplication factor of the photodiode over temperature. The current monitor output, IPDM, maintains its high linearity versus photodiode current over the full range of APD bias voltage. The current ratio of 5:1 remains constant as VSET and VPHV are varied.

ADL5317

FUNCTIONAL BLOCK DIAGRAM

COMM

FALT

Overcurrent

Protection

Thermal

Protection

VSET

30 V

VPLV

VPHV VCL H

Figure 1. Functional Block Diagram

The ADL5317 also offers a supply tracking mode for compatibility with adjustable high voltage supplies. The VAPD pin accurately follows 2.0 V below the VPHV supply pin when VSET is tied to a voltage from 3 V to 5.5 V (or higher with current limiting resistor) and the VCLH pin is open.

Protection from excessive input current at VAPD and excessive die temperature is provided. The voltage at VAPD falls rapidly from its setpoint when the input current exceeds 18 mA nominally. A die temperature in excess of 140°C will cause the bias controller and monitor to shut down until the temperature falls below 120°C. Either overstress condition will trigger a logic low at the FALT pin, an open-collector output loaded by an external pull-up to an appropriate logic supply (1 mA max.).

The ADL5317 is available in a 16-lead LFCSP package and is specified for operation from −40°C to +85°C.

29 R

SET

GARD VAPD

Current

Mirror

5:1

IPDM

APD

Rev. PrE

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective companies.

ADL5317 PRELIMINARY TECHNICAL DATA

Rev. PrE | Page 2 of 11

ADL5317—Specifications

Table 1. V

= 78 V, V

PHV

PLV

= 5 V, I

= 5 µA, TA = 25°C, unless otherwise noted

APD

Parameter Conditions Min Typ Max Unit

CURRENT MONITOR OUTPUT

Current Gain from VAPD to IPDM

Wideband Noise at IPDM

APD BIAS CONTROL

Voltage Range of V

APD

Specified Input Current Range, I Incremental Gain from VSET to VAPD VSET Voltage Range Incremental Input Resistance at VSET Input Bias Current at VSET

Settling Time, 5%

APD

Supply Tracking Offset (below V

APD

OVERSTRESS PROTECTION

VAPD Current Compliance Limit

APD

IPDM (Pin 11)

−40°C < TA < +85°C 10 nA < I 5 nA < I I

= 5 nA 2 kHz Small-signal Bandwidth

APD

= 5 µA

APD

= 5 µA, C

APD

< 1 mA 0.5 TBD % Nonlinearity

APD

< 5 mA 1 TBD %

APD

= 1 nF

GRD

> 3 V

PLV

< 3 V

PLV

VSET (Pin 2), VAPD (Pin 8) 10 V < V

41 V < V

76.5V < V

< 41 V 6 V

PHV

< 76.5 V V

PHV

< 80 V V

PHV

Flows from VAPD pin

0.2 V < V

< 2.4 V TBD 30 TBD V/V

SET

0.2 5.5 V V

= 2.0 V 50 MOhms

SET

= 2.0 V 0.3

SET

PHV

) V

= 1.6 V to 2.4 V, C

SET

= 2.4 V to 1.6 V, C

SET

= 5.0 V, 10 V < V

SET

= 1 nF 20

GRD

= 1 nF 150

GRD

< 77 V TBD 2.0 TBD V

PHV

FALT (Pin 1) V

= 2.0 V, V

SET

deviation of 500 mV TBD 18 TBD mA

APD

Thermal Shutdown Trip Point Die temperature rising 140

Thermal Hysteresis 20

FALT Output Low Voltage

POWER SUPPLIES

Low Voltage Supply

Quiescent Current Independent of I

High Voltage Supply

Quiescent Current

Fault condition, Load current < 1 mA 0.8 V

VPHV (Pin 4, 5), VPLV (Pin 3) VPLV

APD

VPHV

= 5 µA, V

APD

= 1 mA, V

APD

=60 V

APD

= 60 V 3.3 TBD mA

APD

TBD 0.200 TBD A/A

2 MHz

13 nArms

0 V 0 V

PLV

APD

V Output Voltage Range

/ 3 V

–1.5 V

PHV

–35 V

PHV

–35 75 V

PHV

–1.5 V

PHV

5n 5m A

µA

µsec

°C

4 6 V

0.7 TBD mA 10 80 V

2.0 TBD mA

ADL5317 PrE 02/27/2005

PRELIMINARY TECHNICAL DATA ADL5317

Rev. PrE | Page 3 of 11

ABSOLUTE MAXIMUM RATINGS

Table 2. ADL5317 Absolute Maximum Ratings

Parameter Rating

Supply Voltage Input Current at VAPD Internal Power Dissipation

(soldered exposed paddle)

Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec)

80 V 25 mA 615 mW

65°C/W

125°C

–40°C to +85°C

–65°C to +150°C 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ADL5317 PrE 02/27/2005

ADL5317 PRELIMINARY TECHNICAL DATA

Rev. PrE | Page 4 of 11

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1 2 3 4, 5 6 7,9

FALT VSET VPLV VPHV VCLH GARD

Indicates over-current or over-temperature condition. Open collector; active low. APD Bias Voltage Setting Input. Short to VPLV for supply tracking mode. Low Voltage Supply, 4 V to 6 V High Voltage Supply, 10 V to 80 V. May be shorted to VPHV for extended linear operating range. No connect for supply tracking mode. Guard pin tracks VAPD pin and filters setpoint buffer noise (with extenal capacitor C

shielding of VAPD trace. Capacitive load only.

8 10 11 12 13–16

VAPD N/C IPDM N/C COMM

APD Bias Voltage Output and Current Input. Sources current only. Optional shielding of IPDM trace. No connection to die. Photodiode Monitor Current Output. Sources current only. Current at this node is equal to I Optional shielding of IPDM trace. No connection to die. Analog Ground.

FALT

VSET

ADL5317

VPLV

VPHV

Figure 2. 16-Lead Leadframe Chip Scale Package (LFCSP)

N/C

IPDM

N/C

GARD

to COMM). Optional

GRD

/5.

APD

ADL5317 PrE 02/27/2005

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