Accurately sets avalanche photodiode (APD) bias voltage
Wide bias range from 6 V to 75 V
3 V-compatible control interface
Monitors photodiode current (5:1 ratio) over six decades
Linearity 0.25% from 10 nA to 1 mA, 0.5% from 5 nA to 5 mA
Overcurrent protection and overtemperature shutdown
Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm)
APPLICATIONS
Optical power monitoring and biasing in APD systems
Wide dynamic range voltage sourcing and current
monitoring in high voltage systems
GENERAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
COMM16COMM15COMM14COMM
FALT
1
2
3
4
OVERCURRENT
PROTECTION
VSET
VPLV
VPHV
VPHV VCLH
5
PROTECTION
THERMAL
6
30 × V
SET
29 × R
R
GARDVAPD
Figure 1.
7
ADL5317
1313
ADL5317
CURRENT
MIRROR
5:1
I
APD
8
NC
IPDM
I
APD
5
NC
GARD
12
11
10
9
05456-001
The ADL5317 is a high voltage, wide dynamic range, biasing
and current monitoring device optimized for use with
avalanche photodiodes. When used with a stable high voltage
supply (up to 80 V), the bias voltage at the VAPD pin can be
varied from 6 V to 75 V using the 3 V-compatible VSET pin.
The current sourced from the VAPD pin over a range of 5 nA to
5 mA is accurately mirrored with an attenuation of 5 and
sourced from the IPDM monitor output. In a typical
application, the monitor output drives a current input
logarithmic amplifier to produce an output representing the
optical power incident upon the photodiode. The photodiode
anode can be connected to a high speed transimpedance
amplifier for the extraction of the data stream.
A signal of 0.2 V to 2.5 V with respect to ground applied at the
VSET pin is amplified by a fixed gain of 30 to produce the 6 V
to 75 V bias at Pin VAPD. The accuracy of the bias control
interface of the ADL5317 allows for straightforward calibration,
thereby maintaining a constant avalanche multiplication factor
of the photodiode over temperature. The current monitor
output, IPDM, maintains its high linearity vs. photodiode
current over the full range of APD bias voltage. The current
ratio of 5:1 remains constant as V
SET
and V
are varied.
PHV
The ADL5317 also offers a supply tracking mode compatible
with adjustable high voltage supplies. The VAPD pin accurately
follows 2.0 V below the VPHV supply pin when VSET is tied to
a voltage from 3.0 V to 5.5 V (or higher with a current limiting
resistor), and the VCLH pin is open.
Protection from excessive input current at VAPD as well as
excessive die temperature is provided. The voltage at VAPD falls
rapidly from its setpoint when the input current exceeds 18 mA
nominally. A die temperature in excess of 140°C will cause the
bias controller and monitor to shut down until the temperature
falls below 120°C. Either overstress condition will trigger a logic
low at the FALT pin, an open collector output loaded by an
external pull-up to an appropriate logic supply (1 mA max).
The ADL5317 is available in a 16-lead LFCSP package and is
specified for operation from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VAPD to GARD Offset 3 mV
Specified Input Current Range, I
VSET to VAPD Incremental Gain 29.7 30 30.3 V/V 0.2 V < V
VSET Input Referred Offset, 1σ 0.5 mV
VSET Voltage Range 0.2 5.5 V
Incremental Input Resistance at VSET 100 MΩ V
Input Bias Current at VSET 0.3 µA V
V
Settling Time, 5%
APD
V
Supply Tracking Offset (Below V
APD
OVERSTRESS PROTECTION FALT (Pin 1)
VAPD Current Compliance Limit 14 18 21 mA V
Thermal Shutdown Trip Point 140
Thermal Hysteresis 20
FALT Output Low Voltage 0.8 V Fault condition, load current < 1 mA
POWER SUPPLIES
Low Voltage Supply 4 6 V VPLV
Quiescent Current 0.7 0.84 mA Independent of I
High Voltage Supply 10 80 V VPHV
Quiescent Current 2.3 2.9 mA I
3.6 4.5 mA I
1
Tested 1.5 V < V
= 5 V, V
PLV
Voltage Operating Range
APD
< 2.5 V, guaranteed operation 0.2 V < V
SET
APD
= 60 V, I
APD
= 5 A, TA = 25°C, unless otherwise noted.
APD
)
PHV
IPDM (Pin 11)
0.198 0.200 0.202 A/A
0.25 1.6 % 10 nA < I
0.5 3.0 % 5 nA < I
2 kHz I
2 MHz I
10 nA
0 V
0 V
6 V
V
− 35 V
PHV
V
− 35 75 V 76.5 V < V
PHV
PLV
/ 3 V
APD
− 1.5 V 10 V < V
PHV
− 1.5 V 41 V < V
PHV
V
= 25°C
T
A
−40°C < T
APD
= 5 nA, V
APD
= 5 µA, V
APD
= 5 µA, C
I
APD
= 40 V, V
V
PHV
V
> 3 × V
APD
V
< 3 × V
APD
< +85°C
A
< 1 mA Nonlinearity
APD
< 5 mA
= 60 V, V
PHV
= 60 V, V
PHV
= 2 nF, BW = 10 MHz,
GRD
= 30 V
APD
PLV
PLV
< 41 V
PHV
< 76.5 V
PHV
< 80 V
PHV
= 30 V Small-Signal Bandwidth
APD
= 30 V
APD
5n 5m A Flows from VAPD pin
1
< 2.5 V
SET
= 2.0 V
SET
= 2.0 V, flows from VSET pin
SET
20 sec
100 sec
1.90 2.0 2.15 V V
°C
°C
< 2.5 V.
SET
= 1.6 V to 2.4 V, C
V
SET
= 30 V
V
APD
= 2.4 V to 1.6 V, C
V
SET
= 30 V
V
APD
= 5.0 V, 10 V < V
SET
= 2.0 V, V
SET
APD
= 2 nF, V
GRD
= 2 nF, V
GRD
< 77 V
PHV
deviation of 500 mV
Die temperature rising
VPHV (Pin 4, Pin 5), VPLV (Pin 3)
APD
= 5 A, V
APD
= 1 mA, V
APD
= 60 V
APD
APD
= 60 V
= 60 V,
PHV
= 60 V,
PHV
Rev. 0 | Page 3 of 16
ADL5317
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 80 V
Input Current at VAPD 25 mA
Internal Power Dissipation 615 mW
θJA (Soldered Exposed Paddle)
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C
65°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 16
ADL5317
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMM
COMM
COMM
COMM
14
13
15
16
PIN 1
INDICATOR
1FALT
2VSET
ADL5317
3VPLV
TOP VIEW
(Not to Scale)
4VPHV
5
6
VPHV
VCLH
NC = NO CONNECT
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 FALT Open Collector (Active Low) Logic Output. Indicates an overcurrent or overtemperature condition.
2 VSET APD Bias Voltage Setting Input. Short to VPLV for supply tracking mode.
3 VPLV Low Voltage Supply, 4 V to 6 V.
4, 5 VPHV High Voltage Supply, 10 V to 80 V.
6 VCLH Can be shorted to VPHV for extended linear operating range. No connect for supply tracking mode.
7, 9 GARD
Guard pin tracks VAPD pin and filters setpoint buffer noise (with External Capacitor C
shielding of VAPD trace. Capacitive load only.
8 VAPD APD Bias Voltage Output and Current Input. Sources current only.
10, 12 NC Optional shielding of IPDM trace. No connection to die.
11 IPDM Photodiode Monitor Current Output. Sources current only. Current at this node is equal to I
13 to 16 COMM Analog Ground.
12 NC
11 IPDM
10 NC
9 GARD
8
7
VAPD
GARD
05456-002
to COMM). Optional
GRD
/5.
APD
Rev. 0 | Page 5 of 16
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