Tight orthogonal alignment: 0.05°
Triaxis digital accelerometer: ±18 g
Delta-angle/velocity calculations
Wide sensor bandwidth: 330 Hz
High sample rate: 2.460 kSPS
Autonomous operation and data collection
No external configuration commands required
Startup time: 500 ms
Factory-calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +85°C
SPI-compatible serial interface
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
4 FIR filter banks, 120 configurable taps
Digital I/O: data-ready, alarm indicator, external clock
Alarms for condition monitoring
Power-down/sleep mode for power management
Enable external sample clock input: up to 2.25 kHz
Single-command self test
Single-supply operation: 3.3 V
2000 g shock survivability
Operating temperature range: −40°C to +85°C
APPLICATIONS
Precision instrumentation
Platform stabilization and control
Industrial vehicle navigation
Downhole instrumentation
Robotics
ADIS16375
FUNCTIONAL BLOCK DIAGRAM
TEMPERATURE
SENSOR
TRIAXIS MEMS
ANGULAR RATE
SENSOR
TRIAXIS MEMS
ACCELERATIO N
SENSOR
SELF-TEST
ADIS16375
SIGNAL
CONDITIO NING
AND
CONVERSION
DIGITAL
CONTROL
RST
CALIBRATION
DIGITAL
PROCESSING
ALARMS
DIO3DIO2DIO1
Figure 1.
AND
DIO4
OUTPUT
REGISTERS
AND SPI
INTERFACE
POWER
MANAGEMENT
GENERAL DESCRIPTION
The ADIS16375iSensor® is a complete inertial system that includes
a triaxis gyroscope and triaxis accelerometer. Each sensor in the
ADIS16375 combines industry-leading iMEMS® technology
with signal conditioning that optimizes dynamic performance.
The factory calibration characterizes each sensor for sensitivity,
bias, alignment, and linear acceleration (gyro bias). As a result,
each sensor has its own dynamic compensation formulas that
provide accurate sensor measurements over a temperature
range of −40°C to +85°C.
The ADIS16375 provides a simple, cost-effective method for
integrating accurate, multiaxis, inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation systems.
An improved SPI interface and register structure provide faster
data collection and configuration control.
This compact module is approximately 44 mm × 47 mm × 14 mm
and provides a flexible connector interface that enables multiple
mounting orientation options.
CS
SCLK
DIN
DOUT
VDDRTC
VCC
GND
09389-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Parameter Test Conditions/Comments Min Typ Max Unit
GYROSCOPES
Dynamic Range ±300 ±350 °/sec
Sensitivity1 16-bit resolution, x_GYRO_OUT registers only 0.01311 °/sec/LSB
Initial Sensitivity Tolerance ±1 %
Sensitivity Temperature Coefficient −40°C ≤ TA ≤ +85°C ±40 ppm/°C
Misalignment Axis-to-axis ±0.05 Degrees
Axis-to-frame (package) ±1.0 Degrees
Nonlinearity Best-fit straight line ±0.025 % of FS
Initial Bias Error ±1 σ ±1.0 °/sec
In-Run Bias Stability 1 σ 12 °/hr
Angular Random Walk 1 σ 1.0 °/√hr
Bias Temperature Coefficient −40°C ≤ TA ≤ +85°C ±0.005 °/sec/°C
Linear Acceleration Effect on Bias Any axis, 1 σ (GEN_CONFIG[7] = 1) ±0.013 °/sec/g
Output Noise No filtering 0.45 °/sec rms
Rate Noise Density f = 25 Hz, no filtering 0.02 °/sec/√Hz rms
3 dB Bandwidth 330 Hz
Sensor Resonant Frequency 14.5 kHz
ACCELEROMETERS Each axis
Dynamic Range ±18
Sensitivity1 16-bit resolution, x_ACCL_OUT registers only 0.8192 mg/LSB
Initial Sensitivity Tolerance ±1 %
Sensitivity Temperature Coefficient −40°C ≤ TA ≤ +85°C ±25 ppm/°C
Misalignment Axis-to-axis ±0.035 Degrees
Axis-to-frame (package) ±1.0 Degrees
Nonlinearity Best-fit straight line, ±10 g ±0.1 % of FS
Best-fit straight line, ±18 g ±0.5 % of FS
Initial Bias Error ±1 σ ±16 mg
In-Run Bias Stability 1 σ 0.13 mg
Velocity Random Walk 1 σ 0.076 m/sec/√hr
Bias Temperature Coefficient −40°C ≤ TA ≤ +85°C ±0.1 mg/°C
Output Noise No filtering 1.5 mg rms
Noise Density No filtering 0.06 mg/√Hz rms
3 dB Bandwidth 330 Hz
Sensor Resonant Frequency 5.5 kHz
TEMPERATURE SENSOR
Scale Factor Output = 0x0000 at 25°C (±5°C) 0.00565 °C/LSB
LOGIC INPUTS2
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
CS Wake-Up Pulse Width
Logic 1 Input Current, IIH V
Logic 0 Input Current, IIL V
All Pins Except RST
RST Pin
Input Capacitance, CIN 10 pF
DIGITAL OUTPUTS
Output High Voltage, VOH I
Output Low Voltage, VOL I
20 μs
= 3.3 V 10 μA
IH
= 0 V
IL
10 μA
0.33 mA
= 0.5 mA 2.4 V
SOURCE
= 2.0 mA 0.4 V
SINK
g
Rev. B | Page 3 of 28
ADIS16375
Parameter Test Conditions/Comments Min Typ Max Unit
FLASH MEMORY Endurance3 100,000 Cycles
Data Retention4 T
FUNCTIONAL TIMES5 Time until data is available
Power-On Startup Time 500 ms
Reset Recovery Time 500 ms
Sleep Mode Recovery Time 500 μs
Flash Memory Update Time 375 ms
Flash Memory Test Time 50 ms
Automatic Self Test Time Using internal clock, 100 SPS 10 ms
POWER SUPPLY, VDD Operating voltage range 3.0 3.6 V
Power Supply Current7 Normal mode, VDD = 3.3 V 173 mA
Sleep mode, VDD = 3.3 V 12.3 mA
Power-down mode, VDD = 3.3 V 120 μA
POWER SUPPLY, VDDRTC Operating voltage range 3.3 V
Real-Time Clock Supply Current Normal mode, VDDRTC = 3.3 V 13 μA
1
Each gyroscope and accelerometer has 32 bits of available resolution. The 16-bit sensitivity shown reflects the register that contains the upper 16 bits of the sensor
output. Divide this number by 2 for every bit added to this resolution in downstream processing routines.
2
The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant.
3
Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.
4
The data retention lifetime equivalent is at a junction temperature (TJ) of 85°C as per JEDEC Standard 22, Method A117. Data retention lifetime decreases with junction
temperature.
5
These times do not include thermal settling and internal filter response times (330 Hz bandwidth), which may affect overall accuracy.
6
The 0.7 kHz lower limit is established to support Nyquist sampling criteria for the 330 Hz sensor bandwidth.
7
During startup, the power supply current increases and experiences transient behaviors for a period of 400 μs. The peak current during the 400 μs transient period can
reach 1500 mA.
= 85°C 20 Years
J
Rev. B | Page 4 of 28
ADIS16375
C
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
Parameter Description Min1 Typ Max Unit
f
Serial clock 0.01 15 MHz
SCLK
t
Stall period between data 2 μs
STALL
t
Serial clock low period 31 ns
CLS
t
Serial clock high period 31 ns
CHS
tCS Chip select to clock edge 32 ns
t
DOUT valid after SCLK edge 10 ns
DAV
t
DIN setup time before SCLK rising edge 2 ns
DSU
t
DIN hold time after SCLK rising edge 2 ns
DHD
tDR, tDF DOUT rise/fall times, ≤100 pF loading 3 8 ns
t
t
SFS
DSOE
high after SCLK edge
CS
assertion to data out active
CS
tHD SCLK edge to data out invalid 0 ns
t
DSHI
t
1
t
2
t
3
1
Guaranteed by design and characterization but not tested in production.
deassertion to data out high impedance
CS
Input sync pulse width 5 μs
Input sync to data-ready output 490 μs
Input sync period 500 μs
Timing Diagrams
32 ns
0 11 ns
0 9 ns
CS
SCLK
DOUT
DIN
CS
SCLK
t
t
CS
1234561516
t
DSOE
MSBDB14
R/WA5A6A4A3A2
t
DAV
t
DSU
CHS
t
HD
DB13DB12DB10DB11DB2LSBDB1
t
DHD
t
CLS
D2
Figure 2. SPI Timing and Sequence
t
STALL
Figure 3. Stall Time and Data Rate
SYNC
LOCK (CLKIN)
DATA
READY
OUTPUT
REGISTERS
t
3
t
1
DATA VALIDDATA VALID
t
2
Figure 4. Input Clock Timing Diagram
Rev. B | Page 5 of 28
D1LSB
09389-004
t
SFS
t
DSHI
09389-002
09389-003
ADIS16375
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Acceleration
Any Axis, Unpowered 2000 g
Any Axis, Powered 2000 g
VCC to GND −0.3 V to +3.6 V
Digital Input Voltage to GND −0.3 V to +3.6 V
Digital Output Voltage to GND −0.3 V to +3.6 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
1
Extended exposure to temperatures outside the specified temperature
range of −40°C to +85°C can adversely affect the accuracy of the factory
calibration. For best accuracy, store the parts within the specified operating
range of −40°C to +85°C.
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Package Characteristics
Package Type θJA θJC Device Weight
24-Lead Module (ML-24-3) 20.5 6.3 25 g
ESD CAUTION
Rev. B | Page 6 of 28
ADIS16375
A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DIS16375
TOP VIEW
(Not to Scale)
DIO4
DOUT
CS
RST
VDD
VDD
GND
DNC
DNC
DNC
DNC
DNC
10
12
14
16
18
20
22
24
2
11
13
15
17
19
21
23
DNC
VDDRTC
NOTES
1. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT
FOR THE MATI NG SO CKET CO NNECTO R.
2. THE ACTUAL CONNECTOR PI NS ARE NOT VI SIBLE FROM
THE TOP VIEW .
3. MATING CONNECTOR: S AMTEC CLM-112- 02 OR EQUIVAL ENT.
4. DNC = DO NOT CONNECT.
GND
DNC
DNC
VDD
GND
DIO2
3456789
1
DIN
DIO1
DIO3
SCLK
09389-005
Figure 5. Mating Connector Pin Assignments
PIN 23
PIN 1
09389-006
Figure 6. Axial Orientation (Top Side Facing Up)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Typ e Description
1 DIO3 Input/Output Configurable Digital Input/Output.
2 DIO4 Input/Output Configurable Digital Input/Output.
3 SCLK Input SPI Serial Clock.
4 DOUT Output SPI Data Output. Clocks output on SCLK falling edge.
5 DIN Input SPI Data Input. Clocks input on SCLK rising edge.
6
CS
Input SPI Chip Select.
7 DIO1 Input/Output Configurable Digital Input/Output.
8
RST
Input Reset.
9 DIO2 Input/Output Configurable Digital Input/Output.
10, 11, 12 VDD Supply Power Supply.
13, 14, 15 GND Supply Power Ground.
16 to 22, 24 DNC Not applicable Do Not Connect.
23 VDDRTC Supply Real-Time Clock Power Supply.
Rev. B | Page 7 of 28
ADIS16375
TYPICAL PERFORMANCE CHARACTERISTICS
1000
100
AVERAGE
0.001
AVERAGE
+1σ
10
ALLAN VARIANCE (°/ Hour)
1
0.010.1110100100010000
INTEGRATION PERIOD (Seconds)
Figure 7. Gyroscope Allan Variance, +25°C
+1σ
–1σ
0.0001
ALLAN VARIANCE ( g)
0.00001
0.010.1110100100010000
09389-007
INTEGRATION PERIOD (Seconds)
–1σ
09389-008
Figure 8. Accelerometer Allan Variance, 25°C
Rev. B | Page 8 of 28
ADIS16375
BASIC OPERATION
The ADIS16375 is an autonomous sensor system that starts up
on its own when it has a valid power supply. After running through
its initialization process, it begins sampling, processing, and
loading calibrated sensor data into the output registers, which
are accessible using the SPI port. The SPI port typically connects to
a compatible port on an embedded processor, using the connection
diagram in Figure 9. The four SPI signals facilitate synchronous,
serial data communication. Connect
RST
Tabl e 5
(see ) to VDD
or leave it open for normal operation. The factory default
configuration provides users with a data-ready signal on the
DIO2 pin, which pulses high when new data is available in the
output data registers.
VDD
SYSTEM
PROCESSOR
SPI MASTER
I/O LI NES ARE COMPATIBLE WI TH
3.3V LOG IC LEVE LS
SS
SCLK
MOSI
MISO
IRQDIO2
Figure 9. Electrical Connection Diagram
6
3
5
4
9
10
CS
SCLK
DIN
DOUT
131415
+3.3V
111223
ADIS16375
09389-010
Table 6. Generic Master Processor Pin Names and Functions
Embedded processors typically use control registers to configure
their serial ports for communicating with SPI slave devices,
such as the ADIS16375. Tabl e 7 provides a list of settings, which
describe the SPI protocol of the ADIS16375. The initialization
routine of the master processor typically establishes these settings
using firmware commands to write them into its serial control
registers.
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
Master The ADIS16375 operates as a slave.
SCLK ≤ 15 MHz Maximum serial clock rate.
SPI Mode 3 CPOL = 1 (polarity), and CPHA = 1 (phase).
MSB-First Mode Bit sequence.
16-Bit Mode Shift register/data length.
REGISTER STRUCTURE
The register structure and SPI port provide a bridge between
the sensor processing system and an external, master processor.
It contains both output data and control registers. The output
data registers include the latest sensor data, a real-time clock, error
flags, alarm flags, and identification data. The control registers
include sample rate, filtering, input/output, alarms, calibration,
and diagnostic configuration options. All communication
between the ADIS16375 and an external processor involves
either reading or writing to one of the user registers.
TRIAXIS
GYRO
TRIAXIS
ACCEL
TEMP
SENSOR
CONTROLL ER
Figure 10. Basic Operation
DSP
The register structure uses a paged addressing scheme that is
comprised of 13 pages, with each one containing 64 register
locations. Each register is 16-bits wide, with each byte having its
own unique address within that page’s memory map. The SPI
port has access to one page at a time, using the bit sequences in
Figure 15. Select the page to activate for SPI access by writing its
code to the PAGE_ID register. Read the PAGE_ID register to
determine which page is currently active. Ta b le 8 displays the
PAGE_ID contents for each page, along with their basic function.
The PAGE_ID register is located at Address 0x00 on every page.
Calibration
Control: sample rate, filtering, I/O, alarms
Reserved
FIR Filter Bank A Coefficients, 1 to 60
FIR Filter Bank A, Coefficients, 61 to 120
FIR Filter Bank B, Coefficients, 1 to 60
FIR Filter Bank B, Coefficients, 61 to 120
FIR Filter Bank C, Coefficients, 1 to 60
FIR Filter Bank C, Coefficients, 61 to 120
FIR Filter Bank D, Coefficients, 1 to 60
12 0x0C FIR Filter Bank D, Coefficients, 61 to 120
OUTPUT
REGISTERS
CONTROL
REGISTERS
SPI
09389-011
Rev. B | Page 9 of 28
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