Wideband switch: −3 dB @ 4.5 GHz
ADG901—absorptive switch
ADG902—reflective switch
High off isolation: 40 dB @ 1 GHz
Low insertion loss: 0.8 dB @1 GHz
Single 1.65 V to 2.75 V power supply
CMOS/LVTTL control logic
8-lead MSOP and tiny 3 mm × 3 mm LFCSP packages
Low power consumption (<1 μA)
APPLICATIONS
Wireless communications
General purpose RF switching
Dual-band applications
High speed filter selection
Digital transceiver front end switch
IF switching
Tuner modules
Antenna diversity switching list
GENERAL DESCRIPTION
The ADG901/ADG902 are wideband switches that use a CMOS
process to provide high isolation and low insertion loss to
1 GHz. The ADG901 is an absorptive (matched) switch with
50 Ω terminated shunt legs, while the ADG902 is a reflective
switch. These devices are designed such that the isolation is
high over the dc to 1 GHz frequency range. They have on-board
CMOS control logic, thus eliminating the need for external
controlling circuitry. The control inputs are both CMOS and
0
TA = 25°C
–10
–20
–30
–40
–50
–60
ISOLATION (dB)
–70
–80
–90
–100
10k100k100M1M10M1G
VDD = 2.5V
FREQUENCY (Hz)
Figure 2. Off Isolat
VDD = 1.8V
ion vs. Frequency
10G
03336-002
1.65 V to 2.75 V, SPST Switches
ADG901/ADG902
FUNCTIONAL BLOCK DIAGRAM
ADG901
RF2RF1
50Ω50Ω
CTRL
ADG902
RF2RF1
CTRL
03336-001
Figure 1.
LVTTL compatible. The low power consumption of these
CMOS de
vices makes them ideally suited to wireless
applications and general-purpose high frequency switching.
PRODUCT HIGHLIGHTS
1. −40 dB Off Isolation @ 1 GHz
2. 0.8 dB I
3. T
nsertion Loss @ 1 GHz
iny 8-Lead MSOP/LFCSP Packages
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–2.2
INSERTION LOSS (dB)
–2.4
–2.6
–2.8
VDD = 2.5V
–3.0
= 25°C
T
A
–3.0
10k100k100M1M10M1G
Figure 3. Insertion Loss vs. Frequency
FREQUENCY (Hz)
10G
03336-003
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VDD = 1.65 V to 2.75 V, GND = 0 V, input power = 0 dBm, all specifications T
MIN
to T
, unless otherwise specified.
MAX
Table 1.
B Version
Parameter Symbol Conditions Min Typ
AC ELECTRICAL CHARACTERISTICS
Operating Frequency
−3 dB Frequency
Input Power
4
3
4
DC 2.5 GHz
4.5 GHz
0 V dc bias 7 dBm
0.5 V dc bias 16 dBm
Insertion Loss S21, S12 DC to 100 MHz; VDD = 2.5 V ± 10% 0.4 0.7 dB
500 MHz; VDD = 2.5 V ± 10% 0.5 0.8 dB
1000 MHz; VDD = 2.5 V ± 10% 0.8 1.25 dB
Isolation—RF1 to RF2 S21, S12 100 MHz 60 61 dB
CP Package 500 MHz 43 45 dB
1000 MHz 34 40 dB
Isolation—RF1 to RF2 S21, S12 100 MHz 51 60 dB
RM Package 500 MHz 37.5 47 dB
1000 MHz 31 37 dB
Return Loss (On Channel)4 S11, S22 DC to 100 MHz 20 28 dB
500 MHz 23 29 dB
1000 MHz 25 28 dB
Return Loss (Off Channel)4 S11, S22 DC to 100 MHz 18 23 dB
500 MHz 17 21 dB
1000 MHz 15 19 dB
On Switching Time
Off Switching Time
Rise Time
Fall Time
Input Leakage Current II 0 ≤ VIN ≤ 2.75 V ±0.1 ±1 μA
CAPACITANCE
4
RF1/RF2, RF Port On Capacitance CRF on f = 1 MHz 1.2 pF
CTRL Input Capacitance C
f = 1 MHz 2.1 pF
CTRL
POWER REQUIREMENTS
VDD 1.65 2.75 V
Quiescent Power Supply Current IDD Digital inputs = 0 V or VDD 0.1 1 μA
1
Temperature range for B version: −40°C to +85°C.
2
Typical values are at VDD = 2.5 V and 25°C, unless otherwise specified.
3
Point at which insertion loss degrades by 1 dB.
4
Guaranteed by design, not subject to production test.
5
The dc transience at the output of any port of the switch when the control voltage is switched from high to low or low to high in a 50 Ω test setup, measured with 1 ns
rise time pulses and 500 MHz bandwidth.
1
2
Max Unit
0.35
V
V
DD
Rev. B | Page 3 of 16
ADG901/ADG902
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise specified.
Table 2.
Parameter Rating
V
to GND −0.5 V to +4 V
DD
Inputs to GND
Continuous Current 30 mA
Input Power 18 dBm
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
MSOP Package
θ
Thermal Impedance
JA
LFCSP Package
θ
Thermal Impedance (2-Layer
JA
board)
θ
Thermal Impedance (4-Layer
JA
board)
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
ESD 1 kV
1
RF1/RF2 off port inputs to ground: −0.5 V to VDD – 0.5 V
−0.5 V to V
1
V
−40°C to +85°C
−65°C to +150°C
150°C
206°C/W
84°C/W
48°C/W
300°C
235°C
DD
+ 0.3
Stresses above those listed under Absolute Maximum Ratings
y cause permanent damage to the device. This is a stress
ma
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 4 of 16
ADG901/ADG902
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
V
DD
ADG901/
2
CTRL
GND
8-Lead
3 mm × 3 mm LFCSP (CP-8 – Exposed pad tied to substrate, GND
Figure 4. 8-Lead MSOP (RM-8) and
RF1
ADG902
3
TOP VIEW
(Not to Scale)
4
8
RF2
7
GND
6
GND
5
GND
03336-004
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
DD
Power Supply Input. These parts can be operated from 1.65 V to 2.75 V; VDD should be decoupled to GND.
2 CTRL CMOS or LVTTL Logic Level. CTRL input should not exceed V
0 → RF1 Isolated from RF2.
1 → RF1 to RF2.
3, 5, 6, 7 GND Ground Reference Point for All Circuitry on the Part.
4 RF1 RF1 Port.
8 RF2 RF2 Port.
Table 4. Truth Table
CTRL Signal Path
0 RF1 isolated from RF2
1 RF1 to RF2
DD.
Rev. B | Page 5 of 16
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