1.65 V to 3.6 V operation
Automotive temperature range: –40°C to +125°C
Guaranteed leakage specifications up to 125°C
High current carrying capability: 300 mA continuous
Rail-to-rail switching operation
Fast switching times <20 ns
Typical power consumption: <0.1 µW
APPLICATIONS
Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG836L is a low voltage CMOS device containing two
independently selectable single-pole, double-throw (SPDT)
switches. This device offers ultralow on resistance of less than
0.8 Ω over the full temperature range. The ADG836L is fully
specified for 3.3 V, 2.5 V, and 1.8 V supply operation.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG836L exhibits break-before-make switching action.
The ADG836L is available in a 10-lead package.
Dual SPDT/2:1 MUX
ADG836L
FUNCTIONAL BLOCK DIAGRAM
ADG836L
S1A
S1B
IN1
IN2
S2A
S2B
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
PRODUCT HIGHLIGHTS
1. Less than 0.8 Ω over full temperature range of
−40°C to +125°C.
2. Single 1.65 V to 3.6 V operation.
3. Compatible with 1.8 V CMOS logic.
4. High current handling capability (300 mA continuous
current at 3.3 V).
5. Low THD + N (0.02% typ).
6. Small 10-lead MSOP package.
D1
D2
04753-0-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Parameter +25°C −40°C – +85°C −40°C – +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
On Resistance (RON) 0.65 Ω typ VDD = 2.3 V, VS = 0 V to VDD, IS = 10 mA
0.72 0.8 0.88 Ω max (Figure 18)
On Resistance Match between 0.04 Ω typ VDD = 2.3 V, VS = 0.7 V, IS = 10 mA
Channels (∆RON) 0.08 0.085 Ω max
On Resistance Flatness (R
) 0.16 Ω typ VDD = 2.3 V, VS = 0 V to VDD, IS = 10 mA
FLAT (ON)
0.23 0.24 Ω max
LEAKAGE CURRENTS VDD = 2.7 V
Source Off Leakage IS (OFF) ±0.2 nA typ VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V
±0.4 ±4 ±45 nA max (Figure 19)
Channel On Leakage ID, IS (ON) ±0.2 nA typ VS = VD = 0.6 V or 2.4 V (Figure 20)
±0.6 ±12 ±90 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INH
INL
1.7 V min
0.7 V max
Input Current
I
or I
INL
INH
0.005 µA typ VIN = V
±0.1 µA max
CIN, Digital Input Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS
t
ON
2
23 ns typ RL = 50 Ω, CL = 35 pF
29 30 31 ns max VS = 1.5 V/0 V (Figure 21)
t
5 ns typ RL = 50 Ω, CL = 35 pF
OFF
7 8 9 ns max VS = 1.5 V (Figure 21)
Break-before-Make Time Delay
(t
)
BBM
17 ns typ RL = 50 Ω, CL = 35 pF
5 ns min VS1 = VS2 = 1.5 V (Figure 22)
Charge Injection 30 pC typ VS = 1.25 V, RS = 0 Ω, CL = 1 nF (Figure 23)
Off Isolation −67 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz (Figure 24)
Channel-to-Channel Crosstalk −90 dB typ S1A−S2A/S1B−S2B;
−67 dB typ S1A−S1B/S2A−S2B;
Total Harmonic Distortion
0.022 % R
(THD + N)
Insertion Loss −0.06 dB typ RL = 50 Ω, CL = 5 pF (Figure 25)
–3 dB Bandwidth 57 MHz typ RL = 50 Ω, CL = 5 pF (Figure 25)
CS (OFF) 25 pF typ
CD, CS (ON) 75 pF typ
POWER REQUIREMENTS VDD = 2.7 V
I
DD
0.003 µA typ Digital inputs = 0 V or 2.7 V
1 4 µA max
1
Temperature range for Y version is −40°C to +125°C.
2
Guaranteed by design, not subject to production test.