Datasheet ADG788BCP, ADG786BCP Datasheet (Analog Devices)

2.5 , 1.8 V to 5.5 V, 2.5 V Triple/Quad

a

SPDT Switches in Chip Scale Packages

FEATURES

1.8 V to 5.5 V Single Supply
2.5 V Dual Supply

2.5  On Resistance

0.5  On Resistance Flatness
100 pA Leakage Currents
19 ns Switching Times
Triple SPDT: ADG786
Quad SPDT: ADG788
20-Lead 4 mm  4 mm Chip Scale Packages
Low Power Consumption
TTL/CMOS-Compatible Inputs
For Functionally-Equivalent Devices in 16-Lead TSSOP

Packages, See ADG733/ADG734

APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems

S1B

S1A

S2A

S2B

ADG786/ADG788

FUNCTIONAL BLOCK DIAGRAMS

ADG786

D1

D2

LOGIC

A2

A0

A1

EN

SWITCHES SHOWN FOR A LOGIC “1” INPUT

S3A
D3
S3B

S1A

S1B

IN1

IN2

S2B

S2A

S4A

D1

ADG788

D2

D2
S4B

IN4

IN3
S3B

D3
S3A

GENERAL DESCRIPTION

The ADG786 and ADG788 are low voltage, CMOS devices
comprising three independently selectable SPDT (single pole,
double throw) switches and four independently selectable SPDT
switches respectively.

Low power consumption and operating supply range of 1.8 V to

5.5 V and dual ±2.5 V make the ADG786 and ADG788 ideal
for battery powered, portable instruments and many other
applications. All channels exhibit break-before-make switch­ing action preventing momentary shorting when switching
channels. An EN input on the ADG786 is used to enable or
disable the device. When disabled, all channels are switched OFF.

These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high switch­ing speed, very low on resistance, high signal bandwidths and
low leakage currents. On resistance is in the region of a few
ohms, is closely matched between switches and very flat over
the full signal range. These parts can operate equally well in
either direction and have an input signal range which extends to
the supplies.

The ADG786 and ADG788 are available in small 20-lead
chip scale packages.

PRODUCT HIGHLIGHTS

1. Small 20-Lead 4 mm × 4 mm Chip Scale Packages (CSP).

2. Single/Dual Supply Operation. The ADG786 and ADG788
are fully specified and guaranteed with 3 V ± 10% and
5 V ± 10% single supply rails, and ±2.5 V ± 10% dual
supply rails.

3. Low On Resistance (2.5 Ω typical).

4. Low Power Consumption (<0.01 µW).

5. Guaranteed Break-Before-Make Switching Action.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

1

ADG786/ADG788–SPECIFICA TIONS

B Version

–40C

Parameter +25C to +85C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On Resistance (R

On-Resistance Match between 0.1 Ω typ V

Channels (∆R

On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I
Channel ON Leakage I

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current

or I

I

INL

INH

CIN, Digital Input Capacitance 4 pF typ

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

ADG786 t

t

ON

OFF

Break-Before-Make Time Delay, t
Charge Injection ±3 pC typ V
Off Isolation –72 dB typ R
Channel-to-Channel Crosstalk –67 dB typ R
–3 dB Bandwidth 160 MHz typ R

(OFF) 11 pF typ f = 1 MHz

C

S

CD, CS (ON) 34 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

NOTES

1

Temperature range is as follows: B Version: –40°C to +85 °C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

) 2.5 Ω typ VS = 0 V to VDD, IDS = 10 mA;

ON

4.5 5.0 Ω max Test Circuit 1

) 0.4 Ω max

ON

FLAT(ON)

) 0.5 Ω typ VS = 0 V to VDD, IDS = 10 mA

1.2 Ω max

(OFF) ±0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;

S

±0.1 ±0.3 nA max Test Circuit 2

, IS (ON) ±0.01 nA typ VD = VS = 1 V, or 4.5 V;

D

±0.1 ±0.5 nA max Test Circuit 3

INH

INL

2.4 V min

0.8 V max

0.005 µA typ VIN = V
±0.1 µA max

2

19 ns typ RL = 300 Ω, CL = 35 pF;

34 ns max V

7 ns typ RL = 300 Ω, CL = 35 pF;

12 ns max V

(EN) 20 ns typ RL = 300 Ω, CL = 35 pF;

40 ns max V

(EN) 7 ns typ RL = 300 Ω, CL = 35 pF;

12 ns max V

D

13 ns typ RL = 300 Ω, CL = 35 pF;

1 ns min V

0.001 µA typ Digital Inputs = 0 V or 5.5 V

1.0 µA max

(VDD = 5 V  10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)

V

DD

= 0 V to VDD, IDS = 10 mA

S

= 5.5 V

DD

or V

INL

= 3 V, V

S1A

= 3 V, Test Circuit 4

S

= 3 V, Test Circuit 5

S

= 3 V, Test Circuit 5

S

= 3 V, Test Circuit 6

S

= 2 V, RS = 0 Ω, CL = 1 nF;

S

INH

= 0 V, Test Circuit 4

S1B

Test Circuit 7

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 9

= 50 Ω, CL = 5 pF, Test Circuit 10

L

= 5.5 V

DD

–2–

REV. 0

ADG786/ADG788

SPECIFICA TIONS

Parameter +25C to +85C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On Resistance (R

On-Resistance Match between 0.1 Ω typ V

Channels (∆R

On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I
Channel ON Leakage I

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current

I

or I

INL

INH

CIN, Digital Input Capacitance 4 pF typ

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

ADG786 t

t

ON

OFF

Break-Before-Make Time Delay, t
Charge Injection ±3 pC typ V
Off Isolation –72 dB typ R
Channel-to-Channel Crosstalk –67 dB typ R
–3 dB Bandwidth 160 MHz typ R

C

(OFF) 11 pF typ f = 1 MHz

S

CD, CS (ON) 34 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

NOTES

1

Temperature ranges are as follows: B Version: –40°C to +85 °C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)6 Ω typ VS = 0 V to VDD, IDS = 10 mA;

ON

) 0.5 Ω max

ON

(OFF) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V;

S

, IS (ON) ±0.01 nA typ VS = VD = 1 V or 3 V;

D

INH

INL

(EN) 29 ns typ RL = 300 Ω, CL = 35 pF;

(EN) 9 ns typ RL = 300 Ω, CL = 35 pF;

(VDD = 3 V  10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)

B Version

–40C

V

DD

11 12 Ω max Test Circuit 1

FLAT(ON)

)3Ω typ VS = 0 V to VDD, IDS = 10 mA

±0.1 ±0.3 nA max Test Circuit 2
±0.1 ±0.5 nA max Test Circuit 3

2.0 V min

0.8 V max

0.005 µA typ VIN = V
±0.1 µA max

2

28 ns typ RL = 300 Ω, CL = 35 pF;

55 ns max V

9 ns typ RL = 300 Ω, CL = 35 pF;

16 ns max V
60 ns max V
16 ns max V

D

22 ns typ RL = 300 Ω, CL = 35 pF;

1 ns min V

0.001 µA typ Digital Inputs = 0 V or 3.3 V

1.0 µA max

= 0 V to VDD, IDS = 10 mA

S

= 3.3 V

DD

or V

INL

= 2 V, V

S1A

= 2 V, Test Circuit 4

S

= 2 V, Test Circuit 5

S

= 2 V, Test Circuit 5

S

= 2 V, Test Circuit 6

S

= 1 V, RS = 0 Ω, CL = 1 nF;

S

INH

= 0 V, Test Circuit 4

S1B

Test Circuit 7

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 9

= 50 Ω, CL = 5 pF, Test Circuit 10

L

= 3.3 V

DD

1

REV. 0

–3–

ADG786/ADG788–SPECIFICA TIONS

1

DUAL SUPPLY

(VDD = +2.5 V  10%, VSS = –2.5 V  10%, GND = 0 V, unless otherwise noted.)

B Version

–40C

Parameter +25C to +85C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VSS to V
On Resistance (R

) 2.5 Ω typ VS = VSS to VDD, IDS = 10 mA;

ON

DD

V

4.5 5.0 Ω max Test Circuit 1

On-Resistance Match between 0.1 Ω typ V

Channels (∆R

On-Resistance Flatness (R

) 0.4 Ω max

ON

FLAT(ON)

) 0.5 Ω typ VS = VSS to VDD, IDS = 10 mA

= VSS to VDD, IDS = 10 mA

S

1.2 Ω max

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ±0.01 nA typ

S

= +2.75 V, VSS = –2.75 V

DD

VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;

±0.1 ±0.3 nA max Test Circuit 2

Channel ON Leakage I

, IS (ON) ±0.01 nA typ

D

VS = VD = +2.25 V/–1.25 V, Test Circuit 3

±0.1 ±0.5 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

1.7 V min

0.7 V max

Input Current

I

INL

or I

INH

0.005 µA typ VIN = V

INL

or V

INH

±0.1 µA max

CIN, Digital Input Capacitance 4 pF typ

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

ADG786 t

(EN) 21 ns typ RL = 300 Ω, CL = 35 pF;

ON

t

(EN) 10 ns typ RL = 300 Ω, CL = 35 pF;

OFF

Break-Before-Make Time Delay, t
Charge Injection ±5 pC typ V

2

21 ns typ RL = 300 Ω, CL = 35 pF;

35 ns max V

= 1.5 V, V

S1A

= 0 V, Test Circuit 4

S1B

10 ns typ RL = 300 Ω, CL = 35 pF;

16 ns max V
40 ns max V
16 ns max V

D

13 ns typ RL = 300 Ω, CL = 35 pF;

1 ns min V

= 1.5 V, Test Circuit 4

S

= 1.5 V, Test Circuit 5

S

= 1.5 V, Test Circuit 5

S

= 1.5 V, Test Circuit 6

S

= 0 V, RS = 0 Ω, CL = 1 nF;

S

Test Circuit 7

Off Isolation –72 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

Channel-to-Channel Crosstalk –67 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 9

–3 dB Bandwidth 160 MHz typ R

(OFF) 11 pF typ f = 1 MHz

C

S

= 50 Ω, CL = 5 pF, Test Circuit 10

L

CD, CS (ON) 34 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

0.001 µA typ Digital Inputs = 0 V or 2.75 V

= +2.75 V

DD

1.0 µA max

I

SS

0.001 µA typ VSS = –2.75 V

1.0 µA max Digital Inputs = 0 V or 2.75 V

NOTES

1

Temperature range is as follows: B Version: –40°C to +85 °C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–4–

REV. 0

ADG786/ADG788

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V

SS

Analog Inputs
Digital Inputs

2

. . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V or

2

. . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

(Pulsed at 1 ms, 10% Duty Cycle max)

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA

Operating Temperature Range

1

30 mA, Whichever Occurs First
30 mA, Whichever Occurs First

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

20 Lead CSP, θ

Thermal Impedance . . . . . . . . . . . 32°C/W

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C

IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at A, EN, IN, S, or D will be clamped by internal diodes. Current

should be limited to the maximum ratings given.

Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG786/ADG788 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG786BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADG788BCP –40°C to +85°C Chip Scale Package (CSP) CP-20

PIN CONFIGURATIONS

DD

V

NC

16171819

S1B

V

GND

S2B

D1

SS

15

D2

14

NC

13

D1
S1B

12

S1A

11

910

A2A1A0

EXPOSED PAD TIED TO SUBSTRATE, V

NC = NO CONNECT

1
2
3
4
5

S1A

IN1

20

PIN 1
IDENTIFIER

ADG788

TOP VIEW

(Not to Scale)

6

78

D2

S2A

SS

IN4

IN2

S4A

16171819

910

IN3

D4

NC

15

S4B

14

V

DD

13

S3B
D3

12

S3A

11

S2A
S3B

S3A

D3

EN

1
2
3
4
5

S2BNCNC

20

PIN 1
IDENTIFIER

ADG786

TOP VIEW

(Not to Scale)

6

78

SS

V

GND

REV. 0

–5–

ADG786/ADG788

Table I. ADG786 Truth Table

A2 A1 A0 EN ON Switch

XXX1 None
0 0 0 0 D1-S1A, D2-S2A, D3-S3A

Table II. ADG788 Truth Table

Logic Switch A Switch B

0 OFF ON

1 ON OFF
0 0 1 0 D1-S1B, D2-S2A, D3-S3A
0 1 0 0 D1-S1A, D2-S2B, D3-S3A
0 1 1 0 D1-S1B, D2-S2B, D3-S3A
1 0 0 0 D1-S1A, D2-S2A, D3-S3B
1 0 1 0 D1-S1B, D2-S2A, D3-S3B
1 1 0 0 D1-S1A, D2-S2B, D3-S3B
1 1 1 0 D1-S1B, D2-S2B, D3-S3B

TERMINOLOGY

V

DD

V

SS

Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to

ground close to the device.

I

DD

I

SS

Positive Supply Current

Negative Supply Current
GND Ground (0 V) Reference
S Source Terminal. May be an input or output
D Drain Terminal. May be an input or output
IN Logic Control Input
V

(VS) Analog Voltage on Terminals D, S

D

R

ON

∆R

ON

R

FLAT(ON)

Ohmic Resistance between D and S

On Resistance Match between Any Two Channels, i.e., RONmax – RONmin.

Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured

over the specified analog signal range.
I

(OFF) Source Leakage Current with the Switch “OFF”

S

I

, IS (ON) Channel Leakage Current with the Switch “ON”

D

V

INL

V

INH

I

INL(IINH

C
C
C
t

ON

t

OFF

t

ON

t

OFF

t

OPEN

) Input Current of the Digital Input

(OFF) “OFF” Switch Source Capacitance. Measured with reference to ground.

S

, CS(ON) “ON” Switch Capacitance. Measured with reference to ground.

D
IN

(EN) Delay time between the 50% and 90% points of the EN digital input and the switch “ON” condition.

(EN) Delay time between the 50% and 90% points of the EN digital input and the switch “OFF” condition.

Maximum Input Voltage for Logic “0”

Minimum Input Voltage for Logic “1”

Digital Input Capacitance

Delay time measured between the 50% and 90% points of the digital inputs and the switch “ON” condition.

Delay time measured between the 50% and 90% points of the digital input and the switch “OFF” condition.

“OFF” time measured between the 80% points of both switches when switching from one address state to another.
Charge A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching.
Off Isolation A measure of unwanted signal coupling through an “OFF” switch.
Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic

capacitance.
On Response The Frequency Response of the “ON” Switch
Insertion Loss The Loss Due to the ON Resistance of the Switch.

–6–

REV. 0

T ypical Performance Characteristics–

VS, (VD = VDD –VS) – V

0.10

0123 5

CURRENT – nA

VDD = 5V
V

SS

= GND

T

A

= 25C

4

IS, ID (ON), VD = V

S

IS (OFF)

0.05

0

–0.05

–0.10

–0.15

TEMPERATURE – C

0.25

5

CURRENT – nA

V

DD

= +2.5V

V

SS

= –2.5V

V

D

= +2.25V/–1.25V

V

S

= –1.25V/+2.25V

V

DD

= 5V

V

SS

= GND

V

D

= 4.5V/1.0V

V

S

= 1.0V/4.5V

IS, ID (ON)

IS (OFF)

0.20

0.15

0.10

0.05

0

–0.05

20 35 50 65 80

–0.10

ADG786/ADG788

8

7

6

5

4

3

ON RESISTANCE – 

2

1

0

01234

VD, VS, DRAIN OR SOURCE VOLTAGE – V

VDD = 2.7V

VDD = 3.3V

TA = 25C
V

VDD = 4.5V

VDD = 5.5V

= 0V

SS

5

TPC 1. On Resistance as a Function
of V

) for Single Supply

D(VS

8

7

6

5

4

3

ON RESISTANCE – 

2

1

0

0 0.5

VD, VS, DRAIN OR SOURCE VOLTAGE – V

1.0 1.5 2.0 2.5 3.0

+85C

–40C

+25C

VDD = 3V

= 0V

V

SS

TPC 4. On Resistance as a Function
of V

) for Different Temperatures,

D(VS

Single Supply

8

7

6

5

4

3

ON RESISTANCE – 

2

1

0

–3 –2 –10 2

VD, VS, DRAIN OR SOURCE VOLTAGE – V

VDD = +2.5V

= –2.5V

V

SS

TA = 25C

1

TPC 2. On Resistance as a Function
of V

) for Dual Supply

D(VS

8

7

6

5

4

+85C

3

ON RESISTANCE – 

2

–40C

1

0

–3 –2 –10 2

VD, VS, DRAIN OR SOURCE VOLTAGE – V

VDD = +2.5V
V

SS

+25C

1

= –2.5V

TPC 5. On Resistance as a Function

of VD(VS) for Different Temperatures

Dual Supply

8

7

6

5

4

+85C

3

ON RESISTANCE – 

2

3

–40C

1

0

1

02

VD, VS, DRAIN OR SOURCE VOLTAGE – V

TPC 3. On Resistance as a Function
of VD(VS) for Different Temperatures,
Single Supply

3

TPC 6. Leakage Currents as a

,

Function of VD(VS)

+25C

3

VDD = 5V

= 0V

V

SS

45

0.10

0.08

0.06

0.04

0

0 0.5

IS, ID (ON), VD = V

IS (OFF)

1.0 1.5 2.0 2.5 3.0

VS, (VD = VDD –VS) – V

D(VS

0.02

–0.02

CURRENT – nA

–0.04
–0.06
–0.08

–0.10

TPC 7. Leakage Currents as a
Function of V

REV. 0

CURRENT – nA

–0.05

–0.10

–0.15

0.15

0.10

0.05

0

–3 –2

IS, ID (ON), VD = V

IS (OFF)

–10123

VS, (VD = VDD –VS) – V

VDD = +2.5V
V
T

S

TPC 8. Leakage Currents as a
Function of V

D(VS

)

= –2.5V

SS

= 25C

A

TPC 9. Leakage Currents as a
Function of Temperature

VDD = 3V

= GND

V

SS

= 25C

T

A

S

)

–7–

ADG786/ADG788

CURRENT – nA

–0.05

–0.10

0.25

0.20

0.15

0.10

0.05
IS, ID (ON)

0

IS (OFF)

5

20 35 50 65 80

TEMPERATURE – C

VDD = 3V

= GND

V

SS

= 2.7V/1V

V

D

= 1V/2.7V

V

S

TPC 10. Leakage Currents as a
Function of Temperature

CURRENT – A

10m

1m

100

10

1

100n

10n

VDD = +2.5V

= –2.5V

V

SS

VSS = 3V
V

DD

0.1

1 10 100 1000 10000

FREQUENCY – kHz

VDD = 5V

= GND

V

SS

= GND

TA = 25C

TPC 13. Input Current, IDD vs.
Switching Frequency

40

35

30

25

20

TIME – ns

15

10

5

0

–20

TPC 11. tON/t

tON, VDD = 3V

tON, VDD = 5V

t

OFF

t

OFF

020406080

TEMPERATURE – C

OFF

VSS = GND

, VDD = 3V

, VDD = 5V

Times vs.

Temperature

0

–10
–20
–30
–40
–50
–60
–70

ATTENUATION – dB

–80
–90

–100

30k

100k 1M 10M 100M

VDD = 5V

= 25C

T

A

FREQUENCY – Hz

TPC 14. Off Isolation vs. Frequency

0

–2

VDD = 5V

–4

T

= 25C

A

–6

–8

–10

ON RESPONSE – dB

–12

–14

–16

100k 1M 100M

FREQUENCY – HZ

10M10k

TPC 12. On Response vs. Frequency

0

–10

–20
–30
–40

–50
–60

ATTENUATION – dB

–70
–80
–90

30k

100k 1M 10M 100M

FREQUENCY – Hz

VDD = 5V

= 25C

T

A

TPC 15. Crosstalk vs. Frequency

30

20

– pC

10

INJ

Q

–10

0

–3 –2

VDD = +2.5V

= –2.5V

V

SS

VDD = 3V

= GND

V

SS

–10123

VOLTAGE – V

TA = 25C

VDD = 5V

= GND

V

SS

45

TPC 16. Charge Injection vs. Source
Voltage

–8–

REV. 0

Test Circuits

ADG786/ADG788

I

DS

V1

SD

V

S

RON = V1/I

DS

Test Circuit 1. On Resistance

0.1F

VS1B
VS1A

IN/EN

V

DD

0.1F

V

DD

A2
A1
A0

ADG786

EN

50

V

IN

GND

IS (OFF)

SD

A

V

S

Test Circuit 2. IS (OFF)

V

DD

V

DD

S1B
S1A

GND

0.1F

D1

R

L

300

VSS

V

SS

C

L

35pF

V

OUT

Test Circuit 4. Switching Times, tON, t

V

SS

V

SS

S1A
S1B

V

S

D1

R

L

300

C

L

35pF

V

O

ENABLE

DRIVE (V

OUTPUT

Test Circuit 5. Enable Delay, tON (EN), t

ADDRESS
DRIVE

VS1A

V

OUT

VS1B

3V

)

IN

0V

V

O

0V

V

D

50% 50%

90%

t

ON

OFF

50%

(EN)

OFF

SD

NC

NC = NO CONNECT

Test Circuit 3. ID (ON)

90%

t

OFF

50%

0.9V

0

(EN)

t

ON

0.9V

ID (ON)

A

V

D

t

(EN)

OFF

0

REV. 0

V

DD

0.1F

V

DD

V

IN

ADDRESS*

50

SA

SB

V

S

3V

ADDRESS

0V

ADG786/

ADG788

D1

V

0.1F

SS

V

SS

GND

*A0, A1, A2 for ADG786, IN1-4 for ADG788

R

L

300

C

L

35pF

Test Circuit 6. Break-Before-Make Delay, t

V

OUT

V

S

t

OPEN

80%

V

OUT

80%

OPEN

–9–

ADG786/ADG788

R

S

V

S

V

IN

* IN1–4 for ADG734

V

DD

V

DD

ADG786/

ADG788

S
EN*

GND

V

SS

V

SS

INPUT (VIN)

D

C

1nF

V

OUT

L

Test Circuit 7. Charge Injection

LOGIC

V

OUT

3V

0V

V

Q

INJ

= CL  V

OUT

OUT

V

NETWORK

ANALYZER

V

OUT

IN

V

V

DD

0.1F

IN

SS

0.1F

V

V

SS

DD

S

D

GND

50

Test Circuit 8. OFF Isolation

0.1F

R

L

50

50

V

S

IN

NETWORK

ANALYZER

50

V

V

OUT

R

L

50

OFF ISOLATION = 20 LOG

V

V

DD

SS

0.1F

V

V

SA

SB

SS

DD

GND

CHANNEL-TO-CHANNEL

CROSSTALK = 20

D

S

R
50

V

V

DD

0.1F

V

IN

V

IN

V

OUT

V

S

SS

0.1F

V

DD

SS

S

D

GND

INSERTION LOSS = 20 LOG

NETWORK
ANALYZER

50

V

R

L

50

V

WITH SWITCH

OUT

V

WITHOUT SWITCH

OUT

OUT

V

S

Test Circuit 10. Bandwidth

Power Supply Sequencing

When using CMOS devices, care must be taken to ensure cor­rect power supply sequencing. Incorrect sequencing can result
in the device being subjected to stresses beyond those maximum
ratings listed in the data sheet. Digital and analog inputs should
be applied to the device after supplies and ground. In dual sup­ply applications, if digital and analog inputs may be applied
prior to V
connected between V
powers on correctly. For single supply applications, V

and VSS supplies, the addition of a Schottky diode

DD

and GND will ensure that the device

SS

should

SS

be tied to GND as close to the device as possible.

V

OUT

LOG

V

S

Test Circuit 9. Channel-to-Channel Crosstalk

–10–

REV. 0

PIN 1

INDICATOR

0.035 (0.90) MAX

0.033 (0.85) NOM
SEATING

PLANE

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Lead Chip Select Package

(CP-20)

0.157 (4.0)
BSC SQ

TOP

VIEW

12 MAX

0.020 (0.50)
BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

0.148 (3.75)
BSC SQ

0.028 (0.70) MAX

0.026 (0.65) NOM

0.008 (0.20)
REF

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.012 (0.30)

0.009 (0.23)

0.007 (0.18)

0.030 (0.75)

0.024 (0.60)

0.020 (0.50)

0.002 (0.05)

0.0004 (0.01)

0.0 (0.0)

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

16

15

11

10

0.080 (2.00)

0.010 (0.25)

BOTTOM

VIEW

REF

MIN

20

6

1

5

ADG786/ADG788

0.089 (2.25)

0.083 (2.10) SQ

0.077 (1.95)

REV. 0

–11–

C02381–1–7/01(0)

–12–

PRINTED IN U.S.A.