CMOS
a
FEATURES
Low Insertion Loss and On Resistance: 4 ⍀ Typical
On-Resistance Flatness <2 ⍀
Bandwidth >200 MHz
Single 3 V/5 V Supply Operation
Rail-to-Rail Operation
Very Low Distortion: <1%
Low Quiescent Supply Current (100 nA Typical)
Fast Switching Times
t
10 ns
ON
t
4 ns
OFF
TTL/CMOS Compatible
APPLICATIONS
10/100 Base-TX/T4
100VG-AnyLAN
Token Ring 4 Mbps/16 Mbps
ATM25/155
NIC Adapter and Hubs
Audio and Video Switching
Relay Replacement
3 V/5 V, Wide Bandwidth Quad 2:1 Mux
ADG774
FUNCTIONAL BLOCK DIAGRAM
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
ADG774
1 OF 2
DECODER
EN
D1
D2
D3
D4
IN
GENERAL DESCRIPTION
The ADG774 is a monolithic CMOS device comprising four
2:1 multiplexer/demultiplexers with high impedance outputs.
The CMOS process provides low power dissipation yet gives
high switching speed and low on resistance. The on-resistance
variation is typically less than 0.5 Ω with an input signal ranging
from 0 V to 5 V.
The bandwidth of the ADG774 is greater than 200 MHz and
this, coupled with low distortion (typically 0.5%), makes the
part suitable for switching fast ethernet signals.
The on-resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when switching audio signals. Fast switching speed, coupled with high signal
bandwidth, also makes the parts suitable for video signal switching. CMOS construction ensures ultralow power dissipation
making the parts ideally suited for portable and battery powered
instruments.
The ADG774 operates from a single 3.3 V/5 V supply and is
TTL logic compatible. The control logic for each switch is shown
in the Truth Table.
These switches conduct equally well in both directions when ON,
and have an input signal range that extends to the supplies. In
the OFF condition, signal levels up to the supplies are blocked.
The ADG774 switches exhibit break-before-make switching
action.
PRODUCT HIGHLIGHTS
1. Wide bandwidth data rates >200 MHz.
2. Ultralow Power Dissipation.
3. Extended Signal Range.
The ADG774 is fabricated on a CMOS process giving an
increased signal range that fully extends to the supply rails.
4. Low leakage over temperature.
5. Break-Before-Make Switching.
This prevents channel shorting when the switches are configured as a multiplexer.
6. Crosstalk is typically –70 dB @ 30 MHz.
7. Off isolation is typically –60 dB @ 10 MHz.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
ADG774–SPECIFICATIONS
SINGLE SUPPLY
(VDD = +5 V ⴞ 10%, GND = 0 V. All specifications T
MIN
to T
unless otherwise noted.)
MAX
B Version
to
T
Parameter +25ⴗCT
MIN
MAX
Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
On Resistance (R
) 2.2 Ω typ V
ON
DD
V
= 0 V to VDD, IS = –10 mA
D
5 Ω max
On Resistance Match Between
Channels (∆R
)0.15 Ω typ V
ON
= 0 V to VDD, IS = –10 mA
D
0.5 Ω max
On Resistance Flatness (R
FLAT(ON)
) 0.5 Ω typ V
= 0 V to VDD; IS = –1 mA
D
1 Ω max
LEAKAGE CURRENTS
Source OFF Leakage I
(OFF) ±0.01 nA typ V
S
= 4.5 V, VS = 1 V; VD = 1 V, VS = 4.5 V;
D
±0.5 ±1 nA max Test Circuit 2
Drain OFF Leakage I
(OFF) ±0.01 nA typ V
D
= 4.5 V, VS = 1 V; VD = 1 V, VS = 4.5 V;
D
±0.5 ±1 nA max Test Circuit 2
Channel ON Leakage I
(ON) ±0.01 nA typ V
D
S
= VS = 4.5 V; VD = VS = 1 V; Test Circuit 3
D
, I
±0.5 ±1 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.4 V min
0.8 V max
Input Current
I
INL
or I
INH
0.001 µA typ V
IN
= V
±0.5 µA max
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Break-Before-Make Time Delay, t
Off Isolation –65 dB typ R
Channel-to-Channel Crosstalk –75 dB typ R
Bandwidth –3 dB 240 MHz typ R
Distortion 0.5 % typ R
Charge Injection 10 pC typ C
(OFF) 10 pF typ f = 1 kHz
C
S
(OFF) 20 pF typ f = 1 kHz
C
D
2
10 ns typ R
20 ns max V
4 ns typ R
8 ns max V
D
5 ns typ R
1 ns min V
= 100 Ω, C
L
= +3 V; Test Circuit 4
S
= 100 Ω, C
L
= +3 V; Test Circuit 4
S
= 100 Ω, C
L
= VS2 = +5 V; Test Circuit 5
S1
= 100 Ω, f = 10 MHz; Test Circuit 7
L
= 100 Ω, f = 10 MHz; Test Circuit 8
L
= 100 Ω; Test Circuit 6
L
= 100 Ω
L
= 1 nF; Test Circuit 9
L
CD, CS (ON) 30 pF typ f = 1 MHz
POWER REQUIREMENTS V
= +5.5 V
DD
Digital Inputs = 0 V or V
I
DD
1 µA max
0.001 µA typ
I
IN
I
O
NOTES
1
Temperature ranges are as follows: B Version, –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
1 µA typ V
100 mA max VS/VD = 0 V
= +5 V
IN
INL
or V
INH
= 35 pF,
L
= 35 pF,
L
= 35 pF,
L
DD
–2– REV. 0
ADG774
SINGLE SUPPLY
(VDD = +3 V ⴞ 10%, GND = 0 V. All specifications T
MIN
to T
unless otherwise noted.)
MAX
B Version
to
T
Parameter +25ⴗCT
MIN
MAX
Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
On Resistance (R
)4 Ω typ V
ON
DD
V
= 0 V to VDD, IS = –10 mA
D
8 Ω max
On Resistance Match Between
Channels (∆R
)0.15 Ω typ V
ON
= 0 V to VDD, IS = –10 mA
D
0.5 Ω max
On Resistance Flatness (R
FLAT(ON)
) 2Ω typ V
= 0 V to VDD, IS = –10 mA
D
4 Ω max
LEAKAGE CURRENTS
Source OFF Leakage I
(OFF) ±0.01 nA typ V
S
= 3 V, VS = 1 V; VD = 1 V, VS = 3 V;
D
±0.5 ±1 nA max Test Circuit 2
Drain OFF Leakage I
(OFF) ±0.01 nA typ V
D
= 3 V, VS = 1 V; VD = 1 V, VS = 3 V;
D
±0.5 ±1 nA max Test Circuit 2
Channel ON Leakage I
(ON) ±0.01 nA typ V
D
S
= VS = 3 V; VD = VS = 1 V; Test Circuit 3
D
, I
±0.5 ±1 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.0 V min
0.4 V max
Input Current
I
INL
or I
INH
0.001 µA typ V
IN
= V
±0.5 µA max
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Break-Before-Make Time Delay, t
Off Isolation –65 dB typ R
Channel-to-Channel Crosstalk –75 dB typ R
Bandwidth –3 dB 240 MHz typ R
Distortion 2 % typ R
Charge Injection 3 pC typ C
(OFF) 10 pF typ f = 1 kHz
C
S
(OFF) 20 pF typ f = 1 kHz
C
D
2
12 ns typ R
25 ns max V
5 ns typ R
10 ns max V
D
5 ns typ R
1 ns min V
= 100 Ω, C
L
= +1.5 V; Test Circuit 4
S
= 100 Ω, C
L
= +1.5 V; Test Circuit 4
S
= 100 Ω, C
L
= VS2 = 3 V; Test Circuit 5
S1
= 50 Ω, f = 10 MHz; Test Circuit 7
L
= 50 Ω, f = 10 MHz; Test Circuit 8
L
= 50 Ω; Test Circuit 6
L
= 50 Ω
L
= 1 nF; Test Circuit 9
L
CD, CS (ON) 30 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
Digital Inputs = 0 V or V
I
DD
1 µA max
0.001 µA typ
I
IN
I
O
NOTES
1
Temperature ranges are as follows: B Version, –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
1 µA typ V
100 mA max VS/VD = 0 V
= +3 V
IN
or V
INL
= +3.3 V
INH
= 35 pF,
L
= 35 pF,
L
= 35 pF,
L
DD
Table I. Truth Table
EN IN D1 D2 D3 D4 Function
1 X Hi-Z Hi-Z Hi-Z Hi-Z DISABLE
0 0 S1A S2A S3A S4A IN = 0
0 1 S1B S2B S3B S4B IN = 1
–3–REV. 0
ADG774
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
(T
= +25°C unless otherwise noted)
A
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Analog, Digital Inputs
2
. . . . . . . . . . . –0.3 V to VDD + 0.3 V or
1
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 100 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
QSOP Package, Power Dissipation . . . . . . . . . . . . . . . 566 mW
Thermal Impedance . . . . . . . . . . . . . . . . . . . 149.97°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
PIN CONFIGURATION
(SOIC/QSOP)
16
V
DD
15
EN
14
S4A
13
S4B
12
D4
11
S3A
10
S3B
9
D3
S1A
S1B
S2A
S2B
GND
IN
D1
D2
1
2
3
ADG774
4
TOP VIEW
5
(Not to Scale)
6
7
8
TERMINOLOGY
V
DD
Most Positive Power Supply Potential.
GND Ground (0 V) Reference.
S Source Terminal. May be an input or output.
D Drain Terminal. May be an input or output.
IN Logic Control Input.
EN Logic Control Input.
R
ON
∆R
ON
R
FLAT(ON)
Ohmic resistance between D and S.
On Resistance match between any two channels
i.e., R
max – R
ON
ON
min.
Flatness is defined as the difference between the
maximum and minimum value of on resistance
as measured over the specified analog signal
range.
I
(OFF) Source Leakage Current with the switch “OFF.”
S
I
(OFF) Drain Leakage Current with the switch “OFF.”
D
I
, IS (ON) Channel Leakage Current with the switch “ON.”
D
V
) Analog Voltage on Terminals D, S.
D (VS
C
(OFF) “OFF” Switch Source Capacitance.
S
C
(OFF) “OFF” Switch Drain Capacitance.
D
C
, CS (ON) “ON” Switch Capacitance.
D
t
ON
Delay between applying the digital control input
and the output switching on. See Test Circuit 4.
t
OFF
Delay between applying the digital control input
and the output switching Off.
t
D
“OFF” time or “ON” time measured between
the 90% points of both switches, when switching
from one address state to another. See Test
Circuit 5.
Crosstalk A measure of unwanted signal that is coupled
through from one channel to another as a result
of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling through an
“OFF” switch.
Bandwidth Frequency response of the switch in the ON
state measured at 3 dB down.
Distortion R
FLAT(ON)/RL
ORDERING GUIDE
Model Temperature Range Package Descriptions Package Options
ADG774BR –40°C to +85°C R = 0.15" Small Outline IC (SOIC) R-16A
ADG774BRQ –40°C to +85°C RQ = 0.15" Quarter Size Outline Package (QSOP) RQ-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG774 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4– REV. 0
Typical Performance Characteristics–ADG774
VDD = +5V
FREQUENCY – Hz
0
10M10k
ON RESPONSE – dB
–4
–2
100k 1M 100M
–6
FREQUENCY – Hz
0
–10
–100
100k 1G1M 10M 100M
–40
–70
–80
–90
–20
–30
–60
–50
ATTENUATION – dB
VDD = +5V
R
L
= 100V
FREQUENCY – Hz
0
–10
–100
100k 1G1M 10M 100M
–40
–70
–80
–90
–20
–30
–60
–50
ATTENUATION – dB
VDD = +5V
R
L
= 100V
V
P-P
= 0.316V
5.0
VDD = +2.7V
4.5
4.0
3.5
3.0
– V
2.5
ON
R
2.0
1.5
1.0
0.5
0
VDD = +3.0V
VDD = +4.5V
VDD = +5.0V
1.3 2.5 3.7 4.9
OR VD DRAIN OR SOURCE VOLTAGE – V
V
S
TA = +258C
Figure 1. On Resistance as a Function of VD (VS) for
Various Single Supplies
3.0
VDD = +5V
2.5
2.0
+858C
Figure 4. On Response vs. Frequency
– V
1.5
ON
R
1.0
0.5
0
V
OR VO DRAIN OR SOURCE VOLTAGE – V
S
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures with 5 V Single Supplies
4.5
VDD = +3V
4.0
3.5
3.0
2.5
– V
ON
2.0
R
1.5
1.0
0.5
0
0.6 1.1 1.6 2.1 2.6
V
OR VD DRAIN OR SOURCE VOLTAGE – V
S
Figure 3. On Resistance as a Function of VD (VS) for
Different Temperatures with 3 V Single Supplies
+258C
–408C
1.3 2.5 3.7 4.9
Figure 5. Off Isolation vs. Frequency
+858C
+258C
–408C
Figure 6. Crosstalk vs. Frequency
–5–REV. 0
ADG774
20
VDD = +5V
T
= +25 C
A
15
10
5
0
CHARGE INJECTION – pC
–5
–10
0 5.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
SOURCE VOLTAGE – V
Figure 7. Charge Injection vs. Source Voltage
TX1
10 BASE TX+
10 BASE TX–
100 BASE TX+
100 BASE TX–
10 BASE TX+
10 BASE TX–
100 BASE TX+
100 BASE TX–
10 BASE TX
100 BASE TX
TX1
TX2
RX1
RX2
ADG774
TRANSFORMER
Figure 8. Full Duplex Transceiver
RJ45
RX1
Figure 9. Loop Back
120V 100V
Figure 10. Line Termination
–6– REV. 0
Figure 11. Line Clamp
Test Circuits
SD
V
S
A
V
D
ID (ON)
0.1mF
+5V
V
S
IN
D1
V
DD
GND
R
L
100V
V
OUT
V
IN
EN
S1A
S1B
ADG774
I
DS
V1
SD
V
S
RON = V1/I
DS
Test Circuit 1. On Resistance
V
S
+5V
0.1mF
V
DD
SD
IN
GND
EN
+5V
0.1mF
IS (OFF) ID (OFF)
SD
A A
V
S
V
D
Test Circuit 2. Off Leakage
3V
V
IN
V
OUT
R
100V
C
L
L
35pF
V
OUT
Test Circuit 4. Switching Times
50% 50%
90% 90%
t
ON
Test Circuit 3. On Leakage
t
OFF
V
DD
S1A
V
S1B
S
V
EN
S
DECODER
GND
D1
R
L
100V
V
C
L
35pF
OUT
3V
V
IN
0V
V
OUT
V
S
50% 50%
50% 50%
t
D
t
D
Test Circuit 5. Break-Before-Make Time Delay
+5V
0.1mF
V
DD
V
R
L
100V
OUT
Test Circuit 7. Off Isolation
–7–REV. 0
D1
V
S
IN
V
IN
EN
GND
Test Circuit 6. Bandwidth
ADG774
16 9
8
1
0.197 (5.00)
0.189 (4.80)
0.244 (6.20)
0.228 (5.79)
PIN 1
0.157 (3.99)
0.150 (3.81)
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025
(0.64)
BSC
0.059 (1.50)
MAX
0.069 (1.75)
0.053 (1.35)
0.010 (0.20)
0.007 (0.18)
0.050 (1.27)
0.016 (0.41)
88
08
+5V
0.1mF
V
DD
S1A
V
S
D1
100V
NC
S2A
EN
D2
GND
V
IN
CHANNEL-TO-CHANNEL
CROSSTALK = 20 3 LOG |VS/V
R
L
100V
V
OUT
C3326–8–7/98
|
OUT
Test Circuit 8. Channel-to-Channel Crosstalk
+5V
V
DD
R
S
V
S
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
ADG774
1 OF 2
DECODER
EN
D1 V
D2 V
D3 V
D4 V
OUT
OUT
OUT
OUT
C
L
1nF
C
L
1nF
C
L
1nF
C
L
1nF
IN
3V
V
IN
V
OUT
Q
INJ
= CL 3 DV
OUT
DV
OUT
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
16-Lead SOIC
0.3937 (10.00)
0.3859 (9.80)
16 9
PIN 1
0.0192 (0.49)
0.0500
(1.27)
0.0138 (0.35)
BSC
(R-16A)
0.2550 (6.20)
81
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0099 (0.25)
0.0075 (0.19)
Test Circuit 9. Charge Injection
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.0196 (0.50)
0.0099 (0.25)
88
08
0.0500 (1.27)
0.0160 (0.41)
3 458
16-Lead QSOP
(RQ-16)
PRINTED IN U.S.A.
–8–
REV. 0
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