FEATURES
High Off Isolation –75 dB at 100 MHz
–3 dB Signal Bandwidth 300 MHz
+1.8 V to +5.5 V Single Supply
Low On-Resistance (15 ⍀)
Fast Switching Times
t
Typically 9 ns
ON
t
Typically 3 ns
OFF
Typical Power Consumption <0.01 W
TTL/CMOS Compatible
APPLICATIONS
Audio and Video Switching
RF Switching
Networking Applications
Battery Powered Systems
Communication Systems
Relay Replacement
Sample-and-Hold Systems
RF/Video, SPST Switch
ADG751
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADG751 is a low voltage SPST (single pole, single throw)
switch. It is constructed in a T-switch configuration, which
results in excellent Off Isolation while maintaining good frequency response in the ON condition.
High off isolation and wide signal bandwidth make this part
suitable for switching RF and video signals. Low power consumption and operating supply range of +1.8 V to +5.5 V make
it ideal for battery powered, portable instruments.
The ADG751 is designed on a submicron process that provides
low power dissipation yet gives high switching speed and low on
resistance. This part is a fully bidirectional switch and can handle
signals up to and including the supply rails.
The ADG751 is available in 6-lead SOT-23 and 8-lead µSOIC
packages.
PRODUCT HIGHLIGHTS
1. High Off Isolation –75 dB at 100 MHz.
2. –3 dB Signal Bandwidth 300 MHz.
3. Low On-Resistance (15 Ω).
4. Low Power Consumption, typically <0.01 µW.
5. Tiny 6-lead SOT-23 and 8-lead µSOIC packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
ADG751BRM–40°C to +85°CSDBµSOICRM-8
ADG751BRT–40°C to +85°CSDBSOT-23RT-6
ADG751ARM–40°C to +85°CSDAµSOICRM-8
ADG751ART–40°C to +85°CSDASOT-23RT-6
*Brand on these packages is limited to three characters due to space constraints.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG751 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
ADG751
PIN CONFIGURATIONS
8-Lead SOIC
(RM-8)
1
NC
2
S
(Not to Scale)
3
GND
4
IN
NC = NO CONNECT
ADG751
TOP VIEW
8
V
DD
D
7
NC
6
NC
5
6-Lead SOT-23
(RT-6)
1
S
ADG751
V
2
DD
TOP VIEW
(Not to Scale)
3
NC
NC = NO CONNECT
6
D
GND
5
IN
4
TERMINOLOGY
V
DD
Most positive power supply potential.
GNDGround (0 V) reference.
SSource terminal. May be an input or output.
DDrain terminal. May be an input or output.
INLogic control input.
R
ON
R
FLAT(ON)
Ohmic resistance between D and S.
Flatness is defined as the difference between
the maximum and minimum value of on resis-
tance as measured over the specified analog
signal range.
I
(OFF)Source leakage current with the switch “OFF.”
S
I
(OFF)Drain leakage current with the switch “OFF.”
D
I
, IS (ON)Channel leakage current with the switch “ON.”
D
V
)Analog voltage on terminals D and S.
D (VS
C
(OFF)“OFF” switch source capacitance.
S
C
(OFF)“OFF” switch drain capacitance.
D
C
, CS (ON)“ON” switch capacitance.
D
t
ON
Delay between applying the digital control
input and the output switching on. See Test
Circuit 4.
t
OFF
Delay between applying the digital control
input and the output switching off.
Off IsolationA measure of unwanted signal coupling
through an “OFF” switch.
ChargeA measure of the glitch impulse transferred from
Injectionthe digital input to the analog output during
switching.
BandwidthThe frequency at which the output is attenu-
ated by –3 dBs.
On ResponseThe frequency response of the “ON” switch.
Insertion LossLoss due to the ON resistance of the switch.
V
INL
V
INH
I
INL(IINH
I
DD
)Input current of the digital input.
Maximum input voltage for Logic “0.”
Minimum input voltage for Logic “1.”
Positive supply current.
REV. 0
Table I. Truth Table
ADG751 INSwitch Condition
0ON
1OFF
–5–
ADG751
VD OR VS DRAIN SOURCE VOLTAGE – Volts
45
15
01.0
R
ON
– V
2.03.0
40
35
30
25
20
4.05.0 5.4
VDD = +2.7V
VDD = +3.3V
VDD = +4.5V
VDD = +5.5V
TA = +258C
50
55
60
65
VD OR VS DRAIN SOURCE VOLTAGE – Volts
45
15
00.4
R
ON
– V
1.23.0
40
35
30
25
20
50
55
60
65
VDD = +3V
0.81.62.02.42.8
–408C
+258C
+858C
+1258C
–Typical Performance Characteristics
35
VDD = +2.7V
30
25
– V
20
ON
R
15
10
5
01
VD OR VS DRAIN SOURCE VOLTAGE – Volts
VDD = +3.3V
VDD = +5.5V
23 4 5
TA = +258C
VDD = +4.5V
Figure 1. On Resistance as a Function of VD (VS) Single
Supplies (A Grade)
35
VDD = +3V
30
25
+1258C
+858C
Figure 4. On Resistance as a Function of VD (VS) Single
Supplies (B Grade)
– V
20
ON
R
15
10
5
00.5
1.01.52.02.5
V
OR V
DRAIN SOURCE VOLTAGE – Volts
+258C
–408C
3.0
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures V
35
30
25
20
– V
ON
R
15
10
5
0
Figure 3. On Resistance as a Function of VD (VS) for
Different Temperatures V
01
V
OR V
= 3 V (A Grade)
DD
+1258C
+858C
+258C
23
DRAIN SOURCE VOLTAGE – Volts
= 5 V (A Grade)
DD
4
VDD = +5V
–408C
Figure 5. On Resistance as a Function of VD (VS) for
Different Temperatures V
65
60
55
50
45
40
35
– V
ON
30
R
25
20
15
10
5
0
5
0
1.04.03.0
VD OR VS DRAIN SOURCE VOLTAGE – Volts
= 3 V (B Grade)
DD
+1258C
+858C
+258C
2.0
VDD = +5V
–408C
5.0
Figure 6. On Resistance as a Function of VD (VS) for
Different Temperatures V
–6–
= 5 V (B Grade)
DD
REV. 0
0
FREQUENCY – Hz
10n
0.1
I
DD
– Amps
1k10k
100n
10m
1m
1m
10m
100k100M10M
B GRADE
A GRADE
VDD = +5V
T
A
= +258C
SOURCE VOLTAGE – Volts
0
Q
INJ
– pC
5.0
–10
2.0
1.04.03.0
–8
–6
–4
–2
0
2
4
6
VDD = +5V
TA = +258C
VDD = +3V
TA = +258C
–5
BANDWIDTH – dB
ADG751
–10
110
FREQUENCY – MHz
100
300
Figure 7. On Response vs. Frequency (A Grade)
0
TA = +258C
–5
BANDWIDTH – dB
–10
1
10
FREQUENCY – MHz
100
300
Figure 8. On Response vs. Frequency (B Grade)
0
TA = +258C
–25
Figure 10. Supply Current vs. Input Switching Frequency
Figure 11. Charge Injection vs. Source/Drain Voltage
–50
–75
OFF ISOLATION – dB
–100
–125
Figure 9. Off Isolation vs. Frequency for Both Grades
REV. 0
A GRADE
110
FREQUENCY – MHz
B GRADE
100
300
–7–
ADG751
GENERAL DESCRIPTION
The ADG751 is an SPST switch constructed using switches in a
T configuration to obtain high “OFF” isolation while maintaining good frequency response in the “ON” condition.
Figure 12 shows the T-switch configuration. While the switch is
in the OFF state, the shunt switch is closed and the two series
switches are open. The closed shunt switch provides a signal
path to ground for any of the unwanted signals that find their
way through the off capacitances of the series’ MOS devices.
This results in improved isolation between the input and output
than with an ordinary series switch. When the switch is in the
ON condition, the shunt switch is open and the signal path is
through the two series switches which are now closed.
S
IN
SERIES
SHUNT
D
Figure 12. Basic T-Switch Configuration
LAYOUT CONSIDERATIONS
Where accurate high frequency operation is important, careful
consideration should be given to the printed circuit board layout
and to grounding. Wire wrap boards, prototype boards and
sockets are not recommended because of their high parasitic
inductance and capacitance. The part should be soldered directly to a printed circuit board. A ground plane should cover all
unused areas of the component side of the board to provide a
low impedance path to ground. Removing the ground planes
from the area around the part reduces stray capacitance.
Good decoupling is important in achieving optimum performance. V
should be decoupled with a 0.1 µF surface mount
DD
capacitor to ground mounted as close as possible to the device
itself.
–8–
REV. 0
Test Circuits
V
S
V
OUT
50V
NETWORK
ANALYZER
NETWORK
ANALYZER
R
L
50V
IN
GND
V
DD
V
DD
V
IN
SD
0.1mF
INSERTIONLOSS=20LOG
V
OUT
WITHSWITCH
V
OUT
WITHOUTSWITCH
SD
V
S
RON = V1/I
ADG751
V1
IS (OFF)
I
DS
DS
V
S
SD
AA
I
(OFF)
D
NC
V
D
NC = NO CONNECT
SD
ID (ON)
A
V
D
Test Circuit 1. On Resistance
0.1mF
V
S
R
S
V
S
IN
IN
V
DD
V
DD
SD
GND
V
DD
V
DD
SD
GND
Test Circuit 2. Off Leakage
IN
V
R
L
300V
C
35pF
OUT
L
V
S
V
OUT
Test Circuit 4. Switching Times
V
IN
ON
V
C
L
1.0nF
OUT
V
OUT
50%50%V
90%90%
t
OFF
OFF
Q
= CL 3DV
INJ
Test Circuit 3. On Leakage
t
ON
DV
OUT
OUT
NETWORK
ANALYZER
V
S
REV. 0
50V
50V
Test Circuit 6. Off Isolation
Test Circuit 5. Charge Injection
V
DD
0.1mF
V
DD
SD
IN
V
IN
GND
OFF ISOLATION = 20 LOG
NETWORK
ANALYZER
V
OUT
R
L
50V
V
OUT
V
S
Test Circuit 7. Bandwidth
–9–
ADG751
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
0.006 (0.15)
0.002 (0.05)
0.071 (1.80)
0.059 (1.50)
0.051 (1.30)
0.035 (0.90)
0.122 (3.10)
0.114 (2.90)
PIN 1
SEATING
PLANE
PIN 1
0.006 (0.15)
0.000 (0.00)
85
1
4
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.018 (0.46)
0.008 (0.20)
6-Lead SOT-23
0.122 (3.10)
0.106 (2.70)
4 5 6
1
2
3
0.075 (1.90)
BSC
0.020 (0.50)
0.010 (0.25)
0.199 (5.05)
0.187 (4.75)
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
(RT-6)
0.118 (3.00)
0.098 (2.50)
0.037 (0.95) BSC
0.057 (1.45)
0.035 (0.90)
SEATING
PLANE
0.120 (3.05)
0.112 (2.84)
338
278
0.009 (0.23)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
108
08
C3569–8–4/99
0.022 (0.55)
0.014 (0.35)
–10–
PRINTED IN U.S.A.
REV. 0
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