Analog Devices ADG739, ADG738 Datasheet
ADG738/ADG739
a
REV. 0
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
CMOS, Low-Voltage, 3-Wire
Serially-Controlled, Matrix Switches
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
FEATURES
3-Wire Serial Interface
2.7 V to 5.5 V Single Supply
2.5 ⍀ On Resistance
0.75 ⍀ On-Resistance Flatness
100 pA Leakage Currents
Single 8-to-1 Multiplexer ADG738
Dual 4-to-1 Multiplexer ADG739
Power-On Reset
TTL/CMOS-Compatible
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
GENERAL DESCRIPTION
The ADG738 and ADG739 are CMOS analog matrix switches
with a serially-controlled 3-wire interface. The ADG738 is an
8-channel matrix switch, while the ADG739 is a dual 4-channel
matrix switch. On resistance is closely matched between switches
and very flat over the full signal range.
The ADG738 and ADG739 utilize a 3-wire serial interface that
is compatible with SPI™, QSPI™, MICROWIRE™, and some
DSP interface standards. The output of the shift register DOUT
enables a number of these parts to be daisy-chained. On power-up,
the internal shift register contains all zeros and all switches
are in the OFF state.
Each switch conducts equally well in both directions when on,
making these parts suitable for both multiplexing and demultiplexing applications. As each switch is turned on or off by a
separate bit, these parts can also be configured as a type of switch
array, where any, all, or none of the eight switches may be closed
at any time. The input signal range extends to the supply rails.
All channels exhibit break-before-make switching action,
preventing momentary shorting when switching channels.
The ADG738 and ADG739 are available in 16-lead TSSOP
packages.
FUNCTIONAL BLOCK DIAGRAMS
S1
S8
SCLKDDIN
SYNC
ADG738
S1A
SCLK
DA
DIN
S4A
S1B
S4B
DB
ADG739
RESET
DOUT
DOUT
SYNC
INPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
PRODUCT HIGHLIGHTS
1. 3-Wire Serial Interface.
2. Single Supply Operation. The ADG738 and ADG739 are
fully specified and guaranteed with 3 V and 5 V supply rails.
3. Low On Resistance, 2.5 Ω typical.
4. Any configuration of switches may be on or off at any one time.
5. Guaranteed Break-Before-Make Switching Action.
6. Small 16-lead TSSOP Package.
–2– REV. 0
ADG738/ADG739–SPECIFICATIONS
1
(VDD = 5 V ⴞ 10%, GND = 0 V, unless otherwise noted.)
B Version
–40ⴗC
Parameter 25ⴗC to +85ⴗC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
) 2.5 Ω typ VS = 0 V to VDD, IS = 10 mA;
4.5 5 Ω max Test Circuit 1
On-Resistance Match Between 0.4 Ω typ V
S
= 0 V to V
DD, IS
= 10 mA
Channels (∆R
ON
) 0.8 Ω max
On-Resistance Flatness (R
FLAT(ON)
)0.75 Ω typ VS = 0 V to VDD, IS = 10 mA
1.2 Ω max
LEAKAGE CURRENTS V
DD
= 5.5 V
Source OFF Leakage I
S
(OFF) ± 0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;
± 0.1 ± 0.3 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ± 0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;
± 0.1 ± 1 nA max Test Circuit 3
Channel ON Leakage I
D
, IS (ON) ±0.01 nA typ VD = VS = 1 V/4.5 V, Test Circuit 4
± 0.1 ± 1 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current, I
INL
or I
INH
0.005 µA typ VIN = V
INL
or V
INH
± 0.1 µA max
CIN, Digital Input Capacitance 3 pF typ
DIGITAL OUTPUT
Output Low Voltage 0.4 max I
SINK
= 6 mA
C
OUT
, Digital Output Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS
2
t
ON
20 ns typ RL = 300 Ω, CL = 35 pF, Test Circuit 5;
32 ns max V
S1
= 3 V
t
OFF
10 ns typ RL = 300 Ω, CL = 35 pF, Test Circuit 5;
17 ns max V
S1
= 3 V
Break-Before-Make Time Delay, t
D
9 ns typ RL = 300 Ω, CL = 35 pF;
1 ns min V
S1
= VS8 = 3 V, Test Circuit 5
Charge Injection ± 3 pC typ V
S
= 2.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 6
Off Isolation –55 dB typ R
L
= 50 Ω, CL = 5 pF, f = 10 MHz;
–75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk –55 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz;
–75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
–3 dB Bandwidth
ADG738 65 MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 8
ADG739 100 MHz typ
CS (OFF) 13 pF typ
CD (OFF)
ADG738 85 pF typ
ADG739 42 pF typ
CD, CS (ON)
ADG738 96 pF typ
ADG739 48 pF typ
POWER REQUIREMENTS V
DD
= 5.5 V
I
DD
10 µA typ Digital Inputs = 0 V or 5.5 V
20 µA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–3–REV. 0
ADG738/ADG739
B Version
–40ⴗC
Parameter 25ⴗC to +85ⴗC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
)6 Ω typ VS = 0 V to VDD, IS = 10 mA;
11 12 Ω max Test Circuit 1
On-Resistance Match Between 0.4 Ω typ V
S
= 0 V to VDD, IS = 10 mA
Channels (∆R
ON
) 1.2 Ω max
On-Resistance Flatness (R
FLAT(ON)
) 3.5 Ω typ VS = 0 V to VDD, IS = 10 mA
LEAKAGE CURRENTS V
DD
= 3.3 V
Source OFF Leakage I
S
(OFF) ± 0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V;
± 0.1 ± 0.3 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ± 0.01 nA typ VD = 3 V/1 V, VD = 1 V/3 V;
± 0.1 ± 1 nA max Test Circuit 3
Channel ON Leakage I
D
, IS (ON) ± 0.01 nA typ VD = VS = 3 V/1 V, Test Circuit 4
± 0.1 ± 1 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0 V min
Input Low Voltage, V
INL
0.4 V max
Input Current, I
INL
or I
INH
0.005 µA typ VIN = V
INL
or V
INH
± 0.1 µA max
CIN, Digital Input Capacitance 3 pF typ
DIGITAL OUTPUT
Output Low Voltage 0.4 max I
SINK
= 6 mA
C
OUT
, Digital Output Capacitance 4 pF typ
DYNAMIC CHARACTERISTICS
2
t
ON
40 ns typ RL = 300 Ω, CL = 35 pF, Test Circuit 5;
70 ns max V
S1
= 2 V
t
OFF
14 ns typ RL = 300 Ω, CL = 35 pF, Test Circuit 5;
25 ns max V
S1
= 2 V
Break-Before-Make Time Delay, t
D
12 ns typ RL = 300 Ω, CL = 35 pF;
1 ns min V
S
= 2 V, Test Circuit 5
Charge Injection ± 3 pC typ V
S
= 1.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 6
Off Isolation –55 dB typ R
L
= 50 Ω, CL = 5 pF, f = 10 MHz;
–75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk –55 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz;
–75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
–3 dB Bandwidth
ADG738 65 MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 8
ADG739 100 MHz typ
CS (OFF) 13 pF typ
CD (OFF)
ADG738 85 pF typ
ADG739 42 pF typ
CD, CS (ON)
ADG738 96 pF typ
ADG739 48 pF typ
POWER REQUIREMENTS V
DD
= 3.3 V
I
DD
10 µA typ Digital Inputs = 0 V or 3.3 V
20 µA max
NOTES
1
Temperature ranges are as follows: B Versions: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = 3 V ⴞ 10%, GND = 0 V, unless otherwise noted.)
SPECIFICATIONS
1
–4– REV. 0
ADG738/ADG739
TIMING CHARACTERISTICS
1, 2
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
f
SCLK
30 MHz max SCLK Cycle Frequency
t
1
33 ns min SCLK Cycle Time
t
2
13 ns min SCLK High Time
t
3
13 ns min SCLK Low Time
t
4
0 ns min SYNC to SCLK Active Edge Setup Time
t
5
5 ns min Data Setup Time
t
6
4.5 ns min Data Hold Time
t
7
0 ns min SCLK Falling Edge to SYNC Rising Edge
t
8
33 ns min Minimum SYNC High Time
t
9
3
20 ns min SCLK Rising Edge to DOUT Valid
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3
CL = 20 pF, RL = 1 kΩ.
Specifications subject to change without notice.
SCLK
SYNC
DIN
DB7
DB0
DB7
1
DB0
1
DOUT
NOTE
1
DATA FROM LAST WRITE CYCLE
t
3
t
2
t
1
t
4
t
8
t
6
t
5
t
9
t
7
Figure 1. 3-Wire Serial Interface Timing Diagram
(VDD = 2.7 V to 5.5 V. All specifications –40ⴗC to +85ⴗC, unless otherwise noted.)
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