Analog Devices ADG725BSU, ADG725BCP, ADG731BSU, ADG731BCP Datasheet

PRELIMINARY TECHNICAL DA T A

16-/32- Channel, Serially Controlled 4

=

1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers

Preliminary Technical Data

FEATURES
3-Wire SPI Serial Interface

1.8 V to 5.5 V Single Supply
±2.5 V Dual Supply Operation

ΩΩ

4

Ω On Resistance

ΩΩ

ΩΩ

0.5

Ω On Resistance Flatness

ΩΩ

7mm x 7mm 48 lead Chip Scale Package (CSP)

or 48 lead TQFP package.
Rail to Rail Operation
Power On Reset
Fast Switching Times
Single 32 to 1 Channel Multiplexer
Dual/Differential 16 to 1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent devices with Parallel Interface

See ADG726/ADG732

APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay replacement
Audio and Video Switching
Battery Powered Systems
Medical Instrumentation
Automatic Test Equipment

S32

ΩΩ

Ω

ΩΩ

ADG725/ADG731

FUNCTIONAL BLOCK DIAGRAMS

ADG731

S1

INPUT SHIFT

REGISTER

SCLK

DIN

SYNC

S1A

S16A

D

S1B

S16B

ADG725

INPUT SHIFT

REGISTER

SCLK

DA

DB

DIN SYNC

GENERAL DESCRIPTION

The ADG725/ADG731 are monolithic CMOS 32
channel/dual 16 channel analog multiplexers with a
serially controlled 3-wire interface. The ADG732 switches
one of thirty-two inputs (S1-S32) to a common output, D.
The ADG725 can be configured as a dual mux switching
one of sixteen inputs to one output or a differential mux
switching one of sixteen inputs to a differential output.

These mulitplexers utilize a 3-wire serial interface that is
compatible with SPI
some DSP interface standards. On power-up, the internal
shift register contains all zeros and all switch are in the
OFF state.

These multiplexers are designed on an enhanced submi­cron process that provides low power dissipation yet gives
high switching speed, very low on resistance and leakage
currents. They operate from single supply of 1.8V to 5.5V
and ±2.5 V dual supply, making them ideally suited to a
variety of applications. On resistance is in the region of a
few Ohms and is closely matched between switches and
very flat over the full signal range. These parts can operate
equally well as either Multiplexers or De-Multiplexers

REV. PrD May 2002

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

TM

, QSPITM, MICROWIRETM and

and have an input signal range which extends to the sup­plies. In the OFF condition, signal levels up to the
supplies are blocked. All channels exhibit break before
make switching action preventing momentary shorting
when switching channels.

They are available in either 48 lead CSP or TQFP
package.

PRODUCT HIGHLIGHTS

1. 3-Wire Serial Interface.

2. +1.8 V to +5.5 V Single or ±2.5 V Dual Supply
operation. These parts are specified and guaranteed
with +5 V ±10%, +3 V ±10% single supply and
±2.5 V ±10% dual supply rails.

3. On Resistance of 4 Ω.

4. Guaranteed Break-Before-Make Switching Action.

5. 7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] Analog Devices, Inc., 2002

PRELIMINARY TECHNICAL DA T A

1

ADG725/ADG731–SPECIFICATIONS

B Version

–40°C

Parameter +25oC to +85°C Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On-Resistance (R

On-Resistance Match Between 0.3 Ω typ V
Channels (∆R
On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I
ADG725 ±0.5 ±2.5 nA max Test Circuit 3
ADG731 ±1 ±5 nA max
Channel ON Leakage I
ADG725 ±0.5 ±2.5 nA max Test Circuit 4
ADG726 ±1 ±5 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current

I

or I

INL

INH

CIN, Digital Input Capacitance 5 pF typ

DYNAMIC CHARACTERISTICS

t

TRANSITION

Break-Before-Make Time Delay, t

Charge Injection ±5 pC typ V

Off Isolation -60 dB typ R

Channel to Channel Crosstalk -60 dB typ R

-3 dB Bandwidth
ADG725 34 MHz typ R
ADG731 18 MHz typ

(OFF) 13 pF typ f = 1 MHz

C

S

C

(OFF)

D

ADG725 180 pF typ f = 1 MHz
ADG731 360 pF typ f = 1 MHz

, CS (ON)

C

D

ADG725 200 pF typ f = 1 MHz
ADG731 400 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)4 Ω typ V

ON

5.5 6 Ω max Test Circuit 1

) 0.8 Ω max

ON

FLAT(ON)

) 0.5 Ω typ V

1 Ω max

(OFF) ±0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;

S

±0.25 ±0.5 nA max Test Circuit 2

(OFF) ±0.05 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;

D

, IS (ON) ±0.05 nA typ VD = VS = 1 V, or 4.5V;

D

INH

INL

2.4 V min

0.8 V max

0.005 µA typ VIN = V
±0.1 µA max

2

40 ns typ R

60 ns max V

30 ns typ R

D

1 ns min V

10 µA typ Digital Inputs = 0 V or +5.5 V

20 µA max

(VDD = 5V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)

V

DD

= 0 V to VDD, IDS = 10 mA;

S

= 0 V to V

S

= 0 V to VDD, IDS = 10 mA

S

= 5.5 V

DD

INL

= 300 Ω, C

L

= 3 V/0 V, V

S1

= 300 Ω, C

L

= 3 V, Test Circuit 6

S

= 0 V, R

S

, IDS = 10 mA

DD

or V

INH

= 35 pF,Test Circuit 5;

L

= 0 V/3V

S32

= 35 pF;

L

= 0 Ω, C

S

= 1 nF;

L

Test Circuit 7

= 50 Ω, C

L

= 5 pF, f = 100 kHz;

L

Test Circuit 8

= 50 Ω, C

L

= 5 pF, f = 100 kHz;

L

Test Circuit 9

= 50 Ω, C

L

= +5.5 V

DD

= 5 pF, Test Circuit 10

L

–2– REV. PrD

PRELIMINARY TECHNICAL DA T A

ADG725/ADG731

1

SPECIFICATIONS

Parameter +25oC to +85°C Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On-Resistance (R

On-Resistance Match Between 0.4 Ω typ V
Channels (∆R
On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I
ADG725 ±0.5 ±2.5 nA max Test Circuit 3
ADG731 ±1 ±5 nA max
Channel ON Leakage I
ADG725 ±0.5 ±2.5 nA max Test Circuit 4
ADG731 ±1 ±5 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current

or I

I

INL

INH

CIN, Digital Input Capacitance 5 pF typ

DYNAMIC CHARACTERISTICS

t

TRANSITION

Break-Before-Make Time Delay, t

Charge Injection ±5 pC typ V

Off Isolation -60 dB typ R

Channel to Channel Crosstalk -60 dB typ R

-3 dB Bandwidth
ADG725 34 MHz typ R
ADG731 18 MHz typ

(OFF) 13 pF typ f = 1 MHz

C

S

C

(OFF)

D

ADG725 180 pF typ f = 1 MHz
ADG731 360 pF typ f = 1 MHz

, CS (ON)

C

D

ADG725 200 pF typ f = 1 MHz
ADG731 400 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

NOTES

1

Temperature ranges are as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)7 Ω typ V

ON

)1Ω max

ON

D

D

INH

INL

(VDD = 3V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)

B Version

–40°C

V

DD

= 0 V to VDD, IDS = 10 mA;

S

11 12 Ω max Test Circuit 1

= 0 V to V

S

FLAT(ON)

(OFF) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V;

S

)3Ω max V

= 0 V to VDD, IDS = 10 mA

S

= 3.3 V

DD

, IDS = 10 mA

DD

±0.25 ±0.5 nA max Test Circuit 2

(OFF) ±0.05 nA typ VS = 1 V/3 V, VD = 3 V/1 V;

, IS (ON) ±0.05 nA typ VS = VD = +1 V or +3 V;

2.0 V min

0.8 V max

0.005 µA typ VIN = V

INL

or V

INH

±0.1 µA max

2

45 ns typ R

75 ns max V

30 ns typ R

D

1 ns min V

= 300 Ω, C

L

= 2 V/0 V, V

S1

= 300 Ω, C

L

= 2 V, Test Circuit 6

S

= 0 V, R

S

= 35 pF Test Circuit 5

L

= 0 V/2 V

S32

= 35 pF;

L

= 0 Ω, C

S

= 1 nF;

L

Test Circuit 7

= 50 Ω, C

L

= 5 pF, f = 1 MHz;

L

Test Circuit 8

= 50 Ω, C

L

= 5 pF, f = 1 MHz;

L

Test Circuit 9

= 50 Ω, C

L

= +3.3 V

DD

= 5 pF, Test Circuit 10

L

10 µA typ Digital Inputs = 0 V or +3.3 V

20 µA max

–3–REV. PrD

PRELIMINARY TECHNICAL DA T A

1

ADG725/ADG731–SPECIFICATIONS

(VDD = +2.5 V ±10%, VSS = -2.5 V ±10%, GND = 0 V, unless otherwise noted)

B Version

–40°C

Parameter +25oC to +85°C Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VSS to V
On-Resistance (R

On-Resistance Match Between 0.3 Ω typ V
Channels (∆R
On-Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I

Channel ON Leakage I

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current

I

or I

INL

INH

CIN, Digital Input Capacitance 5 pF typ

DYNAMIC CHARACTERISTICS

t

TRANSITION

Break-Before-Make Time Delay, t

Charge Injection ±8 pC typ V
Off Isolation -60 dB typ R

Channel to Channel Crosstalk -60 dB typ R

-3 dB Bandwidth
ADG725 34 MHz typ R
ADG731 18 MHz typ
C

(OFF) 13 pF typ

S

(OFF)

C

D

ADG725 180 pF typ f = 1 MHz
ADG731 360 pF typ f = 1 MHz

, CS (ON)

C

D

ADG725 200 pF typ f = 1 MHz
ADG731 400 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

I

SS

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)4 Ω typ V

ON

5.5 6 Ω max Test Circuit 1

) 0.8 Ω max

ON

FLAT(ON)

) 0.5 Ω typ V

1 Ω max

(OFF) ±0.01 nA typ

S

±0.25 ±0.5 nA max Test Circuit 2

(OFF) ±0.05 nA typ

D

±0.5 ±2.5 nA max Test Circuit 3
±1 ±5 nA max

, IS (ON) ±0.01 nA typ

D

±0.5 ±2.5 nA max
±1 ±5 nA max

INH

INL

1.7 V min

0.7 V max

0.005 µA typ VIN = V
±0.1 µA max

2

40 ns typ R

60 ns max V

15 ns typ R

D

1 ns min V

10 µA typ Digital Inputs = 0 V or +2.75 V

20 µA max

10 µA typ VSS = -2.75 V

20 µA max Digital Inputs = 0 V or +2.75 V

Dual Supply

DD

V

= VSS to VDD, IDS = 10 mA;

S

= VSS to VDD, IDS = 10 mA

S

= VSS to VDD, IDS = 10 mA

S

= +2.75 V, VSS = -2.75 V

DD

VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V;

VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V;

VS = VD = +2.25 V/-1.25 V, Test Circuit 4

or V

INL

= 300 Ω, C

L

= 1.5 V/0 V,V

S1

= 300 Ω, C

L

= 1.5 V, Test Circuit 6

S

= 0 V, R

S

= 50 Ω, C

L

INH

= 35 pF Test Circuit 5

L

= 0 V/1.5 V

S32

= 35 pF;

L

= 0 Ω, C

S

= 5 pF, f = 1 MHz;

L

= 1 nF; Test 7

L

Test Circuit 8

= 50 Ω, C

L

= 5 pF, f = 1 MHz;

L

Test Circuit 9

= 50 Ω, C

L

= +2.75 V

DD

= 5 pF, Test Circuit 10

L

–4– REV. PrD

PRELIMINARY TECHNICAL DA T A

ADG725/ADG731

TIMING CHARACTERISTICS

1,2

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

See Figure 1.

2

All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Specifications subject to change without notice.

33 ns min SCLK Cycle time
13 ns min SCLK High Time
13 ns min SCLK Low Time
13 ns min SYNC to SCLK falling edge setup time
40 ns min Minimum SYNC low time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
33 ns min Minimum SYNC high time

SCLK

SYNC

DIN

, T

MIN

MAX

t

8

t

4

t

5

t

7

t

6

DB7

Units Conditions/Comments

t

1

t

2

t

3

DB0

Figure 1. 3-Wire Serial Interface Timing Diagram.

DB7 (MSB)

EN CSA

CSB

A3 A2 A1 A0

X

DATA BITS

DB0 (LSB)

DB7 (MSB)

EN CS X

A4 A3 A2 A1 A0

DATA BITS

DB0 (LSB)

Figure 2. ADG725 Input Shift Register Contents Figure 3. ADG731 Input Shift Register Contents

–5–REV. PrD