ANALOG DEVICES ADG725, ADG731 Service Manual

16-/32-Channel, Serially Controlled 4 ⍀

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a

FEATURES
3-Wire SPI Compatible Serial Interface

1.8 V to 5.5 V Single Supply
ⴞ2.5 V Dual-Supply Operation
4 ⍀ On Resistance

0.5 ⍀ On Resistance Flatness
7 mm x 7 mm 48-Lead Chip Scale Package (LFCSP)

or 48-Lead TQFP Package
Rail-to-Rail Operation
Power-On Reset
42 ns Switching Times
Single 32-to-1 Channel Multiplexer
Dual/Differential 16-to-1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent Devices with Parallel

Interface, See ADG726/ADG732

APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
Medical Instrumentation
Automatic Test Equipment

1.8 V to 5.5 V, ⴞ2.5 V, Analog Multiplexers

S32

ADG725/ADG731

FUNCTIONAL BLOCK DIAGRAM

ADG731

S1

INPUT SHIFT

REGISTER

SCLK DIN

SYNC

S1A

S16A

D

S1B

S16B

ADG725

INPUT SHIFT

REGISTER

SCLK

DIN

DA

DB

SYNC

GENERAL DESCRIPTION

The ADG731/ADG725 are monolithic, CMOS, 32-channel/
dual 16-channel analog multiplexers with a serially controlled
3-wire interface. The ADG731 switches one of 32 inputs
(S1–S32) to a common output, D. The ADG725 can be config­ured as a dual mux switching one of 16 inputs to one output, or a
differential mux switching one of 16 inputs to a differential output.

These mulitplexers utilize a 3-wire serial interface that is com­patible with SPI
interface standards. On power-up, the Internal Shift Register
contains all zeros and all switches are in the OFF state.

These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high switch­ing speed with very low on resistance and leakage currents.
They operate from a single supply of 1.8 V to 5.5 V or a
± 2.5 V dual supply, making them ideally suited to a variety of
applications. On resistance is in the region of a few ohms, is
closely matched between switches, and is very flat over the full
signal range.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

®

, QSPI™, MICROWIRE™, and some DSP

These parts can operate equally well as either multiplexers or
demultiplexers and have an input signal range that extends to the
supplies. In the OFF condition, signal levels up to the supplies
are blocked. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.

The ADG731 and ADG725 are serially controlled 32-channel,
and dual/differential 16-channel multiplexers, respectively. They
are available in either a 48-lead LFCSP or TQFP package.

PRODUCT HIGHLIGHTS

1. 3-Wire Serial Interface.

2. 1.8 V to 5.5 V Single-Supply or ± 2.5 V Dual-Supply
Operation. These parts are specified and guaranteed
with 5 V ± 10%, 3 V ± 10% single-supply,
and ± 2.5 V ± 10% dual-supply rails.

3. On Resistance of 4 W.

4. Guaranteed Break-Before-Make Switching Action.

5. 7 mm ¥ 7 mm 48-Lead Chip Scale Package (LFCSP) or
48-Lead TQFP Package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

1

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ADG725/ADG731–SPECIFICATIONS

(VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)

B Version

Parameter +25⬚C –40⬚C to +85⬚C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 to V
On Resistance (R

)4 Ω typ VS = 0 V to VDD, IDS = 10 mA;

ON

DD

V

5.5 6 Ω max Test Circuit 1
On Resistance Match between 0.3 Ω typ V
Channels (∆R
On Resistance Flatness (R

) 0.8 Ω max

ON

FLAT(ON)

) 0.5 Ω typ VS = 0 V to VDD, IDS = 10 mA

= 0 V to VDD, IDS = 10 mA

S

1 Ω max

LEAKAGE CURRENTS V

Source OFF Leakage I

(OFF) ± 0.01 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;

S

= 5.5 V

DD

± 0.25 ± 1nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ± 0.05 nA typ VD = 4.5 V/1 V, VS = 1 V/4.5 V;

D

ADG725 ± 0.5 ± 2.5 nA max Test Circuit 3
ADG731 ± 1 ±5nA max

Channel ON Leakage I

, IS (ON) ±0.05 nA typ VD = VS = 1 V or 4.5 V;

D

ADG725 ± 0.5 ± 2.5 nA max Test Circuit 4
ADG731 ± 1 ±5nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

INL

INH

2.4 V min

0.8 V max

Input Current

I

INL

or I

INH

0.005 µA typ VIN = V

INL

or V

INH

± 0.5 µA max

CIN, Digital Input Capacitance 5 pF typ

DYNAMIC CHARACTERISTICS

t

TRANSITION

Break-Before-Make Time Delay, t

Charge Injection 5 pC typ V

2

42 ns typ RL = 300 Ω, CL = 35 pF; Test Circuit 5
53 62 ns max V

D

30 ns typ RL = 300 Ω, CL = 35 pF

1 ns min V

= 3 V/0 V, V

S1

= 3 V; Test Circuit 6

S

= 2.5 V, RS = 0 Ω, CL = 1 nF;

S

= 0 V/3 V

S32

Test Circuit 7

Off Isolation –72 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

Channel-to-Channel Crosstalk –72 dB typ R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 9

–3 dB Bandwidth

ADG725 34 MHz typ R

= 50 Ω, CL = 5 pF; Test Circuit 10

L

ADG731 18 MHz typ

(OFF) 15 pF typ f = 1 MHz

C

S

C

(OFF)

D

ADG725 170 pF typ f = 1 MHz
ADG731 340 pF typ f = 1 MHz

, CS (ON)

C

D

ADG725 175 pF typ f = 1 MHz
ADG731 350 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

10 µA typ Digital Inputs = 0 V or 5.5 V

= 5.5 V

DD

20 µA max

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. A–2–

ADG725/ADG731

www.BDTIC.com/ADI

1

SPECIFICATIONS

Parameter +25⬚C –40⬚C to +85⬚C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 to V
On Resistance (R

On Resistance Match between 0.35 Ω typ V
Channels (∆R
On Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I

ADG725 ± 0.5 ± 2.5 nA max Test Circuit 3
ADG731 ± 1 ± 5nA max

Channel ON Leakage I

ADG725 ± 0.5 ± 2.5 nA max Test Circuit 4
ADG731 ± 1 ± 5nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current

or I

I

INL

INH

CIN, Digital Input Capacitance 5 pF typ

DYNAMIC CHARACTERISTICS

t

TRANSITION

Break-Before-Make Time Delay, t

Charge Injection 1 pC typ V

Off Isolation –72 dB typ R

Channel-to-Channel Crosstalk –72 dB typ R

–3 dB Bandwidth

ADG725 34 MHz typ R
ADG731 18 MHz typ

(OFF) 15 pF typ f = 1 MHz

C

S

C

(OFF)

D

ADG725 170 pF typ f = 1 MHz
ADG731 340 pF typ f = 1 MHz

, CS (ON)

C

D

ADG725 175 pF typ f = 1 MHz
ADG731 350 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)7 Ω typ VS = 0 V to VDD, IDS = 10 mA;

ON

)1Ω max

ON

(OFF) ± 0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V;

S

(OFF) ± 0.05 nA typ VS = 1 V/3 V, VD = 3 V/1 V;

D

, IS (ON) ± 0.05 nA typ VS = VD = 1 V or 3 V;

D

INH

INL

(VDD = 3 V  10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)

B Version

DD

V

11 12 Ω max Test Circuit 1

FLAT(ON)

)3Ω max VS = 0 V to VDD, IDS = 10 mA

± 0.25 ±1nA max Test Circuit 2

2.0 V min

0.7 V max

0.005 µA typ VIN = V
± 0.5 µA max

2

60 ns typ RL = 300 Ω, CL = 35 pF; Test Circuit 5
80 90 ns max V

D

30 ns typ RL = 300 Ω, CL = 35 pF

1 ns min V

5 µA typ Digital Inputs = 0 V or 3.3 V

10 µA max

= 0 V to VDD, IDS = 10 mA

S

= 3.3 V

DD

or V

INL

= 2 V/0 V, V

S1

= 2 V; Test Circuit 6

S

= 0 V, RS = 0 Ω, CL = 1 nF;

S

INH

= 0 V/2 V

S32

Test Circuit 7

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 8

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 9

= 50 Ω, CL = 5 pF; Test Circuit 10

L

= 3.3 V

DD

REV. A

–3–

ADG725/ADG731

www.BDTIC.com/ADI

(VDD = +2.5 V  10%, VSS = –2.5 V  10%, GND = 0 V,

1

DUAL-SUPPLY SPECIFICATIONS

B Version

Parameter +25⬚C –40⬚C to +85⬚C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VSS to V
On Resistance (R

On Resistance Match Between 0.3 Ω typ V
Channels (∆R
On Resistance Flatness (R

LEAKAGE CURRENTS V

Source OFF Leakage I

Drain OFF Leakage I

ADG725 ± 0.5 ± 2.5 nA max Test Circuit 3
ADG731 ± 1 ±5nA max

Channel ON Leakage I

ADG725 ± 0.5 ± 2.5 nA max
ADG731 ± 1 ±5nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current

or I

I

INL

INH

CIN, Digital Input Capacitance 5 pF typ

DYNAMIC CHARACTERISTICS

t

TRANSITION

Break-Before-Make Time Delay, t

Charge Injection 1 pC typ V
Off Isolation –72 dB typ R

Channel-to-Channel Crosstalk –72 dB typ R

–3 dB Bandwidth

ADG725 34 MHz typ R
ADG731 18 MHz typ

(OFF) 13 pF typ

C

S

(OFF)

C

D

ADG725 130 pF typ f = 1 MHz
ADG731 260 pF typ f = 1 MHz

, CS (ON)

C

D

ADG725 150 pF typ f = 1 MHz
ADG731 300 pF typ f = 1 MHz

POWER REQUIREMENTS V

I

DD

I

SS

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

)4 Ω typ VS = VSS to VDD, IDS = 10 mA;

ON

5.5 6 Ω max Test Circuit 1

) 0.8 Ω max

ON

FLAT(ON)

(OFF) ± 0.01 nA typ

S

) 0.5 Ω typ VS = VSS to VDD, IDS = 10 mA

± 0.25 ± 0.5 nA max Test Circuit 2

(OFF) ± 0.05 nA typ

D

, IS (ON) ± 0.01 nA typ

D

INH

INL

0.005 µA typ VIN = V

2

55 ns typ RL = 300 Ω, CL = 35 pF; Test Circuit 5
75 84 ns max V

D

15 ns typ RL = 300 Ω, CL = 35 pF

10 µA typ Digital Inputs = 0 V or 2.75 V

10 µA typ VSS = –2.75 V

unless otherwise noted.)

V

DD

= VSS to VDD, IDS = 10 mA

S

1 Ω max

= +2.75 V, VSS = –2.75 V

DD

VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;

VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;

VS = VD = +2.25 V/–1.25 V; Test Circuit 4

1.7 V min

0.7 V max

or V

INL

INH

± 0.5 µA max

1 ns min V

= 1.5 V/0 V, V

S1

= 1.5 V; Test Circuit 6

S

= 0 V, RS = 0 Ω, CL = 1 nF; Test Circuit 7

S

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

= 0 V/1.5 V

S32

Test Circuit 8

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Test Circuit 9

= 50 Ω, CL = 5 pF; Test Circuit 10

L

= +2.75 V

DD

20 µA max

20 µA max Digital Inputs = 0 V or 2.75 V

REV. A–4–

ADG725/ADG731

www.BDTIC.com/ADI

TIMING CHARACTERISTICS

1, 2

Parameter Limit at T

f

SCLK

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

See Figure 1.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Specifications subject to change without notice.

30 MHz max SCLK Cycle Frequency
33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
13 ns min SYNC to SCLK Falling Edge Setup Time
40 ns min Minimum SYNC Low Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
33 ns min Minimum SYNC High Time

SCLK

SYNC

DIN

MIN

t8t

, T

MAX

4

DB7

Unit Conditions/Comments

t

1

t

2

t

5

t

7

t

6

t

3

DB0

Figure 1. 3-Wire Serial Interface Timing Diagram

DB7 (MSB)

CSA

EN

CSB

A3 A2 A1 A0

X

DATA BITS

DB0 (LSB)

Figure 2. ADG725 Input Shift Register Contents

DB7 (MSB)

EN CS

X

A3 A2 A1 A0

A4

DATA BITS

DB0 (LSB)

Figure 3. ADG731 Input Shift Register Contents

REV. A

–5–