1.8 V to 5.5 V single supply
4 Ω (max) on resistance
Low on resistance flatness
−3 dB bandwidth >200 MHz
Tiny package options
8-lead MSOP
3 mm × 2 mm LFCSP (A grade)
Fast switching times
t
, 20 ns
ON
t
, 10 ns
OFF
Low power consumption (<0.1 μW)
TTL/CMOS compatible
APPLICATIONS
USB 1.1 signal switching circuits
Cell phones
PDAs
Battery-powered systems
Communication systems
Sample hold systems
Audio signal routing
Video switching
Mechanical reed relay replacement
GENERAL DESCRIPTION
The ADG721, ADG722, and ADG723 are monolithic CMOS
SPST switches. These switches are designed on an advanced
submicron process that provides low power dissipation yet gives
high switching speed, low on resistance, and low leakage
currents. The devices are packaged in both a tiny 3 mm × 2 mm
LFCSP and an MSOP, making them ideal for space-constrained
applications.
The ADG721, ADG722, and ADG723 are designed to operate
rom a single 1.8 V to 5.5 V supply, making them ideal for use
f
in battery-powered instruments and with the new generation of
DACs and ADCs from Analog Devices, Inc.
The ADG721, ADG722, and ADG723 contain two independent
sin
gle-pole/single-throw (SPST) switches. The ADG721 and
ADG722 differ only in that both switches are normally open
Switches in 3 mm × 2 mm LFCSP
ADG721/ADG722/ADG723
FUNCTIONAL BLOCK DIAGRAMS
S1
D1
IN2
ADG722
IN1
D2
S2
00045-003
IN1
D2
S2
00045-002
ADG721
S1
D1
IN2
Figure 1. Figure 2.
IN1
D2
S2
00045-001
ADG723
S1
D1
IN2
SWITCHES SHOWN FOR
A LOGIC "0" INPUT
Figure 3.
and normally closed, respectively. In the ADG723, Switch 1 is
normally open and Switch 2 is normally closed.
Each switch of the ADG721, ADG722, and ADG723 conducts
ually well in both directions when on. The ADG723 exhibits
eq
break-before-make switching action.
PRODUCT HIGHLIGHTS
1. 1.8 V to 5.5 V single-supply operation.
r y low R
2. Ve
3. L
ow on resistance flatness.
4. −3 dB ban
5. L
ow power dissipation. CMOS construction ensures low
power dissipation.
6. 8-lead MSO
(4 Ω max at 5 V, 10 Ω max at 3 V).
ON
dwidth >200 MHz.
P and 3 mm × 2 mm LFCSP.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VDD = 5 V ± 10%, GND = 0 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 1.
A, B Grade
1
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance, RON 2.5 Ω typ VS = 0 V to VDD, IS = −10 mA
4 5 Ω max See Figure 12
On Resistance Match Between Channels, ∆RON 0.3 Ω typ VS = 0 V to VDD, IS = −10 mA
1.0 Ω max
On Resistance Flatness, R
0.85 Ω typ VS = 0 V to VDD, IS = −10 mA
FLAT(ON)
1.5 Ω max
LEAKAGE CURRENTS – A Grade VDD = 5.5 V
Source off Leakage, IS (OFF) ±0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V, see Figure 13
Drain off Leakage, ID (OFF) ±0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V, see Figure 13
Channel on Leakage, ID, IS (ON) ±0.01 nA typ VS = VD = 1 V or VS = VD = 4.5 V, see Figure 14
LEAKAGE CURRENTS – B Grade VDD = 5.5 V
Source off Leakage, IS (OFF) ±0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V
±0.25 ±0.35 nA max Test Circuit 2
Drain off Leakage, ID (OFF) ±0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V
±0.25 ±0.35 nA max See Figure 13
Channel on Leakage, ID, IS (ON) ±0.01 nA typ VS = VD = 1 V or VS = VD = 4.5 V
±0.25 ±0.35 nA max See Figure 14
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
2.4 V min
INH
0.8 V max
INL
Input Current
I
or I
0.005 μA typ VIN = V
INL
INH
INL
or V
INH
±0.1 μA max
DYNAMIC CHARACTERISTICS2
tON 14 ns typ RL = 300 Ω, CL = 35 pF
20 ns max VS = 3 V, see Figure 15
t
6 ns typ RL = 300 Ω, CL = 35 pF
OFF
10 ns max VS = 3 V, see Figure 15
Break-Before-Make Time Delay, tD (ADG723 Only) 7 ns typ RL = 300 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 3 V, see Figure 16
Charge Injection 2 pC typ VS = 2 V, RS = 0 Ω, CL = 1 nF, see Figure 17
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz
−80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 18
Channel-to-Channel Crosstalk −77 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz
−97 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 19
Bandwidth −3 dB 200 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 20
CS (OFF) 7 pF typ
CD (OFF) 7 pF typ
CD, CS (ON) 18 pF typ
POWER REQUIREMENTS VDD = 5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or 5 V
1.0 μA max
1
Temperature range: A, B grades, −40°C to +85°C. All specifications apply to both grades unless otherwise stated.
2
Guaranteed by design; not subject to production test.
Rev. B | Page 3 of 16
ADG721/ADG722/ADG723
www.BDTIC.com/ADI
VDD = 3 V ± 10%, GND = 0 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2.
A, B Grades
1
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance, RON 6.5 Ω typ VS = 0 V to VDD, IS = −10 mA
10 Ω max See Figure 12
On Resistance Match Between Channels, ∆RON 0.3 Ω typ VS = 0 V to VDD, IS = −10 mA
1.0 Ω max
On Resistance Flatness, R
3.5 Ω typ VS = 0 V to VDD, IS = −10 mA
FLAT(ON)
LEAKAGE CURRENTS – A Grade VDD = 3.3 V
Source off Leakage, IS (OFF) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V, see Figure 13
Drain off Leakage, ID (OFF) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V, see Figure 13
Channel on Leakage, ID, IS (ON) ±0.01 nA typ VS = VD = 1 V or 3 V, Figure 14
LEAKAGE CURRENTS – B Grade VDD = 3.3 V
Source off Leakage, IS (OFF) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V
±0.25 ±0.35 nA max See Figure 13
Drain off Leakage, ID (OFF) ±0.01 nA typ VS = 3 V/1 V, VD = 1 V/3 V
±0.25 ±0.35 nA max See Figure 13
Channel on Leakage, ID, IS (ON) ±0.01 nA typ VS = VD = 1 V or 3 V
±0.25 ±0.35 nA max See Figure 14
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
2.0 V min
INH
0.4 V max
INL
Input Current
I
or I
0.005 μA typ VIN = V
INL
INH
INL
or V
INH
±0.1 μA max
DYNAMIC CHARACTERISTICS2
tON 16 ns typ RL = 300 Ω, CL = 35 pF
24 ns max VS = 2 V, see Figure 15
t
7 ns typ RL = 300 Ω, CL = 35 pF
OFF
11 ns max VS = 2 V, see Figure 15
Break-Before-Make Time Delay, tD (ADG723 Only) 7 ns typ RL = 300 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 2 V, see Figure 16
Charge Injection 2 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF, see Figure 17
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz
−80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 18
Channel-to-Channel Crosstalk −77 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz
−97 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 19
Bandwidth −3 dB 200 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 20
CS (OFF) 7 pF typ
CD (OFF) 7 pF typ
CD, CS (ON) 18 pF typ
POWER REQUIREMENTS VDD = 3.3 V
IDD 0.001 μA typ Digital inputs = 0 V or 3 V
1.0 μA max
1
Temperature range: A, B Grades, −40°C to +85°C. All specifications apply to both grades unless otherwise stated.
2
Guaranteed by design; not subject to production test.
Rev. B | Page 4 of 16
ADG721/ADG722/ADG723
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
Analog, Digital Inputs1
Continuous Current, S or D 30 mA
Operating Temperature Range
Industrial (A, B Grade) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature +150°C
8-Lead MSOP
θJA Thermal Impedance1 50.8°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Lead-Free Temperature,
Soldering
IR Reflow, Peak Temperature 260°C (+0/−5°C)
Time at Peak Temperature 10 sec to 40 sec
ESD 2 kV
1
Assumes exposed paddle is tied to ground.
−0.3 V to V
whichever occurs first
+ 0.3 V or 30 mA,
DD
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 5 of 16
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