FEATURES
+1.8 V to +5.5 V Single Supply
2 ⍀ (Typ) On Resistance
Low On-Resistance Flatness
–3 dB Bandwidth >200 MHz
Rail-to-Rail Operation
6-Lead SOT-23
8-Lead SOIC Package
Fast Switching Times
t
18 ns
ON
t
12 ns
OFF
Typical Power Consumption (<0.01 W)
TTL/CMOS Compatible
APPLICATIONS
Battery Powered Systems
Communication Systems
Sample Hold Systems
Audio Signal Routing
Video Switching
Mechanical Reed Relay Replacement
Low Voltage 2 ⍀ SPST Switches
ADG701/ADG702
FUNCTIONAL BLOCK DIAGRAMS
ADG701
S
ADG702
S
SWITCHES SHOWN FOR
A LOGIC "1" INPUT
D
IN
D
IN
GENERAL DESCRIPTION
The ADG701/ADG702 are monolithic CMOS SPST switches.
These switches are designed on an advanced submicron process
that provides low power dissipation yet high switching speed,
low on resistance, low leakage currents and –3 dB bandwidths of
greater than 200 MHz can be achieved.
The ADG701/ADG702 can operate from a single +1.8 V to
+5.5 V supply making it ideal for use in battery powered instruments and with the new generation of DACs and ADCs from
Analog Devices.
As can be seen from the Functional Block Diagrams, with a
logic input of “1” the switch of the ADG701 is closed, while
that of the ADG702 is open. Each switch conducts equally well
in both directions when ON.
The ADG701/ADG702 are available in 6-lead SOT-23 and
8-lead µSOIC packages.
PRODUCT HIGHLIGHTS
1. +1.8 V to +5.5 V Single Supply Operation. The ADG701/
ADG702 offer high performance, including low on resistance
and fast switching times and is fully specified and guaranteed
with +3 V and +5 V supply rails.
2. Very Low R
operation, R
3. On-Resistance Flatness R
(3 Ω max at 5 V, 5 Ω max at 3 V). At 1.8 V
ON
is typically 40 Ω over the temperature range.
ON
FLAT(ON)
(1 Ω max).
4. –3 dB Bandwidth >200 MHz.
5. Low Power Dissipation. CMOS construction ensures low
power dissipation.
6. Fast t
ON/tOFF.
7. Tiny 6-Lead SOT-23 and 8-Lead µSOIC.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
(VDD = 5 V ⴞ 10%, GND = 0 V. All specifications –40ⴗC to +85ⴗC
1
ADG701/ADG702–SPECIFICATIONS
unless otherwise noted.)
B Version
Parameter+25ⴗC–40ⴗC to +85ⴗCUnitsTest Conditions/Comments
ANALOG SWITCH
Analog Signal Range0 V to V
On Resistance (R
)2Ω typV
ON
DD
V
= 0 V to VDD, IS = –10 mA;
S
34Ω maxTest Circuit 1
On-Resistance Flatness (R
FLAT(ON)
)0.5Ω typV
= 0 V to VDD, IS = –10 mA
S
1.0Ω max
LEAKAGE CURRENTSV
Source OFF Leakage I
(OFF)±0.01nA typV
S
= +5.5 V
DD
= 4.5 V/1 V, VD = 1 V/4.5 V;
S
±0.25±0.35nA maxTest Circuit 2
Drain OFF Leakage I
(OFF)±0.01nA typV
D
= 4.5 V/1 V, VD = 1 V/4.5 V;
S
±0.25±0.35nA maxTest Circuit 2
Channel ON Leakage I
(ON)±0.01nA typV
D
S
= VD = 1 V, or 4.5 V;
S
, I
±0.25±0.35nA maxTest Circuit 3
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.4V min
0.8V max
Input Current
I
INL
or I
INH
0.005µA typV
IN
= V
INL
or V
INH
±0.1µA max
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Charge Injection5pC typV
2
12ns typR
18ns maxV
8ns typR
12ns maxV
= 300 Ω, C
L
= 3 V; Test Circuit 4
S
= 300 Ω, C
L
= 3 V; Test Circuit 4
S
= 2 V, R
S
= 35 pF
L
= 35 pF
L
= 0 Ω, C
S
= 1 nF;
L
Test Circuit 5
Off Isolation–55dB typR
–75dB typR
= 50 Ω, C
L
= 50 Ω, C
L
= 5 pF, f = 10 MHz
L
= 5 pF, f = 1 MHz;
L
Test Circuit 6
Bandwidth –3 dB200MHz typR
= 50 Ω, C
L
= 5 pF;
L
Test Circuit 7
(OFF)17pF typ
C
S
(OFF)17pF typ
C
D
CD, CS (ON)38pF typ
POWER REQUIREMENTSV
= +5.5 V
DD
Digital Inputs = 0 V or 5 V
I
DD
0.001µA typ
1.0µA max
NOTES
1
Temperature ranges are as follows: B Versions: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–REV. A
ADG701/ADG702
1
SPECIFICATIONS
Parameter+25ⴗC–40ⴗC to +85ⴗCUnitsTest Conditions/Comments
ANALOG SWITCH
Analog Signal Range0 V to V
On Resistance (R
On-Resistance Flatness (R
LEAKAGE CURRENTSV
Source OFF Leakage I
Drain OFF Leakage I
Channel ON Leakage I
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current
or I
I
INL
INH
DYNAMIC CHARACTERISTICS
t
ON
t
OFF
Charge Injection4pC typV
Off Isolation–55dB typR
Bandwidth –3 dB200MHz typR
(OFF)17pF typ
C
S
(OFF)17pF typ
C
D
CD, CS (ON)38pF typ
POWER REQUIREMENTSV
I
DD
NOTES
1
Temperature ranges are as follows: B Versions: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
)3.5Ω typV
ON
(OFF)±0.01nA typV
S
(OFF)±0.01nA typV
D
, I
D
INH
INL
(VDD = 3 V ⴞ 10%, GND = 0 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted.)
B Version
DD
V
= 0 V to VDD, IS = –10 mA;
S
56Ω maxTest Circuit 1
FLAT(ON)
)1.5Ω typV
= 0 V to VDD, IS = –10 mA
S
= +3.3 V
DD
= 3 V/1 V, VD = 1 V/3 V;
S
±0.25±0.35nA maxTest Circuit 2
= 3 V/1 V, VD = 1 V/3 V;
S
±0.25±0.35nA maxTest Circuit 2
(ON)±0.01nA typV
S
= VD = 1 V, or 3 V;
S
±0.25±0.35nA maxTest Circuit 3
2.0V min
0.4V max
0.005µA typV
IN
= V
±0.1µA max
2
14ns typR
20ns maxV
8ns typR
13ns maxV
= 300 Ω, C
L
= 2 V, Test Circuit 4
S
= 300 Ω, C
L
= 2 V, Test Circuit 4
S
= 1.5 V, R
S
Test Circuit 5
= 50 Ω, C
L
–75dB typR
= 50 Ω, C
L
Test Circuit 6
= 50 Ω, C
L
Test Circuit 7
= +3.3 V
DD
Digital Inputs = 0 V or 3 V
0.001µA typ
1.0µA max
or V
INL
INH
= 35 pF
L
= 35 pF
L
= 0 Ω, C
S
= 5 pF, f = 10 MHz
L
= 5 pF, f = 1 MHz;
L
= 5 pF;
L
= 1 nF;
L
–3–REV. A
ADG701/ADG702
ABSOLUTE MAXIMUM RATINGS
(T
= +25°C unless otherwise noted)
A
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog, Digital Inputs
2
. . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
1
or 30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
ADG701BRT–40°C to +85°CS3BSOT-23 (Plastic Surface Mount)RT-6
ADG702BRT–40°C to +85°CS4BSOT-23 (Plastic Surface Mount)RT-6
ADG701BRM–40°C to +85°CS3BµSOIC (Small Outline)RM-8
ADG702BRM–40°C to +85°CS4BµSOIC (Small Outline)RM-8
*Brand = Due to package size limitations, these three characters represent the part number.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG701/ADG702 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–REV. A
ADG701/ADG702
PIN CONFIGURATIONS
8-Lead SOIC
(RM-8)
1
D
ADG701/
NC
2
ADG702
NC
3
TOP VIEW
(Not to Scale)
4
DD
NC = NO CONNECT
8
S
GND
7
IN
6
NCV
5
6-Lead Plastic Surface Mount (SOT-23)
(RT-6)
1
D
ADG701/
2
S
ADG702
TOP VIEW
3
GND
(Not to Scale)
NC = NO CONNECT
6
V
DD
NC
5
4
IN
TERMINOLOGY
V
DD
Most Positive Power Supply Potential.
GNDGround (0 V) Reference.
SSource Terminal. May be an input or output.
DDrain Terminal. May be an input or output.
INLogic Control Input.
R
ON
R
FLAT(ON)
Ohmic Resistance Between D and S.
Flatness is defined as the difference between
the maximum and minimum value of on
resistance as measured over the specified
analog signal range.
I
(OFF)Source Leakage Current with the Switch “OFF.”
S
I
(OFF)Drain Leakage Current with the Switch “OFF.”
D
I
, IS (ON)Channel Leakage Current with the Switch “ON.”
D
V
)Analog Voltage on Terminals D, S.
D (VS
C
(OFF)“OFF” Switch Source Capacitance.
S
C
(OFF)“OFF” Switch Drain Capacitance.
D
C
, CS (ON)“ON” Switch Capacitance.
D
t
ON
Delay between applying the digital control
input and the output switching on. See Test
Circuit 4.
t
OFF
Delay between applying the digital control
input and the output switching off.
Off IsolationA measure of Unwanted Signal Coupling
Through an “OFF” Switch.
ChargeA measure of the glitch impulse transferred
Injectionfrom the digital input to the analog output
during switching.
BandwidthThe frequency at which the output is attenu-
ated by –3 dBs.
On ResponseThe frequency response of the “ON” switch.
On LossThe voltage drop across the “ON” switch seen
on the On Response vs. Frequency plot as how
many dBs the signal is away from 0 dB at very
low frequencies.
–5–REV. A
ADG701/ADG702
VDD = +3V
FREQUENCY – Hz
0
10M10k
ON RESPONSE – dB
–4
–2
100k1M100M
–6
–Typical Performance Characteristics
3.5
VDD = 2.7V
3.0
2.5
2.0
– V
ON
R
1.5
1.0
0.5
0
05.00.5
VDD = 3.0V
VDD = 5.0V
1.0 1.52.0 2.5 3.0 3.5 4.0 4.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
TA = 25 C
VDD = 4.5V
Figure 1. On Resistance as a Function of VD (VS) Single
Supplies
3.5
3.0
2.5
2.0
– V
ON
R
1.5
1.0
0.5
0
+858C
+258C
–408C
00.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
1.01.52.02.53.0
VDD = +3V
10m
VDD = +5V
1m
100m
10m
– A
1m
SUPPLY
I
100n
10n
1n
1001k100k1M
1010M10k
FREQUENCY – Hz
Figure 4. Supply Current vs. Input Switching Frequency
–10
VDD = +5V, +3V
–20
–30
–40
–50
–60
–70
OFF ISOLATION – dB
–80
–90
–100
–110
100k1M100M
FREQUENCY – Hz
10M10k
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures V
Figure 3. On Resistance as a Function of VD (VS) for
Different Temperatures V
– V
R
ON
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 3 V
DD
+858C
+258C
–408C
05.00.5
1.0 1.52.0 2.5 3.0 3.5 4.0 4.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
= 5 V
DD
Figure 5. Off Isolation vs. Frequency
VDD = +5V
Figure 6. On Response vs. Frequency
–6–REV. A
Test Circuits
SD
ADG701/ADG702
I
DS
V1
IS (OFF)ID (OFF)
SD
AA
SD
ID (ON)
A
V
S
RON = V1/I
DS
Test Circuit 1. On Resistance
V
S
V
S
IN
R
S
V
S
Test Circuit 2. Off Leakage
V
DD
0.1mF
V
DD
SD
GND
Test Circuit 4. Switching Times
V
DD
V
DD
SD
IN
GND
R
L
300V
C
1nF
V
D
V
S
V
D
Test Circuit 3. On Leakage
ADG701
V
IN
V
OUT
C
L
35pF
V
OUT
L
V
IN
ADG702
V
OUT
V
ADG701
IN
V
IN
ADG702
V
OUT
50%50%
50%50%
90%90%
t
ON
ON
Q
= CL 3DV
INJ
OUT
DV
t
OFF
OUT
OFF
Test Circuit 5. Charge Injection
V
DD
0.1mF
V
DD
V
R
50V
OUT
L
IN
V
V
S
IN
Test Circuit 7. Bandwidth
SD
IN
V
V
S
IN
GND
Test Circuit 6. Off Isolation
V
DD
0.1mF
V
DD
SD
GND
R
50V
V
OUT
L
–7–REV. A
ADG701/ADG702
S
V
IN
D
C
DS
C
D
C
LOAD
R
LOAD
V
OUT
0.122 (3.10)
0.106 (2.70)
PIN 1
0.118 (3.00)
0.098 (2.50)
0.075 (1.90)
BSC
0.037 (0.95) BSC
1
3
4 5 6
2
0.071 (1.80)
0.059 (1.50)
0.009 (0.23)
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
108
08
0.020 (0.50)
0.010 (0.25)
0.006 (0.15)
0.000 (0.00)
0.051 (1.30)
0.035 (0.90)
SEATING
PLANE
0.057 (1.45)
0.035 (0.90)
APPLICATIONS INFORMATION
The ADG701/ADG702 belongs to Analog Devices’ new family of CMOS switches. This series of general purpose switches
have improved switching times, lower on resistance, higher
bandwidth, low power consumption and low leakage currents.
ADG701/ADG702 Supply Voltages
Functionality of the ADG701/ADG702 extends from +1.8 V to
+5.5 V single supply, which makes it ideal for battery powered
instruments, where important design parameters are power
efficiency and performance.
It is important to note that the supply voltage effects the input
signal range, the on resistance and the switching times of the
part. By taking a look at the typical performance characteristics
and the specifications, the effects of the power supplies can be
clearly seen.
For V
= +1.8 V operation, R
DD
is typically 40 Ω over the
ON
temperature range.
On Response vs. Frequency
Figure 7 illustrates the parasitic components that affect the ac
performance of CMOS switches (the switch is shown surrounded
by a box). Additional external capacitances will further degrade
some performance. These capacitances affect feedthrough,
crosstalk and system bandwidth.
C
DS
S
R
ON
C
V
IN
D
C
D
LOAD
R
LOAD
V
OUT
Figure 7. Switch Represented by Equivalent Parasitic
Components
The transfer function that describes the equivalent diagram of
the switch (Figure 7) is of the form (A)s shown below.
A(s) = R
T
s(RONC
s(R
ONCTRT
DS
) +1
) +1
where:
= C
C
T
RT = R
LOAD
LOAD
+ CD + C
/(R
LOAD
+ RON)
DS
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
The signal transfer characteristic is dependent on the switch
channel capacitance, CDS. This capacitance creates a frequency
zero in the numerator of the transfer function A(s). Because the
switch on resistance is small, this zero usually occurs at high
frequencies. The bandwidth is a function of the switch output
capacitance combined with C
and the load capacitance. The
DS
frequency pole corresponding to these capacitances appears in
the denominator of A(s).
The dominant effect of the output capacitance, C
, causes the
D
pole breakpoint frequency to occur first. Therefore, in order to
maximize bandwidth a switch must have a low input and output
capacitance and low on resistance. The On Response vs. Frequency plot for the ADG701/ADG702 can be seen in Figure 6.
Off Isolation
Off isolation is a measure of the input signal coupled through an
off switch to the switch output. The capacitance, C
, couples
DS
the input signal to the output load, when the switch is off, as
shown in Figure 8.
Figure 8. Off Isolation Is Affected by External Load Resistance and Capacitance
The larger the value of CDS, larger values of feedthrough will be
produced. The typical performance characteristic graph of Figure 5 illustrates the drop in off-isolation as a function of frequency. From dc to roughly 1 MHz, the switch shows better
than –75 dB isolation. Up to frequencies of 10 MHz, the off
isolation remains better than –55 dB. As the frequency increases,
more and more of the input signal is coupled through to the
output. Off-isolation can be maximized by choosing a switch
with the smallest C
as possible. The values of load resistance
DS
and capacitance affect off isolation also, as they contribute to
the coefficients of the poles and zeros in the transfer function of
the switch when open.
A(s) =
s(R
s(R
LOADCDS
LOAD
)( C
T
)
) +1
6-Lead Plastic Surface Mount (SOT-23)
(RT-6)
C3292a–0–8/98
0.122 (3.10)
0.114 (2.90)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
85
1
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.018 (0.46)
0.008 (0.20)
0.199 (5.05)
0.187 (4.75)
4
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
0.120 (3.05)
0.112 (2.84)
33°
27°
PRINTED IN U.S.A.
0.028 (0.71)
0.016 (0.41)
–8–REV. A
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