ANALOG DEVICES ADG621 Service Manual

CMOS ±5 V/+5 V,

R

R

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FEATURES

5.5 Ω (maximum) on resistance

0.9 Ω (maximum) on resistance flatness

2.7 V to 5.5 V single supply
±2.7 V to ±5.5 V dual supply
Rail-to-rail operation
10-lead MSOP package
Typical power consumption (<0.01 μW)
TTL-/CMOS-compatible inputs

APPLICATIONS

Automatic test equipment
Power routing
Communication systems
Data acquisition systems
Sample-and-hold systems
Avio nics
Relay replacements
Battery-powered systems

GENERAL DESCRIPTION

The ADG621/ADG622/ADG623 are monolithic, CMOS,
single-pole, single-throw (SPST) switches. Each switch of the
ADG621/ADG622/ADG623 conducts equally well in both
directions when on.

The ADG621/ADG622/ADG623 contain two independent
switches. The ADG621 and ADG622 differ only in that both
switches are normally open and normally closed. In the ADG623,
Switch 1 is normally open, and Switch 2 is normally closed. The
ADG623 exhibits break-before-make switching action.

The ADG621/ADG622/ADG623 offer low on resistance of
4 Ω, which is matched to within 0.25 Ω between channels.
These switches also provide low power dissipation yet give
high switching speeds. The ADG621/ADG622/ADG623 are
available in a 10-lead MSOP package.

4 Ω Dual SPST Switches

ADG621/ADG622/ADG623

FUNCTIONAL BLOCK DIAGRAMS

ADG621

S1
D1

IN2

NOTES

1. SWITCHES SHOWN FO

Figure 1.

ADG622

S1
D1

IN2

NOTES

1. SWITCHES SHOWN FOR A LOGIC 0 INPUT

Figure 2.

ADG623

S1
D1

IN2

NOTES

1. SWITCHES SHOWN FO

Figure 3.

PRODUCT HIGHLIGHTS

1. Low on resistance, R

2. Dual ±2.7 V to ±5.5 V or single +2.7 V to +5.5 V.

3. Low power dissipation; CMOS construction ensures low

power dissipation.

4. Tiny 10-lead MSOP package.

(4 Ω typical).

ON

IN1

D2
S2

A LOGIC 0 INPUT

IN1

D2
S2

IN1

D2
S2

A LOGIC 0 INPUT

02616-001

02616-002

02616-003

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2001–2007 Analog Devices, Inc. All rights reserved.

ADG621/ADG622/ADG623

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Dual Supply................................................................................... 3

Single Supply................................................................................. 4

REVISION HISTORY

6/07—Rev. 0 to Rev. A

Change to On Resistance Flatness, R

Specification (Table 1)...................................................................... 3

Change to On Resistance Flatness, R

Specification (Table 2)...................................................................... 4

Added Table 6.................................................................................... 6

Changes to Terminology Section.................................................... 7

Changes to Figure 13........................................................................ 9

Updated Outline Dimensions....................................................... 12

Changes to Ordering Guide.......................................................... 12

11/01—Revision 0: Initial Version

FLAT(ON)

FLAT(ON)

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions..............................6

Terminology.......................................................................................7

Typical Performance Characteristics..............................................8

Test Circuits..................................................................................... 10

Outline Dimensions....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. A | Page 2 of 12

ADG621/ADG622/ADG623

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SPECIFICATIONS

DUAL SUPPLY1

VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VSS to VDD V VDD = +4.5 V, VSS = −4.5 V
On Resistance, RON 4 Ω typ

5.5 7 Ω max
On Resistance Match Between Channels, ∆RON 0.25 Ω typ VS = ±4.5 V, IS = −10 mA

0.35 0.4 Ω max
On Resistance Flatness, R

0.9 0.9 Ω typ VS = ±3.3 V, IS = −10 mA

FLAT(ON)

1.5 Ω max

LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V

Source Off Leakage, IS (Off) ±0.01 nA typ

±0.25 ±1 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ

±0.25 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.01 nA typ
±0.25 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

2.4 V min

INH

0.8 V max

INL

or I

0.005 μA typ VIN = V

INL

INH

±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS2

tON 75 ns typ
120 155 ns max
t

45 ns typ

OFF

70 85 ns max
Break-Before-Make Time Delay, t

(ADG623 Only) 30 ns typ RL = 300 Ω, CL = 35 pF; V

BBM

10 ns min
Charge Injection 110 pC typ
Off Isolation −65 dB typ
Channel-to-Channel Crosstalk −90 dB typ
Bandwidth −3 dB 230 MHz typ
CS (Off) 20 pF typ f = 1 MHz
CD (Off) 20 pF typ f = 1 MHz
CD, CS (On) 70 pF typ f = 1 MHz

POWER REQUIREMENTS VDD = 5.5 V, VSS = –5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or 5.5 V

1.0 μA max
ISS 0.001 μA typ Digital inputs = 0 V or 5.5 V

1.0 μA max

1

Temperature range is as follows: B version, –40°C to +85°C.

2

Guaranteed by design; not subject to production test.

V

= ±4.5 V, IS = −10 mA, see Figure 16

S

V

= ±4.5 V, VD = m 4.5 V, see Figure 17

S

V

= ±4.5 V, VD = m 4.5 V, see Figure 17

S

V

= VD = ±4.5 V, see Figure 18

S

or V

INL

R

= 300 Ω, CL = 35 pF; VS = 3.3 V, see Figure 19

L

R

= 300 Ω, CL = 35 pF; VS = 3.3 V, see Figure 19

L

See

Figure 20

V

= 0 V, RS = 0 Ω, CL = 1 nF, see Figure 21

S

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 22

L

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 23

L

R

= 50 Ω, CL = 5 pF, see Figure 24

L

INH

= VS2 = 3.3 V

S1

Rev. A | Page 3 of 12

ADG621/ADG622/ADG623

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SINGLE SUPPLY1

VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Parameter +25°C –40°C to +85°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 to VDD V VDD = 4.5 V, VSS = 0 V
On Resistance, RON 7 Ω typ
10 12.5 Ω max
On Resistance Match Between Channels, ∆RON 0.5 Ω typ VS = 0 V to 4.5 V, IS = −10 mA

0.75 1 Ω max
On Resistance Flatness, R

0.5 0.5 Ω typ VS = 1.5 V to 3.3 V, IS = −10 mA

FLAT(ON)

1.2 Ω max

LEAKAGE CURRENTS VDD = 5.5 V

Source Off Leakage IS (Off) ±0.01 nA typ
±0.25 ±1 nA max
Drain Off Leakage ID (Off) ±0.01 nA typ
±0.25 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.01 nA typ
±0.25 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

2.4 V min

INH

0.8 V max

INL

or I

0.005 μA typ VIN = V

INL

INH

±0.1 μA max

Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS2

tON 120 ns typ
210 260 ns max
t

50 ns typ

OFF

75 100 ns max
Break-Before-Make Time Delay, t

(ADG623 Only) 70 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.3 V

BBM

10 ns min
Charge Injection 6 pC typ
Off Isolation –65 dB typ
Channel-to-Channel Crosstalk –90 dB typ
Bandwidth −3 dB 230 MHz typ
CS (Off) 20 pF typ f = 1 MHz
CD (Off) 20 pF typ f = 1 MHz
CD, CS (On) 70 pF typ f = 1 MHz

POWER REQUIREMENTS VDD = 5.5 V

IDD 0.001 μA typ Digital Inputs = 0 V or 5.5 V

1.0 μA max

1

Temperature range is as follows: B Version, –40°C to +85°C.

2

Guaranteed by design; not subject to production test.

V

= 0 V to 4.5 V, IS = –10 mA, see Figure 16

S

V

= 1 V/4.5 V, VD = 4.5 V/1 V, see Figure 17

S

V

= 1 V/4.5 V, VD = 4.5 V/1 V, see Figure 17

S

V

= VD = 1 V/4.5 V, see Figure 18

S

or V

INL

R

= 300 Ω, CL = 35 pF; VS = 3.3 V, see Figure 19

L

R

= 300 Ω, CL = 35 pF; VS = 3.3 V, see Figure 19

L

See

Figure 20

V

= 0 V; RS = 0 Ω, CL = 1 nF, see Figure 21

S

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 22

L

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 23

L

R

= 50 Ω, CL = 5 pF, see Figure 24

L

INH

Rev. A | Page 4 of 12