FEATURES
1 pC Charge Injection
ⴞ2.7 V to ⴞ5.5 V Dual Supply
+2.7 V to +5.5 V Single Supply
Automotive Temperature Range –40ⴗC to +125ⴗC
100 pA Max @ 25ⴗC Leakage Currents
85 ⍀ On-Resistance
Rail-to-Rail Switching Operation
Fast Switching Times
16-Lead TSSOP Packages
Typical Power Consumption (<0.1 W)
TTL/CMOS-Compatible Inputs
APPLICATIONS
Automatic Test Equipment
Data Acquisition Systems
Battery-Powered Systems
Communication Systems
Sample and Hold Systems
Audio Signal Routing
Relay Replacement
Avionics
ADG611/ADG612/ADG613
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The ADG611, ADG612, and ADG613 are monolithic CMOS
devices containing four independently selectable switches. These
switches offer ultralow charge injection of 1 pC over full input
signal range and typical leakage currents of 10 pA at 25°C.
They are fully specified for ±5 V, +5 V, and +3 V supplies.
They contain four independent single-pole/single-throw (SPST)
switches. The ADG611 and ADG612 differ only in that the
digital control logic is inverted. The ADG611 switches are turned
on with a logic low on the appropriate control input, while a logic
high is required to turn on the switches of the ADG612. The
ADG613 contains two switches whose digital control logic is
similar to the ADG611, while the logic is inverted on the other
two switches.
Each switch conducts equally well in both directions when ON
and has an input signal range that extends to the supplies. The
ADG613 exhibits break-before-make switching action. The
ADG611/ADG612/ADG613 are available in small 16-lead
TSSOP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. Ultralow Charge Injection (1 pC typically)
2. Dual ± 2.7 V to ± 5.5 V or Single +2.7 V to +5.5 V
Operation.
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
ADG611YRU–40°C to +125°CThin Shrink Small Outline Package (TSSOP)RU-16
ADG612YRU–40°C to +125°CThin Shrink Small Outline Package (TSSOP)RU-16
ADG613YRU–40°C to +125°CThin Shrink Small Outline Package (TSSOP)RU-16
Table I. ADG611/ADG612 Truth Table
PIN CONFIGURATIONS
ADG611 InADG612 InSwitch Condition
01ON
10OFF
Table II. ADG613 Truth Table
LogicSwitch 1, 4Switch 2, 3
0OFFON
1ONOFF
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG611/ADG612/ADG613 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
ADG611/ADG612/ADG613
TERMINOLOGY
V
DD
V
SS
I
DD
I
SS
GNDGround (0 V) Reference
SSource Terminal. May be an input or output
DDrain Terminal. May be an input or output
INLogic Control Input
V
)Analog Voltage on Terminals D, S
D (VS
R
ON
∆R
ON
R
FLAT(ON)
I
(OFF)Source Leakage Current with the Switch “OFF”
S
I
(OFF)Drain Leakage Current with the Switch “OFF”
D
I
, IS (ON)Channel Leakage Current with the Switch “ON”
D
V
INL
V
INH
I
INL(IINH
C
C
C
C
t
ON
t
OFF
)Input Current of the Digital Input.
(OFF)“OFF” Switch Source Capacitance. Measured with reference to ground.
S
(OFF)“OFF” Switch Drain Capacitance. Measured with reference to ground.
D
, CS(ON)“ON” Switch Capacitance. Measured with reference to ground.
D
IN
ChargeA measure of the glitch impulse transferred from the digital input to the analog output during switching.
Injection
Off IsolationA measure of unwanted signal coupling through an “OFF” switch.
CrosstalkA measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
On ResponseFrequency Response of the “ON” Switch
InsertionLoss Due to the ON Resistance of the Switch
Loss
Most Positive Power Supply Potential
Most Negative Power Supply Potential
Positive Supply Current
Negative Supply Current
Ohmic Resistance between D and S
On Resistance match between any two channels, i.e., R
ONMAX–RONMIN
.
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured
over the specified analog signal range.
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Digital Input Capacitance
Delay between applying the digital control input and the output switching on. See Test Circuit 4.
Delay between applying the digital control input and the output switching off.
TPC 4. On Resistance vs. VD(VS)
for Different Temperatures,
Single Supply
600
TA = 25ⴗC
= 0V
V
SS
500
400
300
200
ON RESISTANCE – ⍀
100
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD = 2.7V
VDD = 4.5V
, VS – V
V
D
V
= 3V
DD
V
= 3.3V
DD
= 5V
V
DD
TPC 2. On Resistance vs. VD(VS),
Single Supply
2
1
0
–1
–2
–3
CURRENT – nA
–4
–5
VDD = +5V
= –5V
V
SS
–6
20406080100
0
TEMPERATURE – ⴗC
IS (OFF)
(OFF)
I
D
IS, ID(ON)
TPC 5. Leakage Currents vs.
Temperature, Dual Supply
120
250
200
150
100
ON RESISTANCE – ⍀
50
0
–5
–4 –3 –2 –1012345
+25ⴗC
V
D
+85ⴗC
, VS – V
–40ⴗC
+125ⴗC
VDD = +5V
= –5V
V
SS
TPC 3. On Resistance vs. VD(VS) for
Different Temperatures, Dual Supply
CURRENT – nA
2
1
0
–1
–2
–3
–4
VDD = 5V
–5
= 0V
V
SS
–6
0
20406080100
TEMPERATURE – ⴗC
IS (OFF)
I
(OFF)
D
IS, ID(ON)
120
TPC 6. Leakage Currents vs.
Temperature, Single Supply
2.0
TA = 25ⴗC
1.5
1.0
0.5
0
Qinj – pC
–0.5
–1.0
–1.5
–2.0
–5 –4 –3 –2 –1012345
VDD = +3V
= 0V
V
SS
VDD = +5V
V
SS
= 0V
V
V
V
DD
SS
S
= +5V
= –5V
– V
TPC 7. Charge Injection vs.
Source Voltage
REV. 0
120
100
80
60
TIME – ns
40
20
0
TPC 8. tON/t
Temperature
t
ON, VDD
t
ON, VDD
V
t
OFF, VDD
t
OFF, VDD
V
20 40 60 80 100
0
TEMPERATURE – ⴗC
Times vs.
OFF
–7–
V
SS
V
SS
= +5V
SS
= +5V
= –5V
= +5V
SS
= +5V
= –5V
= 0V
= 0V
0
–2
–4
–6
–8
–10
–12
ATTENUATION – dB
–14
–16
120–40 –20
–18
VDD = –5V
= +5V
V
SS
VDD = 5V
= 0V
V
SS
0.3
110100
FREQUENCY – MHz
TA = 25ⴗC
1000
TPC 9. On Response vs. Frequency
ADG611/ADG612/ADG613
0
–10
–20
–30
–40
–50
–60
ATTENUATION – dB
–70
–80
–90
110100
0.3
FREQUENCY – MHz
VDD = –5V
= +5V
V
SS
= +25ⴗC
T
A
1k
TPC 10. Off Isolation vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
ATTENUATION – dB
–80
–90
–100
110100
0.3
FREQUENCY – MHz
VDD = +5V
= –5V
V
SS
= 25ⴗC
T
A
1k
APPLICATIONS
Figure 1 illustrates a photodetector circuit with programmable
gain. With the resistor values shown in the circuits, and using
different combinations of switches, gains in the range of 2 to 16
can be achieved.
C1
R1
D1
(LSB) IN1
IN2
IN3
(MSB) IN4
2.5V
33k⍀
5V
S1
S2
S3
S4
GND
R4
240k⍀R5240k⍀
D1
R6
120k⍀R7120k⍀
D2
D3
D4
GAIN RANGE 2 TO 16
R8
120k⍀
R9
120k⍀
R9
120k⍀
5V
V
OUT
R2
510k⍀
R3
510k⍀
2.5V
Figure 1. Photodetector Circuit with Programmable Gain
TPC 11. Crosstalk vs. Frequency
–8–
REV. 0
Test Circuits
SD
ADG611/ADG612/ADG613
I
DS
V1
IS (OFF)ID (OFF)
SD
AA
SD
NC
I
D (ON)
A
V
S
RON = V1/I
DS
Test Circuit 1. On Resistance
0.1F
V
S
0.1F
IN1,
IN2
S1D1
S2
V
S1
V
S2
V
IN
VDDV
VDDV
ADG613
GND
IN
SS
SS
D2
V
S
Test Circuit 2. Off Leakage
V
V
DD
SS
0.1F
V
V
DD
SS
SD
GND
Test Circuit 4. Switching Times
0.1F
C
L2
35pF
V
R
L2
300⍀
R
L
300⍀
OUT2
V
C
L
35pF
R
L1
300⍀
OUT
C
L
35pF
V
OUT
V
IN
V
IN
V
OUT1
V
D
ADG611
ADG612
V
OUT1
V
OUT2
50%50%
50%50%
90%90%
t
ON
V
IN
0V
0V
90%
0V
NC = NO CONNECT
Test Circuit 3. On Leakage
t
OFF
50%50%
t
90%
90%
D
90%
t
D
V
D
REV. 0
Test Circuit 5. Break-Before-Make Time Delay
V
V
V
R
S
V
S
SD
IN
SS
DD
V
SS
DD
C
L
1nF
GND
V
IN
ADG611
V
OUT
V
OUT
V
IN
ADG612
Q
INJ
ON
= CL ⴛ⌬V
OUT
⌬V
OFF
OUT
Test Circuit 6. Charge Injection
–9–
ADG611/ADG612/ADG613
V
IN
IN
0.1F
V
DD
V
SS
0.1F
V
DD
SS
S
50⍀
V
D
GND
Test Circuit 7. Off Isolation
NETWORK
ANALYZER
50⍀
V
V
OUT
R
L
50⍀
OFF ISOLATION = 20 LOG
V
DD
0.1F
V
DD
IN
V
IN
S
S
GND
V
V
DD
SS
0.1F
V
DD
SD
0.1F
V
SS
50⍀
VIN1
V
S
NC
S
GND
V
OUT
V
S
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG |V
VIN2
D
R
50⍀
S/VOUT
V
OUT
L
|
Test Circuit 8. Channel-to-Channel Crosstalk
V
SS
0.1F
V
SS
D
NETWORK
ANALYZER
50
⍀
V
V
OUT
R
L
50
⍀
S
V
INSERTION LOSS = 20 LOG
OUT
V
OUT
Test Circuit 9. Bandwidth
WITH SWITCH
WITHOUT SWITCH
–10–
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
ADG611/ADG612/ADG613
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
16
0.0256 (0.65)
BSC
9
0.177 (4.50)
0.169 (4.30)
81
0.0433 (1.10)
MAX
0.0118 (0.30)
0.0075 (0.19)
0.256 (6.50)
0.246 (6.25)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
REV. 0
–11–
C02753–0–1/02(0)
–12–
PRINTED IN U.S.A.
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