ANALOG DEVICES ADG 612 YRUZ Datasheet

1 pC Charge Injection, 100 pA Leakage,

3

CMOS, ±5 V/+5 V/+3 V, Quad SPST Switches

FEATURES

1 pC charge injection ±2.7 V to ±5.5 V dual-supply operation +2.7 V to +5.5 V single-supply operation Automotive temperature range: −40°C to +125°C 100 pA maximum at 25°C leakage currents 85 Ω on resistance Rail-to-rail switching operation Fast switching times 16-lead TSSOP and SOIC packages Typical power consumption: <0.1 μW TTL-/CMOS-compatible inputs

APPLICATIONS

Automatic test equipment Data acquisition systems Battery-powered systems Communications systems Sample-and-hold systems Audio signal routing Relay replacement Avio nics

ADG611/ADG612/ADG613

FUNCTIONAL BLOCK DIAGRAM

ADG611

IN1

IN2

IN

IN4

NOTES

1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.

S1

D1

S2

D2

S3

D3

S4

D4

ADG612

IN1

IN2

IN3

IN4

Figure 1.

S1

D1

S2

D2

S3

D3

S4

D4

ADG613

IN1

IN2

IN3

IN4

S1

D1

S2

D2

S3

D3

S4

D4

02753-001

GENERAL DESCRIPTION

The ADG611/ADG612/ADG613 are monolithic CMOS devices containing four independently selectable switches. These switches offer ultralow charge injection of 1 pC over the full input signal range and typical leakage currents of 10 pA at 25°C.

The devices are fully specified for ±5 V, +5 V, and +3 V supplies. Each contains four independent single-pole, single-throw (SPST) switches. The ADG611 and ADG612 differ only in that the digital control logic is inverted. The ADG611 switches are turned on with a logic low on the appropriate control input, whereas a logic high is required to turn on the switches of the ADG612. The ADG613 contains two switches with digital control logic similar to that of the ADG611 and two switches in which the logic is inverted.

Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG613 exhibits break-before-make switching action. The ADG611/ADG612/ADG613 are available in a small, 16-lead TSSOP package, and the ADG611 is also available in a 16-lead SOIC package.

PRODUCT HIGHLIGHTS

1. Ultralow charge injection (1 pC typically).

2. Dual ±2.7 V to ±5.5 V or single +2.7 V to +5.5 V operation.

3. Automotive temperature range: −40°C to +125°C.

4. Small, 16-lead TSSOP and SOIC packages.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADG611/ADG612/ADG613

REVISION HISTORY

11/09—Rev. 0 to Rev. A

Changes to Analog Signal Range Parameter

and to On Resistance, R Change to Digital Input Capacitance, C

Changes to Table 4 and to Absolute Maximum Ratings Section ...... 6

Added Table 5; Renumbered Sequentially .................................... 7

Updated Outline Dimensions ....................................................... 14

Changes to Ordering Guide .......................................................... 14

1/02—Revision 0: Initial Version

Parameter, Table 1 .......................... 3

ON

Parameter, Table 2 .... 4

IN

Absolute Maximum Ratings ............................................................6

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Ter minology .................................................................................... 10

Test Circuits ..................................................................................... 11

Applications Information .............................................................. 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADG611/ADG612/ADG613

SPECIFICATIONS

DUAL-SUPPLY OPERATION

VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Par ameter +25 °C −40°C to +85°C −40°C to +125°C1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VSS to VDD V On Resistance, RON 85 Ω typ VS = ±3 V, IS = −1 mA; see Figure 14 115 140 160 Ω max VS = ±3 V, IS = −1 mA; see Figure 14 On-Resistance Match

Between Channels, ΔR

ON

4 5.5 6.5 Ω max VS = ±3 V, IS = −1 mA On-Resistance Flatness, R

FLAT(ON)

40 55 60 Ω max VS = ±3 V, IS = −1 mA

LEAKAGE CURRENTS VDD = +5.5 V, V

Source Off Leakage, I

±0.01 nA typ

S(OFF)

±0.1 ±0.25 ±2 nA max Drain Off Leakage, I

±0.01 nA typ

D(OFF)

±0.1 ±0.25 ±2 nA max Channel On Leakage, I

D(ON)

, I ±0.1 ± 0.25 ± 6 nA max VD = VS = ±4.5 V; see Figure 16 DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

2.4 V min

INH

0.8 V max

INL

or I

0.005 μA typ VIN = V

INL

INH

±0.1 μA max VIN = V

Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS

2

tON 45 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 65 75 90 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 t

25 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17

OFF

40 45 50 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 Break-Before-Make Time Delay, t 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 Charge Injection −0.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −65 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21

−3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 C

5 pF typ f = 1 MHz

S(OFF)

C

5 pF typ f = 1 MHz

D(OFF)

C

, C

D(ON)

5 pF typ f = 1 MHz

S(ON)

POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or 5.5 V

1.0 μA max Digital inputs = 0 V or 5.5 V I

0.001 μA typ Digital inputs = 0 V or 5.5 V

SS

1.0 μA max Digital inputs = 0 V or 5.5 V

1

The temperature range for the Y version is −40°C to +125°C.

2

Guaranteed by design; not subject to production test.

2 Ω typ V

= ±3 V, IS = −1 mA

S

25 Ω typ VS = ±3 V, IS = −1 mA

= −5.5 V

SS

V

= ±4.5 V, VS = +4.5 V; see Figure 15

D

V

= ±4.5 V, VS = +4.5 V; see Figure 15

D

V

= ±4.5 V, VS = + 4.5 V; see Figure 15

D

V

= ±4.5 V, VS = + 4.5 V; see Figure 15

D

±0.01 nA typ VD = VS = ±4.5 V; see Figure 16

S(ON)

or V or V

INH

INL

15 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18

BBM

Rev. A | Page 3 of 16

ADG611/ADG612/ADG613

SINGLE-SUPPLY OPERATION

VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Par ameter +25 °C −40°C to +85°C −40°C to +125°C1Unit Test Conditions/Comments

ANALOG SWITCH Analog Signal Range 0 to VDD V On Resistance, RON 210 Ω typ VS = 3.5 V, IS = −1 mA; see Figure 14 290 350 380 Ω max VS = 3.5 V, IS = −1 mA; see Figure 14 On-Resistance Match

Between Channels, ΔR

ON

10 12 13 Ω max VS = 3.5 V, IS = −1 mA

LEAKAGE CURRENTS VDD = 5.5 V

Source Off Leakage, I

±0.01 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15

S(OFF)

±0.1 ±0.25 ±2 nA max VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15 Drain Off Leakage, I

±0.01 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15

D(OFF)

±0.1 ±0.25 ±2 nA max VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 15

Channel On Leakage, I

D(ON)

, I

S(ON)

±0.1 ±0.25 ±6 nA max VS = VD = 1 V or 4.5 V; see Figure 16

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

2.4 V min

INH

0.8 V max

INL

or I

0.005 μA typ VIN = V

INL

INH

±0.1 μA max VIN = V Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS

2

tON 70 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 100 130 150 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 t

25 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17

OFF

40 45 50 ns max RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 Break-Before-Make Time Delay, t 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 Charge Injection 1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −62 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21

−3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 C

5 pF typ f = 1 MHz

S(OFF)

C

5 pF typ f = 1 MHz

D(OFF)

C

, C

D(ON)

5 pF typ f = 1 MHz

S(ON)

POWER REQUIREMENTS VDD = 5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or 5.5 V

1.0 μA max Digital inputs = 0 V or 5.5 V

1

The temperature range for the Y version is −40°C to +125°C.

2

Guaranteed by design; not subject to production test.

3 Ω typ V

= 3.5 V, IS = −1 mA

S

±0.01 nA typ VS = VD = 1 V or 4.5 V; see Figure 16

or V or V

INH

INL

25 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18

BBM

Rev. A | Page 4 of 16

ADG611/ADG612/ADG613

VDD = 3 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Par ameter +25 °C −40°C to +85°C −40°C to +125°C1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 to VDD V On Resistance, RON 380 420 460 Ω typ VS = 1.5 V, IS = −1 mA; see Figure 14

LEAKAGE CURRENTS VDD = 3.3 V

Source Off Leakage, I ±0.1 ±0.25 ± 2 nA max VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15 Drain Off Leakage, I ±0.1 ±0.25 ±2 nA max VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15 Channel On Leakage, I ±0.1 ±0.25 ±6 nA max VS = VD = 1 V or 3 V; see Figure 16

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

±0.1 μA max VIN = V

Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS

tON 130 ns typ RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 185 230 260 ns max RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 t

40 ns typ RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17

OFF

55 60 65 ns max RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 Break-Before-Make Time Delay, t 10 ns min RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 Charge Injection 1.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 Off Isolation −62 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21

−3 dB Bandwidth 680 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 22 C

5 pF typ f = 1 MHz

S(OFF)

C

5 pF typ f = 1 MHz

D(OFF)

C

, C

D(ON)

5 pF typ f = 1 MHz

S(ON)

POWER REQUIREMENTS V

IDD 0.001 μA typ Digital inputs = 0 V or 3.3 V

1.0 μA max Digital inputs = 0 V or 3.3 V

1

The temperature range for the Y version is −40°C to +125°C.

2

Guaranteed by design; not subject to production test.

±0.01 nA typ VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15

S(OFF)

±0.01 nA typ VS = 1 V/3 V, VD = 3 V/1 V; see Figure 15

D(OFF)

, I

±0.01 nA typ VS = VD = 1 V or 3 V; see Figure 16

S(ON)

2.0 V min

0.8 V max

0.005 μA typ VIN = V

2

50 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18

BBM

= 3.3 V

DD

INL

or V or V

INH

or I

D(ON)

INH

INL

INH

Rev. A | Page 5 of 16

ADG611/ADG612/ADG613

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Table 4.

Parameter Rating

VDD to VSS 13 V VDD to GND −0.3 V to +6.5 V VSS to GND +0.3 V to −6.5 V Analog Inputs1 V Digital Inputs1

Peak Current, S or D

Continuous Current, S or D 10 mA

3 V operation 85°C to 125°C 7.5 mA

Operating Temperature Range

Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance

16-Lead TSSOP 150.4°C/W

16-Lead SOIC, 4-Layer Board 80.6°C/W Lead Soldering

Lead Temperature, Soldering

(10 sec)

IR Reflow, Peak Temperature

(<20 sec)

(Pb-Free) Soldering

Reflow, Peak Temperature 260(+0/−5)°C

Time at Peak Temperature 20 sec to 40 sec

1

Overvoltages at IN, S, or D are clamped by internal diodes. The current

should be limited to the maximum ratings given.

− 0.3 V to VDD + 0.3 V

SS

GND − 0.3 V to V 30 mA, whichever occurs first

20 mA (pulsed at 1 ms, 10% duty cycle maximum)

300°C

220°C

+ 0.3 V or

DD

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating can be applied at any one time.

ESD CAUTION

Rev. A | Page 6 of 16

ADG611/ADG612/ADG613

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

IN1

2

D1

ADG611/

3

S1

ADG612/

4

V

ADG613

SS

TOP VIEW

5

GND

(Not to Scale)

6

S4

7

D4

8

IN4

NC = NO CONNECT

16

IN2

15

D2

14

S2

13

V

DD

12

NC

11

S3

10

D3

9

IN3

2753-002

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 IN1 Switch 1 Digital Control Input. 2 D1 Drain Terminal of Switch 1. Can be an input or output. 3 S1 Source Terminal of Switch 1. Can be an input or output. 4 VSS Most Negative Power Supply Terminal. Tie this pin to GND when using the device with single-supply voltages. 5 GND Ground (0 V) Reference. 6 S4 Source Terminal of Switch 4. Can be an input or output. 7 D4 Drain Terminal of Switch 4. Can be an input or output. 8 IN4 Switch 4 Digital Control Input. 9 IN3 Switch 3 Digital Control Input. 10 D3 Drain Terminal of Switch 3. Can be an input or output. 11 S3 Source Terminal of Switch 3. Can be an input or output. 12 NC Not Internally Connected. 13 VDD Most Positive Power Supply Terminal. 14 S2 Source Terminal of Switch 2. Can be an input or output. 15 D2 Drain Terminal of Switch 2. Can be an input or output. 16 IN2 Switch 2 Digital Control Input.

Table 6. ADG611/ADG612 Truth Table

ADG611 Input ADG612 Input Switch Condition

0 1 On 1 0 Off

Table 7. ADG613 Truth Table

Logic Switch 1, Switch 4 Switch 2, Switch 3

0 Off On 1 On Off

Rev. A | Page 7 of 16

ADG611/ADG612/ADG613

TYPICAL PERFORMANCE CHARACTERISTICS

250

TA = 25°C

200

±3.3V

150

±2.7V ±3.0V

100

ON RESISTANCE ( Ω)

50

0

–5–4–3–2–1012345

VD, VS (V)

±4.5V

±5.5V

±5.0V

02753-003

Figure 3. On Resistance vs. VD (VS), Dual Supplies Figure 6. On Resistance vs. VD (VS) for Various Temperatures, Single Supply

600

VDD = 5V V

= 0V

SS

500

400

300

+125°C

200

ON RESISTANCE ( Ω)

100

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

+85°C

+25°C

VD, VS (V)

–40°C

02753-006

600

TA = 25°C V

= 0V

SS

500

400

300

200

ON RESISTANCE ( Ω)

100

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

= 2.7V

V

DD

VDD = 3.0V

VDD = 4.5V

VD, VS (V)

VDD = 3.3V

= 5.0V

V

DD

02753-004

Figure 4. On Resistance vs. VD (VS), Single Supply

250

VDD = +5V V

= –5V

SS

200

150

100

ON RESISTANCE ( Ω)

50

0

–5–4–3–2–1012345

+25°C

VD, VS (V)

+125°C

+85°C

–40°C

02753-005

Figure 5. On Resistance vs. VD (VS) for Various Temperatures, Dual Supplies

2

VDD = +5V V

= –5V

SS

1

0

–1

–2

–3

LEAKAGE CURRENT (n A)

–4

–5

–6

0 20406080100120

TEMPERATURE (°C)

I

D(OFF)

I

S(ON), ID(ON)

I

S(OFF)

Figure 7. Leakage Current vs. Temperature, Dual Supplies

2

VDD = 5V V

= 0V

SS

1

0

–1

–2

–3

LEAKAGE CURRENT (n A)

–4

–5

–6

0 20406080100120

TEMPERATURE (°C)

I

S(OFF)

I

D(OFF)

I

S(ON), ID(ON)

Figure 8. Leakage Current vs. Temperature, Single Supply

02753-007

02753-008

Rev. A | Page 8 of 16

ADG611/ADG612/ADG613

2.0 TA = 25°C

1.5

1.0

0.5

(pC)

0

INJ

Q

–0.5

–1.0

–1.5

–2.0

–5–4–3–2–1012345

V V

DD SS

VS (V)

= +3V

= 0V

= +5V

= 0V

= +5V

= –5V

Figure 9. Charge Injection vs. Source Voltage

02753-009

OFF ISOLATION (dB)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0.3 1k100101

VDD = –5V V

= +5V

SS

T

= 25°C

A

FREQUENCY (MHz)

Figure 12. Off Isolation vs. Frequency

02753-012

CROSSTALK (dB)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

VDD = +5V V

= –5V

SS

T

= 25°C

A

0.3 1k100101

FREQUENCY (MHz)

Figure 13. Crosstalk vs. Frequency

02753-013

120

100

80

60

TIME (ns)

40

20

0

–40 0–20 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 10. tON/t

t

, VDD = +5V

ON

V

= 0V

SS

t

, VDD = +5V

ON

V

= –5V

SS

t

, VDD = +5V

OFF

V

= 0V

SS

t

, VDD = +5V

OFF

V

= –5V

SS

Times vs. Temperature

OFF

02753-010

0

TA = 25°C

ATTENUATION (dB)

–2

–4

–6

–8

–10

–12

–14

–16

–18

0.3 1k100101

V

= –5V

DD

V

= +5V

SS

V

= +5V

DD

V

= 0V

SS

FREQUENCY (MHz)

02753-011

Figure 11. On Response vs. Frequency

Rev. A | Page 9 of 16

ADG611/ADG612/ADG613

TERMINOLOGY

V

VDD

Most positive power supply potential.

V

SS

Most negative power supply potential.

I

DD

Positive supply current.

I

SS

Negative supply current.

GND

Ground (0 V) reference.

S

Source terminal. Can be an input or output.

D

Drain terminal. Can be an input or output.

IN

Logic control input.

V

(VS)

D

Analog voltage on Terminal D and Terminal S.

R

ON

Ohmic resistance between Terminal D and Terminal S.

ΔR

ON

On-resistance match between any two channels, that is, R

ONMAX

R

FLAT(ON)

− R

ONMIN

.

Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range.

I

S(OFF)

Source leakage current with the switch off.

I

D(OFF)

Drain leakage current with the switch off.

I

, I

S(ON)

D(ON)

Channel leakage current with the switch on.

V

INL

Maximum input voltage for Logic 0.

INH

Minimum input voltage for Logic 1.

I

, I

INL

INH

Input current of the digital input.

C

S(OFF)

Off switch source capacitance. Measured with reference to ground.

C

D(OFF)

Off switch drain capacitance. Measured with reference to ground.

C

, C

S(ON)

D(ON)

On switch capacitance. Measured with reference to ground.

C

IN

Digital input capacitance.

t

ON

Delay between applying the digital control input and the output switching on (see Figure 17).

t

OFF

Delay between applying the digital control input and the output switching off (see Figure 17).

Charge Injection

A measure of the glitch impulse transferred from the digital input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.

On Response

Frequency response of the on switch.

Insertion Loss

Loss due to the on resistance of the switch.

Rev. A | Page 10 of 16

ADG611/ADG612/ADG613

V

VDDV

V

VDDV

TEST CIRCUITS

I

DS

V1

SD

I

S(OFF)

SD

A

I

D(OFF)

A

SD

NC

I

D(ON)

A

S

RON = V1/I

Figure 14. On Resistance

DS

02753-014

V

S

Figure 15. Off Leakage

V

D

02753-015

NC = NO CONNECT

V

D

2753-016

Figure 16. On Leakage

VDDV

GND

SS

V

OUT

V

IN

V

IN

ADG611

ADG612

SS

V

OUT

R 300Ω

C

L

35pF

t

ON

50% 50%

90% 90%

t

OFF

02753-017

Figure 17. Switching Times

0.1µF 0.1µF

SD

S

IN

0.1µF 0.1µF

V

S1

V

S2

IN1,

V

IN

IN2

SS

V

DD

SS

S1 D1

S2 D2

ADG613

GND

R

L2

300Ω

V

C

L1

35pF

OUT1

C

L2

35pF

V

OUT2

R

L1

300Ω

Figure 18. Break-Before-Make Time Delay

V

OUT1

OUT2

IN

0V

50% 50%

90%

t

BBM

t

BBM

90%

02753-018

SS

V

ADG611

OUT

V

OUT

IN

ADG612

ON OFF

Q

= CL × ΔV

INJ

OUT

ΔV

OUT

V

DDVSS

C 1nF

V

L

R

S

V

S

SD

IN

GND

02753-019

Figure 19. Charge Injection

Rev. A | Page 11 of 16

ADG611/ADG612/ADG613

V

VDDV

V

VDDV

SS

0.1µF0.1µF

SS

0.1µF0.1µF

V

DD

SS

IN

S

50Ω

D

IN

GND

Figure 20. Off Isolation

V

DD

S

V

S

NC

VIN1

S

GND

CHANNEL-TO-CHANNEL CROSSTAL K = 20 log |V

Figure 21. Channel-to-Channel Crosstalk

NETWO RK ANALYZER

50Ω

R

L

50Ω

OFF ISOLATION = 20 log

SS

0.1µF0.1µF

V

SS

D

VIN2

D

S/VOUT

V

50Ω

V

OUT

R 50Ω

NETWO RK

V

DD

SS

S

IN

S

D

IN

GND

V

OUT

V

S

02753-020

INSERTION LOSS = 20 log

ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

V

WITH SWITCH

OUT

V

WITHOUT SWITCH

OUT

02753-022

Figure 22. Bandwidth

V

OUT

L

|

02753-021

Rev. A | Page 12 of 16

ADG611/ADG612/ADG613

(

APPLICATIONS INFORMATION

Figure 23 illustrates a photodetector circuit with programmable gain. With the resistor values shown in this figure, gains in the range of 2 to 16 can be achieved by using different combinations of switches.

C1

R1

D1

(LSB) IN1

IN2

IN3

MSB) IN4

2.5V

S1 D1

S2 D2

S3 D3

S4 D4

GND

33kΩ

5V

240kΩR5240kΩ

120kΩR7120kΩ

GAIN RANGE: 2 T O 16

R4

R6

R8

120kΩ

R9

120kΩ

R9

120kΩ

5V

V

OUT

R2 510kΩ

R3 510kΩ

2.5V

02753-023

Figure 23. Photodetector Circuit with Programmable Gain

Rev. A | Page 13 of 16

ADG611/ADG612/ADG613

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

6.40 BSC

81

1.20 MAX

SEATING PLANE

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

10.00 (0.3937)

9.80 (0.3858)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

16

1

1.27 (0.0500) BSC

0.51 (0.0201)

0.31 (0.0122)

9

8

6.20 (0.2441)

5.80 (0.2283)

1.75 (0.0689)

1.35 (0.0531)

SEATING PLANE

8° 0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

45°

CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; INCH DI MENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMET ER EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AC

060606-A

Figure 25. 16-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG611YRUZ ADG611YRUZ-REEL ADG611YRUZ-REEL7 ADG611YRZ ADG612YRUZ ADG612YRUZ-REEL ADG612YRUZ-REEL7 ADG612WRUZ-REEL ADG613YRUZ ADG613YRUZ-REEL ADG613YRUZ-REEL7

1

Z = RoHS Compliant Part.

1