Datasheet ADG5412 Datasheet (ANALOG DEVICES)

High Voltage Latch-Up Proof,

3

FEATURES

Latch-up proof 8 kV human body model (HBM) ESD rating Low on resistance (<10 Ω) ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V V

to VDD analog signal range

SS

APPLICATIONS

Relay replacement Automatic test equipment Data acquisition Instrumentation Avio nics Audio and video switching Communication systems

GENERAL DESCRIPTION

The ADG5412/ADG5413 contain four independent singlepole/single-throw (SPST) switches. The ADG5412 switches turn on with Logic 1. The ADG5413 has two switches with digital control logic similar to that of the ADG5412; however, the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.

The ADG5412 and ADG5413 do not have a V inputs are compatible with 3 V logic inputs over the full operating supply range.

The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. High switching speed also makes the devices suitable for video signal switching. The ADG5413

pin. The digital

L

Quad SPST Switches

ADG5412/ADG5413

FUNCTIONAL BLOCK DIAGRAMS

S1

IN1

IN2

ADG5412

IN

IN4

SWITCHES SHOWN FO R A LOGIC 1 INPUT.

D1

S2

D2

S3

D3

S4

D4

Figure 1.

IN1

IN2

ADG5413

IN3

IN4

exhibits break-before-make switching action for use in multiplexer applications.

PRODUCT HIGHLIGHTS

1. Trench isolation guards against latch-up. A dielectric trench

separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions.

2. Low R

3. Dual-supply operation. For applications where the analog

signal is bipolar, the ADG5412/ADG5413 can be operated from dual supplies up to ±22 V.

4. Single-supply operation. For applications where the analog

signal is unipolar, the ADG5412/ADG5413 can be operated from a single rail power supply up to 40 V.

5. 3 V logic compatible digital inputs: V

6. No V

.

ON

logic power supply required.

L

INH

S1

D1

S2

D2

S3

D3

S4

D4

= 2.0 V, V

09202-001

= 0.8 V.

INL

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADG5412/ADG5413

REVISION HISTORY

6/11—Rev. 0 to Rev. A

Change to I

7/10—Revision 0: Initial Version

Parameter in Table 2................................................. 4

SS

Continuous Current per Channel, Sx or Dx..............................7

Absolute Maximum Ratings ............................................................8

ESD Caution...................................................................................8

Pin Configurations and Function Descriptions............................9

Typical Performance Characteristics........................................... 10

Test Circuits..................................................................................... 14

Terminology.................................................................................... 16

Trench Isolation .............................................................................. 17

Applications Information.............................................................. 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. A | Page 2 of 20

ADG5412/ADG5413

SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V On Resistance, RON 9.8 Ω typ

11 14 16 Ω max VDD = +13.5 V, VSS = −13.5 V On-Resistance Match Between Channels,

∆R

ON

0.35 Ω typ V

0.7 0.9 1.1 Ω max On-Resistance Flatness, R

1.2 Ω typ VS = ±10 V, IS = −10 mA

FLAT (ON)

1.6 2 2.2 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.05 nA typ

±0.25 ±0.75 ±3.5 nA max Drain Off Leakage, ID (Off) ±0.05 nA typ

±0.25 ±0.75 ±3.5 nA max

Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 23 ±0.4 ±2 ±12 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 2.5 pF typ DYNAMIC CHARACTERISTICS1

tON 170 ns typ RL = 300 Ω, CL = 35 pF

202 236 262 ns max VS = 10 V; see Figure 31

t

120 ns typ RL = 300 Ω, CL = 35 pF

OFF

145 170 182 ns max VS = 10 V; see Figure 31

Break-Before-Make Time Delay, tD

15 ns typ R

(ADG5413 Only) 6 ns min VS1 = VS2 = 10 V; see Figure 30 Charge Injection, Q

240 pC typ

INJ

Off Isolation −78 dB typ

Channel-to-Channel Crosstalk −70 dB typ

Total Harmonic Distortion + Noise 0.009 % typ

−3 dB Bandwidth 167 MHz typ

Insertion Loss −0.7 dB typ

CS (Off) 18 pF typ VS = 0 V, f = 1 MHz CD (Off) 18 pF typ VS = 0 V, f = 1 MHz CD (On), CS (On) 60 pF typ VS = 0 V, f = 1 MHz

= ±10 V, IS = −10 mA;

V

S

see Figure 24

= ±10 V, IS = −10 mA

S

V

= ±10 V, VD = 10 V;

S

Figure 27

see

V

= ±10 V, VD = 10 V;

S

Figure 27

see

GND

= 300 Ω, CL = 35 pF

L

= 0 V, RS = 0 Ω, CL = 1 nF;

V

S

m

or VDD

see Figure 32

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 26

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 25

= 1 kΩ, 15 V p-p, f = 20 Hz

R

L

to 20 kHz; see Figure 28

= 50 Ω, CL = 5 pF; see

R

L

Figure 29

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 29

Rev. A | Page 3 of 20

ADG5412/ADG5413

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 45 μA typ Digital inputs = 0 V or VDD 55 70 μA max ISS 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

±20 V DUAL SUPPLY

VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V On Resistance, RON 9 Ω typ

10 13 15 Ω max VDD = +18 V, VSS = −18 V On-Resistance Match Between

Channels, ∆R

ON

0.35 Ω typ V

0.7 0.9 1.1 Ω max On-Resistance Flatness, R

1.5 Ω typ VS = ±15 V, IS = −10 mA

FLAT (ON)

1.8 2.2 2.5 Ω max LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V

Source Off Leakage, IS (Off) ±0.05 nA typ

±0.25 ±0.75 ±3.5 nA max Drain Off Leakage, ID (Off) ±0.05 nA typ

±0.25 ±0.75 ±3.5 nA max Channel On Leakage, ID (On), IS (On) ±0.1 nA typ

±0.4 ±2 ±12 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

±0.1 μA max Digital Input Capacitance, CIN 2.5 pF typ

DYNAMIC CHARACTERISTICS1

tON 158 ns typ RL = 300 Ω, CL = 35 pF 187 217 240 ns max VS = 10 V; see Figure 31 t

110 ns typ RL = 300 Ω, CL = 35 pF

OFF

138 154 170 ns max VS = 10 V; see Figure 31 Break-Before-Make Time Delay, tD

12 ns typ R

(ADG5413 Only)

5 ns min

Charge Injection, Q

310 pC typ

INJ

Off Isolation −78 dB typ

Channel-to-Channel Crosstalk −70 dB typ

Rev. A | Page 4 of 20

= ±15 V, IS = −10 mA;

V

S

see Figure 24

= ±15 V, IS = −10 mA

S

V

= ±15 V, VD = 15 V;

S

Figure 27

see

V

= ±15 V, VD = 15 V;

S

Figure 27

see

= VD = ±15 V; see

V

S

m

Figure 23

or VDD

GND

= 300 Ω, CL = 35 pF

L

= VS2 = 10 V; see

V

S1

Figure 30

= 0 V, RS = 0 Ω, CL = 1 nF;

V

S

see Figure 32

= 50 Ω, CL = 5 pF, f = 1 MHz; see

R

L

Figure 26

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 25

ADG5412/ADG5413

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Total Harmonic Distortion + Noise 0.007 % typ

−3 dB Bandwidth 160 MHz typ

Insertion Loss −0.6 dB typ

CS (Off) 17 pF typ VS = 0 V, f = 1 MHz CD (Off) 17 pF typ VS = 0 V, f = 1 MHz CD (On), CS (On) 60 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +22 V, VSS = −22 V

IDD 50 μA typ Digital inputs = 0 V or VDD 70 110 μA max ISS 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance, RON 19 Ω typ

22 27 31 Ω max VDD = 10.8 V, VSS = 0 V On-Resistance Match Between Channels,

∆R

ON

0.8 1 1.2 Ω max On-Resistance Flatness, R

4.4 Ω typ VS = 0 V to 10 V, IS = −10 mA

FLAT (ON)

5.5 6.5 7.5 Ω max LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.05 nA typ

±0.25 ±0.75 ±3.5 nA max Drain Off Leakage, ID (Off) ±0.05 nA typ

±0.25 ±0.75 ±3.5 nA max Channel On Leakage, ID (On), IS (On) ±0.1 nA typ

±0.4 ±2 ±12 nA max DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

±0.1 μA max Digital Input Capacitance, CIN 2.5 pF typ

DYNAMIC CHARACTERISTICS1

tON 225 ns typ RL = 300 Ω, CL = 35 pF 296 358 403 ns max VS = 8 V; see Figure 31 t

150 ns typ RL = 300 Ω, CL = 35 pF

OFF

187 222 247 ns max VS = 8 V; see Figure 31

0.4 Ω typ V

= 1 kΩ, 20 V p-p, f = 20 Hz to

R

L

20 kHz; see Figure 28

= 50 Ω, CL = 5 pF;

R

L

see Figure 29

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 29

= 0 V to 10 V, IS = −10 mA;

V

S

see Figure 24

= 0 V to 10 V, IS = −10 mA

S

= 1 V/10 V, VD = 10 V/1 V;

V

S

see Figure 27

= 1 V/10 V, VD = 10 V/1 V;

V

S

see Figure 27

= VD = 1 V/10 V; see

V

S

Figure 23

or VDD

GND

Rev. A | Page 5 of 20

ADG5412/ADG5413

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Break-Before-Make Time Delay, tD

70 ns typ R

(ADG5413 Only) 38 ns min VS1 = VS2 = 8 V; see Figure 30 Charge Injection, Q

95 pC typ

INJ

Off Isolation −78 dB typ

Channel-to-Channel Crosstalk −70 dB typ

Total Harmonic Distortion + Noise 0.07 % typ

−3 dB Bandwidth 180 MHz typ

Insertion Loss −1.3 dB typ

CS (Off) 22 pF typ VS = 6 V, f = 1 MHz CD (Off) 22 pF typ VS = 6 V, f = 1 MHz CD (On), CS (On) 58 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD 40 μA typ Digital inputs = 0 V or VDD 65 μA max VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

= 300 Ω, CL = 35 pF

L

= 6 V, RS = 0 Ω, CL = 1 nF;

V

S

see Figure 32

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 26

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 25

= 1 kΩ, 6 V p-p, f = 20 Hz

R

L

to 20 kHz; see Figure 28

= 50 Ω, CL = 5 pF; see

R

L

Figure 29

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 29

36 V SINGLE SUPPLY

VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance, RON 10.6 Ω typ

12 15 17 Ω max VDD = 32.4 V, VSS = 0 V On-Resistance Match Between Channels,

∆R

ON

0.35 Ω typ V

0.7 0.9 1.1 Ω max On-Resistance Flatness, R

2.7 Ω typ VS = 0 V to 30 V, IS = −10 mA

FLAT(ON)

3.2 3.8 4.5 Ω max LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.05 nA typ

±0.25 ±0.75 ±3.5 nA max Drain Off Leakage, ID (Off) ±0.05 nA typ

±0.25 ±0.75 ±3.5 nA max Channel On Leakage, ID (On), IS (On) ±0.1 nA typ

±0.4 ±2 ±12 nA max

= 0 V to 30 V, IS = −10 mA;

V

S

see Figure 24

= 0 V to 30 V, IS = −10 mA

S

= 1 V/30 V, VD = 30 V/1 V;

V

S

see Figure 27

= 1 V/30 V, VD = 30 V/1 V;

V

S

see Figure 27

= VD = 1 V/30 V; see

V

S

Figure 23

Rev. A | Page 6 of 20

ADG5412/ADG5413

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

±0.1 μA max Digital Input Capacitance, CIN 2.5 pF typ

DYNAMIC CHARACTERISTICS1

tON 180 ns typ RL = 300 Ω, CL = 35 pF 220 230 248 ns max VS = 18 V; see Figure 31 t

130 ns typ RL = 300 Ω, CL = 35 pF

OFF

169 167 174 ns max VS = 18 V; see Figure 31

Break-Before-Make Time Delay, tD

(ADG5413 Only) 8 ns min VS1 = VS2 = 18 V; see Figure 30 Charge Injection, Q

Off Isolation −78 dB typ

Channel-to-Channel Crosstalk −70 dB typ

Total Harmonic Distortion + Noise 0.03 % typ

−3 dB Bandwidth 174 MHz typ

Insertion Loss −0.8 dB typ

CS (Off) 18 pF typ VS = 18 V, f = 1 MHz CD (Off) 18 pF typ VS = 18 V, f = 1 MHz CD (On), CS (On) 58 pF typ VS = 18 V, f = 1 MHz

POWER REQUIREMENTS VDD = 39.6 V

IDD 80 μA typ Digital inputs = 0 V or VDD 100 130 μA max VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

25 ns typ R

280 pC typ

INJ

= 300 Ω, CL = 35 pF

L

= 18 V, RS = 0 Ω, CL = 1 nF;

V

S

see Figure 32

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 26

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

Figure 25

= 1 kΩ, 18 V p-p, f = 20 Hz

R

L

to 20 kHz; see Figure 28

= 50 Ω, CL = 5 pF; see

R

L

Figure 29

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 29

GND

or VDD

CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx

Table 5.

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx OR Dx

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 89 59 37 mA maximum

LFCSP (θJA = 30.4°C/W) 160 94 49 mA maximum VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 95 63 39 mA maximum

LFCSP (θJA = 30.4°C/W) 170 98 50 mA maximum VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 61 43 29 mA maximum

LFCSP (θJA = 30.4°C/W) 110 70 42 mA maximum VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 80 54 35 mA maximum

LFCSP (θJA = 30.4°C/W) 144 87 47 mA maximum

Rev. A | Page 7 of 20

ADG5412/ADG5413

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to VSS 48 V VDD to GND −0.3 V to +48 V VSS to GND +0.3 V to −48 V Analog Inputs1

Digital Inputs1

Peak Current, Sx or Dx Pins

Continuous Current, Sx or Dx2 Data + 15% Temperature Range

Operating −40°C to +125°C

Storage −65°C to +150°C Junction Temperature 150°C Thermal Impedance, θJA

16-Lead TSSOP (4-Layer

Board)

16-Lead LFCSP (4-Layer

Board)

Reflow Soldering Peak

Temperature, Pb Free

1

Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.

Limit current to the maximum ratings given.

2

See Table 5.

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first 278 mA (pulsed at 1 ms, 10%

duty cycle maximum)

112.6°C/W

30.4°C/W

260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating can be applied at any one time.

ESD CAUTION

Rev. A | Page 8 of 20

ADG5412/ADG5413

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

IN1

D

D2

1

IN1

D1

2

S1

3

ADG5412/

V

4

SS

ADG5413

TOP VIEW

5

GND

(Not to Scal e)

S4

6

D4

7

8

IN4

NC = NO CONNECT

Figure 2. TSSOP Pin Configuration

16

IN2

D2

15

S2

14

V

13

DD

12

NC

S3

11

D3

10

9

IN3

09202-002

1S1

2V

SS

3GND

4S4

NOTES

1. EXPOSED PAD TIED TO SUBSTRATE, V

2. NC = NO CONNECT .

Figure 3. LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 IN1 Logic Control Input 1. 2 16 D1 Drain Terminal 1. This pin can be an input or output. 3 1 S1 Source Terminal 1. This pin can be an input or output. 4 2 VSS Most Negative Power Supply Potential. 5 3 GND Ground (0 V) Reference. 6 4 S4 Source Terminal 4. This pin can be an input or output. 7 5 D4 Drain Terminal 4. This pin can be an input or output. 8 6 IN4 Logic Control Input 4. 9 7 IN3 Logic Control Input 3. 10 8 D3 Drain Terminal 3. This pin can be an input or output. 11 9 S3 Source Terminal 3. This pin can be an input or output. 12 10 NC No Connection. 13 11 VDD Most Positive Power Supply Potential. 14 12 S2 Source Terminal 2. This pin can be an input or output. 15 13 D2 Drain Terminal 2. This pin can be an input or output. 16 14 IN2 Logic Control Input 2. EP Exposed Pad

The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, V

.

SS

IN2

14

15

16

PIN 1 INDICATO R

ADG5412/

ADG5413

TOP VIEW

(Not to Scale)

7

5

6

D4

IN4

IN3

13

12 S2

11 V

DD

10 NC

9S3

8

D3

.

SS

09202-003

Table 8. ADG5412 Truth Table

INx Switch Condition

1 On 0 Off

Table 9. ADG5413 Truth Table

INx S1, S4 S2, S3

0 Off On 1 On Off

Rev. A | Page 9 of 20

ADG5412/ADG5413

TYPICAL PERFORMANCE CHARACTERISTICS

16

14

12

TA = 25°C

VDD = +9V V

VDD = +11V V

= –11V

SS

= –9V

VDD = +10V V

= –10V

SS

12

10

8

TA = 25°C

VDD = 36V V

= 0V

SS

VDD = 32.4V V

= 0V

SS

8

6

ON RESISTANCE ()

4

2

0

–20 –15 –1010–5 0 5 10 15 20

10

VDD = +13.5V V

= –13.5V

SS

Figure 4. R

VDD = +15V V

= –15V

SS

VS, VD (V)

as a Function of VS, VD (Dual Supply)

ON

VDD = +16.5V V

= –16.5V

SS

12

VDD = +18V V

= –18V

VS, VD (V)

SS

VDD = +20V V

= –20V

SS

VDD = +22V V

SS

10

8

6

4

ON RESISTANCE ()

2

TA = 25°C

0

–25 –20 –15 –10 –5 0 5 10 15 20 25

Figure 5. R

as a Function of VS, VD (Dual Supply)

ON

25

TA = 25°C

20

15

10

ON RESISTANCE ()

5

0

0 2 4 6 8 101214

Figure 6. R

VDD = +10V V

= 0V

SS

VDD = +9V V

= 0V

SS

VDD = 12V

= 0V

V

SS

as a Function of VS, VD (Single Supply)

ON

VDD = 13.2V

= 0V

V

SS

VS, VD (V)

VDD = 10.8V

= 0V

V

SS

VDD = 11V V

= 0V

SS

= –22V

6

4

ON RESISTANCE ()

2

0

0 5 10 15 20 25 30 35 40 45

09202-034

Figure 7. R

as a Function of VS, VD (Single Supply)

ON

VDD = 39.6V V

= 0V

SS

VS, VD (V)

09202-033

18

16

14

12

10

8

6

ON RESISTANCE ()

4

2

VDD = +15V V

= –15V

SS

0

–15 –10 –5 0 5 10 15

09202-035

Figure 8. R

as a Function of VS (VD) for Different Temperatures,

ON

TA = +125°C

= +85°C

T

A

T

= +25°C

A

= –40°C

T

A

VS, VD (V)

09202-040

±15 V Dual Supply

16

14

12

10

8

6

ON RESISTANCE ()

4

2

VDD = +20V V

= –20V

SS

0

–20 –15 –10 –5 0 5 10 15 20

09202-032

Figure 9. R

as a Function of VS (VD) for Different Temperatures,

ON

TA = +125°C

T

= +85°C

A

= +25°C

T

A

= –40°C

T

A

VS, VD (V)

09202-041

±20 V Dual Supply

Rev. A | Page 10 of 20

ADG5412/ADG5413

30

VDD = 12V V

= 0V

SS

25

20

15

10

ON RESISTANCE ()

5

0

024681012

Figure 10. R

as a Function of VS (VD) for Different Temperatures,

ON

TA = +125°C

= +85°C

T

A

T

= +25°C

A

= –40°C

T

A

, VD (V)

V

S

12 V Single Supply

16

14

12

10

8

6

ON RESISTANCE ()

4

TA = +125°C

T

= +85°C

A

= +25°C

T

A

= –40°C

T

A

0.8 VDD = +20V

V

= –20V

SS

V

= +15V/–15V

BIAS

0.6

0.4

0.2

0

–0.2

LEAKAGE CURRENT (n A)

–0.4

–0.6

0 25 50 75 100 125

09202-042

TEMPERATURE (°C)

ID (OFF) – +

ID, IS (ON) + +

ID, IS (ON) – –

I

(OFF) + –

S

IS (OFF) – +

ID (OFF) + –

09202-038

Figure 13. Leakage Currents vs. Temperature, ±20 V Dual Supply

0.6 VDD = 12V V

= 0V

SS

V

= 1V/10V

BIAS

0.4

0.2

LEAKAGE CURRENT (n A)

0

ID, IS (ON) – –

(OFF) + –

I

S

ID (OFF) – +

ID, IS (ON) + +

2

VDD = 36V V

= 0V

SS

0

Figure 11. R

10 15

5

as a Function of VS (VD) for Different Temperatures,

ON

20 25

VS, VD (V)

30 35 40

36 V Single Supply

0.8 VDD = +15V

V

= –15V

SS

V

= +10V/–10V

BIAS

0.6

0.4

0.2

0

LEAKAGE CURRENT ( nA)

–0.2

–0.4

0 255075100125

ID (OFF) – +

TEMPERATURE (°C)

ID, IS (ON) + +

ID, IS (ON) – –

(OFF) + –

I

S

IS (OFF) – +

ID (OFF) + –

Figure 12. Leakage Currents vs. Temperature, ±15 V Dual Supply

ID (OFF) + –

–0.2

0 255075100125

09202-043

TEMPERATURE (°C)

IS (OFF) – +

09202-036

Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply

0.8 VDD = 36V V

= 0V

SS

V

= 1V/30V

BIAS

0.6

0.4

0.2

0

–0.2

LEAKAGE CURRENT (n A)

–0.4

–0.6

0 25 50 75 100 125

09202-037

TEMPERATURE (°C)

ID, IS (ON) + +

ID, IS (ON) – –

ID (OFF) – +

IS (OFF) – +

ID (OFF) + –

I

(OFF) + –

S

09202-039

Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply

Rev. A | Page 11 of 20

ADG5412/ADG5413

A

0

T

= 25°C

A

V

= +15V

DD

–10

V

= –15V

SS

–20

–30

–40

TION (dB)

–50

–60

OFF ISOL

–70

–80

–90

–100

10k 100k 1M 10M 100M 1G1k

FREQUENCY (Hz)

Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply

09202-025

0

T

= 25°C

A

= +15V

V

DD

–10

= –15V

V

SS

–20

–30

–40

–50

–60

ACPSRR (dB)

–70

–80

–90

–100

1k 1M 10M10k 100k

FREQUENCY ( Hz)

NO DECOUPLI NG CAPACITORS

DECOUPLING CAPACITORS

Figure 19. ACPSRR vs. Frequency, ±15 V Dual Supply

09202-026

0

TA = 25°C V

= +15V

DD

–10

V

= –15V

SS

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

–100

10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply

500

TA = 25°C

450

400

350

300

250

200

150

CHARGE INJECTI ON (pC)

100

50

0

–20 –10 0 10 20 30 40

V V

DD SS

= +15V = –15V

VDD = +20V V

= –20V

SS

VS (V)

VDD = +36V V

SS

VDD = +12V V

= 0V

SS

= 0V

Figure 18. Charge Injection vs. Source Voltage

09202-028

09202-030

0.10

LOAD = 1k T

= 25°C

A

0.09

0.08

0.07

0.06

0.05

0.04

THD + N (%)

0.03

0.02

0.01

0

0 5 10 15 20

= 12V, VSS = 0V, VS = 6V p-p

V

DD

VDD = 36V, VSS = 0V, VS = 18V p-p

VDD = 15V, VSS = 15V, VS = 15V p-p

= 20V, VSS = 20V, VS = 20V p-p

V

DD

FREQUENCY (MHz)

Figure 20. THD + N vs. Frequency, ±15 V Dual Supply

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

INSERTION LOSS (dB)

–4.0

–4.5

–5.0

10k 100k 1M 10M 100M1k 1G

FREQUENCY (Hz)

Figure 21. Bandwidth

TA = 25°C

= +15V

V

DD

= –15V

V

SS

09202-027

09202-029

Rev. A | Page 12 of 20

ADG5412/ADG5413

350

300

t

(12V)

250

200

150

TIME (ns)

ON

t

(±15V)

t

(36V)

ON

t

OFF

t

(±20V)

ON

(±15V)

100

50

0

–40 –20 0 20 40 60 80 100 120

t

OFF

Figure 22. t

t

(36V)

OFF

TEMPERATURE (°C)

, t

Times vs. Temperature

ON

OFF

(12V)

t

OFF

(±20V)

09202-031

Rev. A | Page 13 of 20

ADG5412/ADG5413

V

VDDV

V

TEST CIRCUITS

Sx Dx

S

Figure 23. On Leakage

IS(OFF) ID (OFF)

ID (ON)

Sx Dx

A A

A

V

D

09202-016

S

V

D

09202-015

Figure 27. Off Leakage

I

DS

V1

Sx Dx

S

RON = V1/I

DS

Figure 24. On Resistance

DD

0.1µF

NETWORK ANALYZER

V

OUT

R

L

50

V

S

CHANNEL-TO-CHANNEL CROSSTAL K = 20 log

V

S1

S2

Figure 25. Channel-to-Channel Crosstalk

GND

SS

R

1k

L

AUDIO PRECISION

R

S

V

S

V p-p

V

OUT

09202-024

V

SS

Sx

Dx

0.1µF 0.1µF

V

DD

INx

IN

09202-014

Figure 28. THD + Noise

SS

0.1µF

V

DD

SS

Dx

R

L

50

GND

V

OUT

S

09202-021

V

INx

IN

0.1µF

DD

V

SS

V

DD

SS

Sx

Dx

GND

INSERTION LOSS = 20 log

0.1µF

NETWORK

ANALYZER

50

R

L

50

V

WITH SWITCH

OUT

V

WITHOUT SWITCH

OUT

V

S

V

OUT

09202-023

Figure 29. Bandwidth

DD

0.1µF

V

INx

V

IN

SS

0.1µF

NETWO RK

V

DD

GND

SS

Sx

50

Dx

OFF ISOLATION = 20 log

ANALYZER

50

V

OUT

R

L

50

V

S

V

OUT

V

S

09202-020

Figure 26. Off Isolation

Rev. A | Page 14 of 20

ADG5412/ADG5413

V

VDDV

V

DD

SS

0.1µF

V

DD

IN1, IN2

S1 D1

S2 D2

ADG5413

GND

V

S1

V

S2

0.1µF

V

SS

R

L

R

L

300

C

L

35pF

V

OUT2

300

C

L

35pF

V

OUT1

Figure 30. Break-Before-Make Time Delay, t

V

DD

SS

0.1µF

V

DD

Sx

S

INx

GND

0.1µF

V

SS

V

C

L

35pF

OUT

Dx

R

L

300

IN

V

OUT

Figure 31. Switching Times

V

OUT1

V

OUT2

ADG5412

V

IN

0V

90%

0V

D

50% 50%

90% 90%

t

ON

50% 50%

90%

t

D

t

OFF

90%

t

D

09202-017

09202-018

SS

V

DD

SS

C 1nF

V

OUT

L

R

S

V

S

Sx Dx

IN

GND

V

IN

V

OUT

ADG5412

Q

INJ

ON

= CL × V

OUT

V

OFF

OUT

09202-019

Figure 32. Charge Injection

Rev. A | Page 15 of 20

ADG5412/ADG5413

TERMINOLOGY

IDD

I

represents the positive supply current.

DD

I

SS

I

represents the negative supply current.

SS

, VS

V

D

V

and VS represent the analog voltage on Terminal D and

D

Ter m in a l S , res pe c ti v ely.

R

ON

R

represents the ohmic resistance between Terminal D and

ON

Ter m in a l S .

ΔR

ON

represents the difference between the RON of any two

ΔR

ON

channels.

R

FLAT (ON)

Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by R

(Off)

I

S

I

(Off) is the source leakage current with the switch off.

S

(Off)

I

D

I

(Off) is the drain leakage current with the switch off.

D

(On), IS (On)

I

D

I

(On) and IS (On) represent the channel leakage currents with

D

the switch on.

V

INL

V

is the maximum input voltage for Logic 0.

INL

V

INH

V

is the minimum input voltage for Logic 1.

INH

I

, I

INL

INH

I

INL

and I

represent the low and high input currents of the

INH

digital inputs.

C

(Off)

D

C

(Off) represents the off switch drain capacitance, which is

D

measured with reference to ground.

C

(Off)

S

C

(Off) represents the off switch source capacitance, which is

S

measured with reference to ground.

C

(On), CS (On)

D

C

(On) and CS (On) represent on switch capacitances, which

D

are measured with reference to ground.

FLAT (ON)

.

C

IN

C

is the digital input capacitance.

IN

t

ON

t

represents the delay between applying the digital control

ON

input and the output switching on.

t

OFF

t

represents the delay between applying the digital control

OFF

input and the output switching off.

t

D

represents the off time measured between the 80% point of

t

D

both switches when switching from one address state to another.

Off Isolation

Off isolation is a measure of unwanted signal coupling through an off switch.

Charge Injection

Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching.

Crosstalk

Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.

Bandwidth

Bandwidth is the frequency at which the output is attenuated by 3 dB.

On Response

On response is the frequency response of the on switch.

Insertion Loss

Insertion loss is the loss due to the on resistance of the switch.

Total Harmonic Distortion + Noise (THD + N)

The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by THD + N.

AC Power Supply Rejection Ratio (ACPSRR)

ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.

Rev. A | Page 16 of 20

ADG5412/ADG5413

TRENCH ISOLATION

In the ADG5412 and ADG5413, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latchup proof switch.

NMOS PMOS

P-WELL N-WELL

TRENCH

BURIED OXIDE L AYER

HANDLE WAFER

Figure 33. Trench Isolation

09202-022

Rev. A | Page 17 of 20

ADG5412/ADG5413

APPLICATIONS INFORMATION

The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5412/ADG5413 high voltage switches

allow single-supply operation from 9 V to 40 V and dual-supply operation from ±9 V to ±22 V. The ADG5412/ADG5413 (as well as other select devices within the same family) achieve an 8 kV human body model ESD rating, which provides a robust solution eliminating the need for separate protect circuitry designs in some applications.

Rev. A | Page 18 of 20

ADG5412/ADG5413

S

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

EATING

PLANE

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65 BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20 MAX

SEATING PLANE

6.40

BSC

0.20

0.09 8°

0°

Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

4.10

4.00 SQ

3.90

0.65

BSC

0.45

0.40

0.35

0.05 MAX

0.02 NOM

0.20 REF

0.35

0.30

0.25

13

12

9

8

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

EXPOSED

PAD

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

0.75

0.60

0.45

N

1

I

P

R

O

C

I

A

T

N

I

16

5

D

1

4

2.70

2.60 SQ

2.50

0.20 MIN

COMPLIANT

TO

JEDEC STANDARDS MO-220-WGGC.

08-16-2010-C

Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-16-17)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADG5412BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG5412BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG5412BCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17 ADG5413BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG5413BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG5413BCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17

1

Z = RoHS Compliant Part.

Rev. A | Page 19 of 20

ADG5412/ADG5413

NOTES

Rev. A | Page 20 of 20

Datasheet ADG5412 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

±15 V DUAL SUPPLY

±20 V DUAL SUPPLY

12 V SINGLE SUPPLY

36 V SINGLE SUPPLY

CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

TERMINOLOGY

TRENCH ISOLATION

APPLICATIONS INFORMATION

OUTLINE DIMENSIONS

ORDERING GUIDE