Page 1
CMOS Latched
S8A
S1ADBS8BS
FEATURES
44 V supply maximum rating
V
to VDD analog signal range
SS
Single- or dual-supply specifications
Wide supply ranges (10.8 V to 16.5 V)
Microprocessor compatible (100 ns
Extended plastic temperature range (−40°C to +85°C)
Low leakage (20 pA typical)
Low power dissipation (28 mW maximum)
Available in PDIP, CERDIP, SOIC, and PLCC packages
Superior alternative to DG526 and DG527
APPLICATIONS
Data acquisition systems
Communication systems
Automatic test equipment
Microprocessor controlled systems
GENERAL DESCRIPTION
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 single channels and dual 8 channels,
respectively. On-chip latches facilitate microprocessor interfacing.
The ADG526A switches one of 16 inputs to a common output,
depending on the state of four binary addresses and an enable
input. The ADG527A switches one of eight differential inputs to
a common differential output, depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic-compatible digital inputs.
The ADG526A and ADG527A are designed on an enhanced
2
LC
MOS process that gives an increased signal capability of VSS
to V
and enables operation over a wide range of supply
DD
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single- or dual-supply range. These multiplexers
also feature high switching speeds and low R
WR
pulse)
ON
.
8-/16-Channel Analog Multiplexers
ADG526A/ADG527A
FUNCTIONAL BLOCK DIAGRAMS
ADG526A
S1
D
S16
WR
1B
WR
PRODUCT HIGHLIGHTS
1. Single- or Dual-Supply Specifications with a Wide
Tolerance. The devices are specified in the 10.8 V to
16.5 V range for both single and dual supplies.
2. Easily Interfaced. The ADG526A and ADG527A can be
easily interfaced with microprocessors. The
latches the state of the address control lines and the enable
RS
line. The
in the latches, resulting in no output (all switches off).
can be tied to the microprocessor reset pin.
3. Extended Signal Range. The enhanced LC
processing results in a high breakdown and an increased
analog signal range from V
4. Break-Before-Make Switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
5. Low Leakage. Leakage currents in the range of 20 pA
make these multiplexers suitable for high precision circuits.
signal clears both the address and enable data
DECODER/
LATCHES
A0 A1 A2 A3 EN RS
Figure 1. ADG526A
ADG527A
DECODER/
LATCHES
A0 A1 A2 EN RS
Figure 2. ADG527A
to VDD.
SS
DA
01532-001
01532-002
2
MOS
WR
signal
RS
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
Page 2
ADG526A/ADG527A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................ 7
REVISION HISTORY
6/08—Rev. B to Rev. C.
Updated Format .................................................................. Universal
ADG526A LCCC Package Removed ............................... Universal
Changes to Features .......................................................................... 1
Added Applications Section ............................................................ 1
Changes to Absolute Maximum Ratings ....................................... 7
Added Table 4, Renumbered Sequentially .................................... 8
Added Table 5 .................................................................................... 9
Changes to Figure 7 and Figure 8 ................................................. 11
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 19
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Typical Performance Characteristics ........................................... 11
Term inology .................................................................................... 12
Timing .............................................................................................. 13
Test Circuits ..................................................................................... 14
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 19
2/02—Rev. A to Rev. B.
Edits to Specifications Table, Dual Supply ..................................... 2
Edits to Specifications Table, Single Supply ................................... 3
Edits to Ordering Guide ................................................................... 4
Removal of one Pin Configuration and Diagram ......................... 6
Rev. C | Page 2 of 20
Page 3
ADG526A/ADG527A
SPECIFICATIONS
DUAL SUPPLY
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted.
Table 1.
ADG526A/ADG527A ADG526A
K Version B Version T Version
Parameter
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C
ANALOG SWITCH
Analog Signal Range VSS VSS VSS VSS VSS VSS V min
V
VDD VDD VDD VDD VDD V max
DD
RON 280 280 280 Ω typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA;
450 600 450 600 450 600 Ω max
300 400 300 400 Ω max VDD = +15 V (±10%),
300 400 Ω max VDD = +15 V (±5%),
RON Drift 0.6 0.6 0.6 %/°C typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA
RON Match 5 5 5 % typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA
IS (Off), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = ±10 V, V2 = 10 V;
1 50 1 50 1 50 nA max
ID (Off), Off Output
0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = 10 V;
Leakage
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
ID (On), On Channel
0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = 10 V;
Leakage
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
I
, Differential Off
DIFF
25 25 nA max V1 = ±10 V, V2 = 10 V;
Output Leakage
(ADG527A Only)
DIGITAL CONTROL
V
, Input High Voltage 2.4 2.4 2.4 V min
INH
V
, Input Low Voltage 0.8 0.8 0.8 V max
INL
I
or I
1 1 1 μA max VIN = 0 to VDD
INL
INH
CIN, Digital Input
8 8 8 pF max
Capacitance
DYNAMIC
CHARACTERISTICS
t
200 200 200 ns typ V1 = ±10 V, V2 = 10 V;
TRANSITION
1
300 400 300 400 300 400 ns max
t
50 50 50 ns typ See Figure 21
OPEN
25 10 25 10 25 10 ns min
tON (EN, WR)
200 200 200 ns typ See Figure 22 and Figure 23
300 400 300 400 300 400 ns max
t
(EN, RS)
OFF
200 200 200 ns typ See Figure 22 and Figure 24
300 400 300 400 300 400 ns max
tW , Write Pulse Width 100 120 100 120 100 130 ns min See Figure 13
tS, Address Enable Setup
100 100 100 ns min See Figure 13
Time
tH, Address Enable Hold
10 10 10 ns min See Figure 13
Time
tRS, Reset Pulse Width 100 100 100 ns min See Figure 14
Unit Comments
see Figure 15
= −15 V (±10%)
V
SS
= −15 V (±5%)
V
SS
see Figure 16
see Figure 17
see Figure 18
see Figure 19
see Figure 20
Rev. C | Page 3 of 20
Page 4
ADG526A/ADG527A
ADG526A/ADG527A ADG526A
K Version B Version T Version
Parameter
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C
Off Isolation 68 68 68 dB typ VEN = 0.8 V, RL = 1 kΩ, CL =
50 50 50 dB min VS = 7 V rms, f = 100 kHz
CS (Off) 5 5 5 pF typ VEN = 0.8 V
CD (Off)
ADG526A 44 44 44 pF typ VEN = 0.8 V
ADG527A 22 22 pF typ
Q
, Charge Injection 4 4 4 pC typ RS = 0 Ω, VS = 0 V;
INJ
POWER SUPPLY
IDD 0.6 0.6 0.6 mA typ V
1.5 1.5 1.5 mA max
ISS 20 20 20 μA typ VIN = V
0.2 0.2 0.2 mA max
Power Dissipation 10 10 10 mW typ
28 28 28 mW max
1
Sample tested at 25°C to ensure compliance.
Unit Comments
= 7 V rms, f = 100 kHz
15 pF,V
S
see Figure 25
= V
or V
IN
INL
or V
INL
INH
INH
Rev. C | Page 4 of 20
Page 5
ADG526A/ADG527A
SINGLE SUPPLY
VDD = 10.8 V to 16.5 V, VSS = GND to 0 V, unless otherwise noted.
Table 2.
ADG526A/ADG527A ADG526A
K Version B Version T Version
Parameter
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C
ANALOG SWITCH
Analog Signal Range VSS VSS VSS VSS VSS VSS V min
V
VDD VDD VDD VDD VDD V max
DD
RON 500 500 500 Ω typ
700 1000 700 1000 700 1000 Ω max
RON Drift 0.6 0.6 0.6 %/°C typ
RON Match 5 5 5 % typ
IS (Off), Off Input
0.02 0.02 0.02 nA typ V1 = 10 V/0 V, V2 = 0 V/
Leakage
1 50 1 50 1 50 nA max
ID (Off), Off Output
0.04 0.04 0.04 nA typ V1 = 10 V/0 V, V2 = 0 V/
Leakage
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
ID (On), On Channel
0.04 0.04 0.04 nA typ V1 = 10 V/0 V, V2 = 0 V/
Leakage
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
I
, Differential Off
DIFF
25 25 nA max V1 = 10 V/0 V, V2 = 0 V/
Output Leakage
(ADG527A Only)
DIGITAL CONTROL
V
, Input High Voltage 2.4 2.4 2.4 V min
INH
V
, Input Low Voltage 0.8 0.8 0.8 V max
INL
I
or I
1 1 1 μA max VIN = 0 to VDD
INL
INH
CIN, Digital Input
8 8 8 pF max
Capacitance
DYNAMIC
CHARACTERISTICS
t
300 300 300 ns typ V1 = 10 V/0 V, V2 = 0 V/
TRANSITION
1
450 600 450 600 450 600 ns max
t
50 50 50 ns typ See Figure 21
OPEN
25 10 25 10 25 10 ns min
tON (EN, WR)
250 250 250 ns typ See Figure 22 and Figure 23
450 600 450 600 450 600 ns max
t
(EN, RS)
OFF
250 250 250 ns typ See Figure 22 and Figure 24
450 600 450 600 450 600 ns max
tW Write Pulse Width 100 120 100 120 100 130 ns min See Figure 13
tS Address Enable
100 100 100 ns min See Figure 13
Setup Time
tH Address Enable Hold
10 10 10 ns min See Figure 13
Time
tRS Reset Pulse Width 100 100 100 ns min See Figure 14
Off Isolation 68 68 68 dB typ VEN = 0.8 V, RL = 1 kΩ, CL =
50 50 50 dB min VS = 3.5 V rms, f = 100 kHz
Unit Comments
0 V ≤ V
≤ 10 V, IDS =
S
0.5 mA; see Figure 15
0 V ≤ V
≤ 10 V, IDS =
S
0.5 mA
0 V ≤ V
≤ 10 V, IDS =
S
0.5 mA
10 V; see Figure 16
10 V; see Figure 17
10 V; see Figure 18
10 V; see Figure 19
10 V; see Figure 20
15 pF
Rev. C | Page 5 of 20
Page 6
ADG526A/ADG527A
ADG526A/ADG527A ADG526A
K Version B Version T Version
Parameter
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C
CS (Off) 5 5 5 pF typ VEN = 0.8 V
CD (Off)
ADG526A 44 44 44 pF typ VEN = 0.8 V
ADG527A 22 22 pF typ
Q
, Charge Injection 4 4 4 pC typ RS = 0 Ω, VS = 0 V; see
INJ
POWER SUPPLY
IDD 0.6 0.6 0.6 mA typ VIN = V
1.5 1.5 1.5 mA max
Power Dissipation 11 11 11 mW typ
25 25 25 mW max
1
Sample tested at 25°C to ensure compliance.
Unit Comments
Figure 25
or V
INL
INH
Rev. C | Page 6 of 20
Page 7
ADG526A/ADG527A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to VSS 44 V
VDD to GND 25 V
VSS to GND
Analog Inputs1
Voltage at Sx or Dx Pins
Continuous Current, Sx or Dx Pins 20 mA
Pulsed Current, Sx or Dx Pins
1 ms Duration, 10% Duty Cycle 40 mA
Digital Inputs1
Voltage at A, EN, WR, RS
Power Dissipation (Any Package)
Up to 75°C 470 mW
Derates Above 75°C 6 mW/°C
Operating Temperature Range
Commercial (K Version)
Industrial (B Version)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec) 300°C
1
Overvoltage at A, EN, WR, RS, Sx, or Dx pins are clamped by diodes. Limit
current to the maximum rating in . Table 3
−25 V
− 2 V to VDD + 2 V
V
SS
or 20 mA, whichever
occurs first
VSS − 4 V to VDD + 4 V
or 20 mA, whichever
occurs first
−40°C to +85°C
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 7 of 20
Page 8
ADG526A/ADG527A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
DD
NC
2
RS
3
S16
4
ADG526A
S15
5
TOP VIEW
S14
6
(Not to Scale)
S13
7
S12
8
S11
9
S10
10
S9
11
GND
12
WR
13
A3
14
NC = NO CONNECT
Figure 3. ADG526A PDIP, SOIC, and CERDIP Pin Configuration
D
28
V
27
SS
S8
26
S7
25
S6
24
S5
23
S4
22
S3
21
S2
20
S1
19
EN
18
A0
17
A1
16
A2
15
1532-005
S15
S14
S13
S12
S11
S10
S09
Figure 4. ADG526A PLCC Pin Configuration
S16RSNC
5
6
7
8
9
10
11
PIN 1
IDENTFIER
ADG526A
TOP VIEW
(Not to S cale)
12 13 14 15 16 17 18
WR
GND
NC = NO CONNECT
Table 4. ADG526A Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 NC No Connect.
3
Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off ).
RS
4 S16 Source Terminal. This pin can be an input or output.
5 S15 Source Terminal. This pin can be an input or output.
6 S14 Source Terminal. This pin can be an input or output.
7 S13 Source Terminal. This pin can be an input or output.
8 S12 Source Terminal. This pin can be an input or output.
9 S11 Source Terminal. This pin can be an input or output.
10 S10 Source Terminal. This pin can be an input or output.
11 S9 Source Terminal. This pin can be an input or output.
12 GND Ground (0 V) Reference.
13
Write. The WR signal latches the state of the address control lines and the enable line.
WR
14 A3 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
15 A2 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
16 A1 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
17 A0 Logic control inputs. Selects which source terminal is connected to the drain (D).
18 EN Enable. Active high logic control input.
19 S1 Source Terminal. This pin can be an input or output.
20 S2 Source Terminal. This pin can be an input or output.
21 S3 Source Terminal. This pin can be an input or output.
22 S4 Source Terminal. This pin can be an input or output.
23 S5 Source Terminal. This pin can be an input or output.
24 S6 Source Terminal. This pin can be an input or output.
25 S7 Source Terminal. This pin can be an input or output.
26 S8 Source Terminal. This pin can be an input or output.
27 VSS Most Negative Power Supply Potential.
28 D Drain Terminal. This pin can be an input or output.
VDDD
1282726234
A3A2A1
VSSS8
A0
EN
25
S7
24
S6
23
S5
22
S4
21
S3
20
S2
S1
19
1532-007
Rev. C | Page 8 of 20
Page 9
ADG526A/ADG527A
1
V
DD
2
DB
3
RS
4
S8B
5
S7B
ADG527A
6
S6B
S5B
S4B
S3B
S2B
S1B
GND
TOP VIEW
7
(Not to Scale)
8 21
9 20
10 19
11 18
12 17
13 16
WR
14 15
NC
NC = NO CONNECT
Figure 5. ADG527A PDIP, SOIC Pin Configuration
Table 5. ADG527A Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 DB Drain Terminal. This pin can be an input or output.
3
Reset. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off).
RS
4 S8B Source Terminal. This pin can be an input or output.
5 S7B Source Terminal. This pin can be an input or output.
6 S6B Source Terminal. This pin can be an input or output.
7 S5B Source Terminal. This pin can be an input or output.
8 S4B Source Terminal. This pin can be an input or output.
9 S3B Source Terminal. This pin can be an input or output.
10 S2B Source Terminal. This pin can be an input or output.
11 S1B Source Terminal. This pin can be an input or output.
12 GND Ground (0 V) Reference.
13
Write. The WR signal latches the state of the address control lines and the enable line.
WR
14 NC No Connect.
15 A2 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
16 A1 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
17 A0 Logic Control Inputs. Selects which source terminal is connected to the drain (D).
18 EN Enable. Active high logic control input.
19 S1A Source Terminal. This pin can be an input or output.
20 S2A Source Terminal. This pin can be an input or output.
21 S3A Source Terminal. This pin can be an input or output.
22 S4A Source Terminal. This pin can be an input or output.
23 S5A Source Terminal. This pin can be an input or output.
24 S6A Source Terminal. This pin can be an input or output.
25 S7A Source Terminal. This pin can be an input or output.
26 S8A Source Terminal. This pin can be an input or output.
27 VSS Most Negative Power Supply Potential.
28 DA Drain Terminal. This pin can be an input or output.
28
DA
V
27
SS
26
S8A
25
S7A
24
S6A
23
S5A
22
S4A
S3A
S2A
S1A
EN
A0
A1
A2
01532-006
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S8BRSDB
5
6
7
8
9
10
11
PIN 1
IDENTFIER
ADG527A
TOP VIEW
(Not to S cale)
12 13 14 15 16 17 18
NC
WR
GND
NC = NO CONNECT
VDDDA
1282726234
A2A1A0
VSSS8A
EN
25
S7A
24
S6A
23
S5A
22
S4A
21
S3A
20
S2A
S1A
19
01532-008
Figure 6. ADG527A PLCC Pin Configuration
Rev. C | Page 9 of 20
Page 10
ADG526A/ADG527A
Table 6. ADG526A Truth Table1
A3 A2 A1 A0 EN
X X X X X
WR
X X X X X X 0 None (address and enable latches cleared)
X X X X 0 0 1 None
0 0 0 0 1 0 1 1
0 0 0 1 1 0 1 2
0 0 1 0 1 0 1 3
0 0 1 1 1 0 1 4
0 1 0 0 1 0 1 5
0 1 0 1 1 0 1 6
0 1 1 0 1 0 1 7
0 1 1 1 1 0 1 8
1 0 0 0 1 0 1 9
1 0 0 1 1 0 1 10
1 0 1 0 1 0 1 11
1 0 1 1 1 0 1 12
1 1 0 0 1 0 1 13
1 1 0 1 1 0 1 14
1 1 1 0 1 0 1 15
1 1 1 1 1 0 1 16
1
X = don’t care.
RS
ON SWITCH
1 Retains previous switch condition
Table 7. ADG527A Truth Table1
A2 A1 A0 EN
X X X X
WR
ON SWITCH PAIR
RS
1 Retains previous switch condition
X X X X X 0 None (address and enable latches cleared)
X X X 0 0 1 None
0 0 0 1 0 1 1
0 0 1 1 0 1 2
0 1 0 1 0 1 3
0 1 1 1 0 1 4
1 0 0 1 0 1 5
1 0 1 1 0 1 6
1 1 0 1 0 1 7
1 1 1 1 0 1 8
1
X = don’t care.
Rev. C | Page 10 of 20
Page 11
ADG526A/ADG527A
TYPICAL PERFORMANCE CHARACTERISTICS
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
700
1.9
600
500
400
(Ω)
ON
R
300
200
100
0
–20 –15 –10 –5 0 5 10 15 20
VD (VS) (V)
VDD = 10.8V
V
= 0V
SS
V
V
DD
SS
= 15V
= 0V
Figure 7. RON as a Function of VD (VS): Single-Supply Voltage, TA = 25°C
700
600
500
400
(Ω)
ON
R
300
200
100
0
–20 –15 –10 –5 0 5 10 15 20
VDD = +5V
V
= –5V
SS
= +10.8V
V
DD
V
= –10.8V
SS
V
DD
V
SS
VD (VS) (V)
= +15V
= –15V
Figure 8. RON as a Function of VD (VS): Dual-Supply Voltage, TA = 25°C
1.8
1.7
TRIGGER LEVEL (V)
1.6
1.5
56789101112131415
01532-009
SUPPLY VOLTAGE (V)
01532-012
Figure 10. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply,
= 25°C
T
A
800
700
600
(ns)
500
400
TRANSITI ON
t
300
200
100
56789101112131415
01532-010
Figure 11. t
TRANSITION
(Note: For V
and VSS <10 V; V1 = VDD/VSS, V2 = VSS/VDD; See Figure 20)
DD
SINGLE
SUPPLY
DUAL
SUPPLY
SUPPLY VOLTAGE (V)
01532-013
vs. Supply Voltage: Dual and Single Supplies, TA = 25°C
100
V
= +16.5V
DD
V
= –16.5V
SS
10
ID (ON)
I
(OFF)
1
LEAKAGE CURRENT (n A)
0.1
0.01
25 35 45 55 65 75 85 95 105 115 125
D
I
(OFF)
S
TEMPERATURE (° C)
01532-011
Figure 9. Leakage Current as a Function of Temperature (Leakage Currents
Reduce as the Supply Voltages Reduce)
Rev. C | Page 11 of 20
1.0
0.8
0.6
(mA)
DD
I
0.4
0.2
0
5678910111213 15 1714 16
SUPPLY VOLTAGE (V)
Figure 12. IDD vs. Supply Voltage: Dual or Single Supply, TA = 25°C
01532-014
Page 12
ADG526A/ADG527A
TERMINOLOGY
t
(EN)
RON
Ohmic resistance between Terminal D and Terminal S.
R
Match
ON
Difference between the R
Drift
R
ON
Change in R
(Off)
I
S
vs. temperature.
ON
of any two channels.
ON
Source terminal leakage current when the switch is off.
I
(Off)
D
Drain terminal leakage current when the switch is off.
I
(On)
D
Leakage current that flows from the closed switch into the body.
V
(VD)
S
Analog voltage on Terminal S or Terminal D.
C
(Off)
S
Channel input capacitance for off condition.
C
(Off)
D
Channel output capacitance for off condition.
C
IN
Digital input capacitance.
t
(EN)
ON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
OFF
Delay time between the 50% and 10% points of the digital input
and switch off condition.
t
TRANSITION
Delay time between the 50% and 90% points of the digital
inputs and switch on condition when switching from one
address state to another.
t
OPEN
Off time measured between 50% points of both switches when
switching from one address state to another.
V
INL
Maximum input voltage for Logic 0.
V
INH
Minimum input voltage for Logic 1.
I
(I
)
INL
INH
Input current of the digital input.
V
DD
Most positive voltage supply.
V
SS
Most negative voltage supply.
I
DD
Positive supply current.
I
SS
Negative supply current.
Rev. C | Page 12 of 20
Page 13
ADG526A/ADG527A
V
V
O
TIMING
Figure 13 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while
WR
is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of
WR
.
Figure 14 shows the reset pulse width, tRS, and reset turn-off
OFF
(RS).
time, t
Note that all digital input signal rise and fall times are measured
from 10% to 90% of 3 V, t
= tF = 20 ns.
R
WR
EN, A0, A1,
A2, (A3)
3
0V
3V
0V
1.5V
2.0V
t
W
Figure 13. Timing Sequence
t
S
t
H
0.8V
01532-003
RS
SWITCH
UTPUT
3
0V
V
O
0V
1.5V
t
RS
t
(RS)
OFF
0.8V
01532-004
Figure 14. Reset Pulse
Rev. C | Page 13 of 20
Page 14
ADG526A/ADG527A
V
VDDV
V
VDDV
VDDV
V
TEST CIRCUITS
I
I
(OFF)
S
S
DS
V1
SD
RON =
Figure 15. R
V
DD
V
DD
A
V2V1
Figure 16. I
SS
V1
I
DS
ON
GND
(Off )
S
V
V1
1532-015
V
SS
V
SS
D
EN
0.8V
01532-016
1
I
= IDA (OFF) – IDB (OFF)
DIFF
SS
V
DD
SS
EN
GND
Figure 18. ID (On)
SS
V
V
DD
SS
ADG527A
GND
Figure 19. I
EN
D
ID (ON)
A
2.4V
V2
01532-018
0.8V
DA
A
DB
A
V2
01532-019
DIFF
V
V
DD
SS
D
1
GND
Figure 17. I
(Off )
D
0.8V
EN
(OFF)
I
A
D
V2
01532-017
Rev. C | Page 14 of 20
Page 15
ADG526A/ADG527A
V
V
VDDV
VDDV
VDDV
V0V
SS
V
DDVSS
ADG526A*
A3
A2
A1
A0
EN
RS
TRANSITION
GND
S2 TO S15
S16
WR
S1
D
OUTPUT
1MΩ
V1
V2
35pF
01532-020
t
TRANSITI ON
ADDRESS
DRIVE (V
90%
OUTPUT
)
IN
V
*SIMILAR CO NNECTION F OR ADG527A.
50Ω
IN
2.4V
3
0
50%
t
TRANSITI ON
90%
Figure 20. Switching Time of Multiplexer, t
SS
V
DDVSS
ADG526A*
A3
OPEN
A2
A1
A0
EN
RS
V
3
0
V
t
OPEN
50%
ADDRESS
DRIVE (V
OUTPUT
)
IN
V
*SIMILAR CO NNECTION F OR ADG527A.
50Ω
IN
2.4V
Figure 21. Break-Before-Make Delay, t
S2 TO S15
GND
WR
S1
S16
D
OUTPUT
1kΩ
5V
35pF
1532-021
SS
(EN)
V
DDVSS
RS
ADG526A*
A3
A2
A1
A0
EN
GND
S2 TO S16
WR
S1
D
OUTPUT
1kΩ
5V
35pF
01532-022
3
50%
90%
t
ON
(EN)
ENABLE
DRIVE (V
OUTPUT
t
OFF
(EN)
10%
)
IN
V
IN
*SIMILAR CO NNECTION F OR ADG527A.
Figure 22. Enable Delay, t
50Ω
ON
2.4V
(EN) t
OFF
Rev. C | Page 15 of 20
Page 16
ADG526A/ADG527A
VDDV
VDDV
VDDV
SS
V
DDVSS
ON
(WR)
EN
ADG526A*
A3
A2
A1
A0
RS
WR
GND
V
DDVSS
EN
ADG526A*
A3
A2
A1
A0
WR
RS
GND
S1
S2 TO S16
SS
S1
S2 TO S16
D
D
OUTPUT
1kΩ
OUTPUT
1kΩ
5V
35pF
01532-023
5V
35pF
3V
0V
NOTE:
DEVICE MUST BE RESET PRIOR TO APPLYING WR PULSE.
50%
t
(WR)
ON
(WR)
DRIVE (V
OUTPUT
20%
)
IN
Figure 23. Write Turn-On Time, t
3V
0V
NOTE:
DEVICE WR MUST PULSE L OW PRIOR TO APPLYING RS PULSE.
50%
t
OFF
(RS)
RS DRIVE (V
80%
OUTPUT
)
IN
2.4V
V
V
50Ω
IN
*SIMILAR CO NNECTION F OR ADG527A.
2.4V
50Ω
IN
Figure 24. Reset Turn-Off, t
*SIMILAR CO NNECTION F OR ADG527A.
(RS)
OFF
01532-024
SS
V
V
DD
SS
ADG526A*
A3
50Ω
A2
A1
A0
S1
EN
3V
V
IN
0V
V
O
Q
= CL × ΔV
INJ
ΔV
O
O
R
S
V
S
V
IN
*SIMILAR CO NNECTION FOR ADG527A.
GND
RS
D
WR
C
1nF
2.4V
L
V
O
01532-025
Figure 25. Charge Injection
Rev. C | Page 16 of 20
Page 17
ADG526A/ADG527A
OUTLINE DIMENSIONS
0.005 (0.13)
MIN
28
114
PIN 1
0.225(5.72)
MAX
0.200 (5.08)
0.125 (3.18)
0.026 (0.66)
0.014 (0.36)
1.490 (37.85) MAX
CONTROLL ING DIMENS IONS ARE IN INCHES; MILLIMETER DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OF F INCH EQUI VALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
Figure 26. 28-Lead Ceramic Dual In-Line Package [CERDIP]
28
114
0.100 (2.54)
0.250 (6.35)
0.200 (5.08)
0.115 (2.92)
0.022 (0.56)
0.014 (0.36)
MAX
BSC
0.070 (1.78)
0.050 (1.27)
0.100 (2.54)
MAX
15
0.610 (15.49)
0.500 (12.70)
0.015 (0.38)
MIN
0.150 (3.81)
MIN
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
(Q-28)
Dimensions shown in inches and (millimeters)
1.565 (39.75)
1.380 (35.05)
15
0.580 (14.73)
0.485 (12.31)
0.015 (0.38)
GAUGE
PLANE
0.015
(0.38)
MIN
SEATING
PLANE
0.005 (0.13)
MIN
15°
0°
0.625 (15.88)
0.600 (15.24)
0.620 (15.75)
0.590 (14.99)
0.700 (17.78)
MAX
0.018 (0.46)
0.008 (0.20)
0.195 (4.95)
0.125 (3.17)
0.015 (0.38)
0.008 (0.20)
030106-A
CONTROLL ING DIMENSIONS ARE IN INCHES; MIL LIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF INCH EQ UIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
CORNER LEADS M AY BE CONFIGURED AS WHOLE LEADS.
COMPLIANT TO JEDEC STANDARDS MS-011
071006-A
Figure 27. 28-Lead Plastic Dual In-Line Package [PDIP]
(N-28)
Dimensions shown in inches and (millimeters)
Rev. C | Page 17 of 20
Page 18
ADG526A/ADG527A
0.048 (1.22)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
4
5
11
12
0.456 (11.582)
0.450 (11.430)
0.495 (12.57)
0.485 (12.32)
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
CONTROLL ING DIMENS IONS ARE IN I NCHES; MILL IMETER DI MENSIONS
(IN PARENTHESES ) ARE ROUNDED-OF F INCH EQUI VALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FO R USE IN DESIGN.
0.056 (1.42)
0.042 (1.07)
26
25
0.050
(1.27)
BSC
19
18
SQ
SQ
COMPLIANT TO JEDEC STANDARDS MO-047-AB
0.120 (3.04)
0.090 (2.29)
0.180 (4.57)
0.165 (4.19)
0.020 (0.51)
MIN
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
0.026 (0.66)
0.045 (1.14)
0.025 (0.64)
0.430 (10.92)
0.390 (9.91)
R
BOTTOM
VIEW
(PINS UP)
042508-A
Figure 28. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28A)
Dimensions shown in inches and (millimeters)
18.10 (0.7126)
17.70 (0.6969)
28
1
15
7.60 (0.2992)
7.40 (0.2913)
14
10.65 (0.4193)
10.00 (0.3937)
9
5
7
5
2
5
(
0
.
0
2
(
0
.
0
0
)
45°
9
8
)
1.27 (0.0500)
0.40 (0.0157)
060706-A
0.30 (0.0118)
0.10 (0.0039)
COPLANARIT Y
0.10
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMET ER EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
0.51 (0.0201)
0.31 (0.0122)
COMPLIANT TO JEDEC STANDARDS MS-013-AE
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
0
.
.
0
Figure 29. 28-Lead Standard Small Outline Package [SOIC] Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
Rev. C | Page 18 of 20
Page 19
ADG526A/ADG527A
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG526AKN −40°C to +85°C 28-Lead PDIP N-28
ADG526AKNZ
ADG526AKR −40°C to +85°C 28-Lead SOIC RW-28
ADG526AKR-REEL −40°C to +85°C 28-Lead SOIC RW-28
ADG526AKRZ1 −40°C to +85°C 28-Lead SOIC RW-28
ADG526AKRZ-REEL
ADG526AKP −40°C to +85°C 28-Lead PLCC P-28A
ADG526AKP-REEL −40°C to +85°C 28-Lead PLCC P-28A
ADG526AKPZ1 −40°C to +85°C 28-Lead PLCC P-28A
ADG526AKPZ-REEL1 −40°C to +85°C 28-Lead PLCC P-28A
ADG526ATQ −55°C to +125°C 28-Lead CERDIP Q-28
ADG526ABQ −40°C to +85°C 28-Lead CERDIP Q-28
ADG526ATCHIPS DIE
ADG527AKN −40°C to +85°C 28-Lead PDIP N-28
ADG527AKNZ
ADG527AKR −40°C to +85°C 28-Lead SOIC RW-28
ADG527AKR-REEL −40°C to +85°C 28-Lead SOIC RW-28
ADG527AKRZ
ADG527AKP −40°C to +85°C 28-Lead PLCC P-28A
ADG527AKPZ
1
Z = RoHS Compliant Part, # denotes RoHS complaint product, may be top or bottom marked.
1
1
−40°C to +85°C 28-Lead SOIC RW-28
1
−40°C to +85°C 28-Lead PDIP N-28
1
−40°C to +85°C 28-Lead SOIC RW-28
1
−40°C to +85°C 28-Lead PLCC P-28A
−40°C to +85°C 28-Lead PDIP N-28
Rev. C | Page 19 of 20
Page 20
ADG526A/ADG527A
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01532-0-6/08(C)
Rev. C | Page 20 of 20
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