Analog Devices ADG526AKP, ADG526AKN, ADG526ABQ, ADG527AKR, ADG527AKP Datasheet
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CMOS Latched
a
FEATURES
44 V Supply Maximum Rating
to VDD Analog Signal Range
V
SS
Single/Dual Supply Specifications
Wide Supply Ranges (10.8 V to 16.5 V)
Microprocessor Compatible (100 ns WR Pulse)
Extended Plastic Temperature Range (–40ⴗC to +85ⴗC)
Low Leakage (20 pA Typ)
Low Power Dissipation (28 mW Max)
Available in DIP, SOIC, PLCC, and LCCC Packages
Superior Alternative to: DG526, DG527
GENERAL DESCRIPTION
8-/16-Channel Analog Multiplexers
The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 channels and dual 8 channels respectively.
On-chip latches facilitate microprocessor interfacing. The
ADG526A switches one of 16 inputs to a common output
depending on the state of four binary addresses and an enable
input. The ADG527A switches one of eight differential inputs
to a common differential output depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic compatible digital inputs.
The ADG526A and ADG527A are designed on an enhanced
LC2MOS process which gives an increased signal capability of
to VDD and enables operation over a wide range of supply
V
SS
voltages. The devices can comfortably operate anywhere in the
10.8 V to 16.5 V single or dual supply range. These multiplexers also feature high switching speeds and low R
ON
.
ADG526A/ADG527A
FUNCTIONAL BLOCK DIAGRAM
ADG526A
S1
S16
WR
PRODUCT HIGHLIGHTS
DECODER/
LATCHES
A0
A1 A2 A3 EN
S1A
S8A
D
S1B
S8B
WR
RS
1. Single/Dual Supply Specifications with a Wide Tolerance:
The devices are specified in the 10.8 V to 16.5 V range for
both single and dual supplies.
2. Easily Interfaced: The ADG526A and ADG527A can be
easily interfaced with microprocessors. The WR signal latches
the state of the Address control lines and the Enable line.
The RS signal clears both the address and enable data in the
latches resulting in no output (all switches off). RS can be
tied to the microprocessor reset pin.
3. Extended Signal Range: The enhanced LC
results in a high breakdown and an increased analog signal
range of V
to VDD.
SS
4. Break-Before-Make Switching: Switches are guaranteed
break-before-make so that input signals are protected against
momentary shorting.
5. Low Leakage: Leakage currents in the range of 20 pA make
these multiplexers suitable for high precision circuits.
ADG527A
DECODER/
LATCHES
A0 A1 A2 EN
2
MOS processing
DA
DB
RS
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
ADG526A/ADG527A–SPECIFICATIONS
Dual Supply
Parameter 25ⴗC +85ⴗC25°C+85ⴗC25ⴗC +125ⴗC Unit Comments
ANALOG
Analog Signal Range V
R
R
R
I
I
I
I
DIGITAL CONTROL
V
V
I
CIN Digital Input Capacitance 8 8 8 pF max
DYNAMIC CHARACTERISTICS*
t
t
t
t
t
t
t
t
OFF Isolation 68 68 68 dB typ V
C
C
Q
POWER SUPPLY
I
I
Power Dissipation 10 10 10 mW typ
*Sample tested at 25ⴗC to ensure compliance.
Specifications subject to change without notice.
SWITCH
ON
Drift 0.6 0.6 0.6 %/°C typ –10 V ≤ VS ≤ +10 V, IDS = 1 mA
ON
Match 555% typ–10 V ≤ VS ≤ +10 V, IDS = 1 mA
ON
(OFF), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = ±10 V, V2 = ⴟ10 V; Test Circuit 2
S
(OFF), Off Output Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = ⴟ10 V, Test Circuit 3
D
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
(ON), On Channel Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = ⴟ10 V; Test Circuit 4
D
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
, Differential Off Output
DIFF
Leakage (ADG527A Only) 25 25 nA max V1 = ±10 V, V2 = ⴟ10 V; Test Circuit 5
, Input High Voltage 2.4 2.4 2.4 V min
INH
, Input Low Voltage 0.8 0.8 0.8 V max
INL
or I
INL
INH
TRANSITION
OPEN
(EN, WR) 200 200 200 ns typ Test Circuit 8 and 9
ON
(EN, RS) 200 200 200 ns typ Test Circuit 8 and 10
OFF
Write Pulsewidth 100 120 100 120 100 130 ns min See Figure 1
W
Address Enable Setup Time 100 100 100 ns min See Figure 1
S
Address Enable Hold Time 10 10 10 ns min See Figure 1
H
Reset Pulsewidth 100 100 100 ns min See Figure 2
RS
(OFF) 555pF typV
S
(OFF)
D
ADG526A 44 44 44 pF typ V
ADG527A 22 22 pF typ
, Charge Injection 444pC typR
INJ
DD
SS
(VDD = +10.8 V to +16.5 V, VSS = –1O.8 V to –16.5 V unless otherwise noted.)
ADG526A/ADG527A ADG526A
K Version B Version T Version
–40ⴗC to –40ⴗC to –55ⴗC to
V
SSVSS
V
DDVDD
SS
V
DDVDD
V
SS
280 280 280 Ω typ –10 V ≤ VS ≤ +10 V, IDS = 1 mA;
450 600 450 600 450 600 Ω max
300 400 300 400 Ω max V
1 50 1 50 1 50 nA max
111µA max VIN = 0 to V
200 200 200 ns typ V1 = ± 10 V, V2 = ⴟ10 V; Test Circuit 6
300 400 300 400 300 400 ns max
50 50 50 ns typ Test Circuit 7
25 10 25 10 25 10 ns min
300 400 300 400 300 400 ns max
300 400 300 400 300 400 ns max
50 50 50 dB min V
0.6 0.6 0.6 mA typ VIN = V
1.5 1.5 1.5 mA max
20 20 20 µA typ VIN = V
0.2 0.2 0.2 mA max
28 28 28 mW max
V
SSVSS
V
DDVDD
V min
V max
300 400 Ω max V
Test Circuit 1
= 15 V (± 10%), VSS = –15 V (± 10%)
DD
= 15 V (± 5%), VSS = –15 V (± 5%)
DD
DD
= 0.8 V, RL = 1 kΩ, CL = 15 pF,
EN
= 7 V rms, f = 100 kHz
V
S
= 7 V rms, f = 100 kHz
S
= 0.8 V
EN
= 0.8 V
EN
= 0 Ω, VS = 0 V; Test Circuit 11
S
or V
INL
INH
or V
INL
INH
–2–
REV. B
ADG526A/ADG527A
Single Supply
(VDD = 10.8 V to 16.5 V, VSS = GND to 0 V unless otherwise noted.)
ADG526A/ADG527A ADG526A
K Version B Version T Version
–40ⴗC to –40ⴗC to –55ⴗC to
Parameter 25ⴗC +85ⴗC25°C +85ⴗC25ⴗC +125ⴗC Unit Comments
ANALOG SWITCH
Analog Signal Range V
R
ON
SSVSS
V
DDVDD
SS
V
DDVDD
V
SS
500 500 500 Ω typ 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA;
V
SS
V
DDVDD
V
SS
V min
V max
V
Test Circuit 1
700 1000 700 1000 700 1000 Ω max
Drift 0.6 0.6 0.6 %/°C typ 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA
R
ON
Match 555% typ0 V ≤ VS ≤ 10 V, IDS = 0.5 mA
R
ON
(OFF), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = 10 V/0 V, V2 = 0 V/10 V;
I
S
Test Circuit 2
1 50 1 50 1 50 nA max
(OFF), Off Output Leakage 0.04 0.04 0.04 nA typ V1 = 10 V/0 V, V2 = 0 V/10 V;
I
D
Test Circuit 3
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
(ON), On Channel Leakage 0.04 0.04 0.04 nA typ V1 = 10 V/0 V, V2 = 0 V/10 V;
I
D
Test Circuit 4
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max
, Differential Off Output
I
DIFF
Leakage (ADG527A only) 25 25 nA max V1 = 10 V/0 V, V2 = 0 V/10 V;
Test Circuit 5
DIGITAL CONTROL
Input High Voltage 2.4 2.4 2.4 V min
V
INH,
, Input Low Voltage 0.8 0.8 0.8 V max
V
INL
I
INL
or I
INH
111µA max VIN = 0 to V
DD
CIN Digital Input Capacitance 8 8 8 pF max
DYNAMIC CHARACTERISTICS*
t
TRANSITION
300 300 300 ns typ V1 = 10 V/0 V, V2 = 0 V/10 V;
450 600 450 600 450 600 ns max Test Circuit 6
t
OPEN
50 50 50 ns typ Test Circuit 7
25 10 25 10 25 10 ns min
(EN, WR) 250 250 250 ns typ Test Circuits 8 and 9
t
ON
450 600 450 600 450 600 ns max
(EN, RS) 250 250 250 ns typ Test Circuits 8 and 10
t
OFF
450 600 450 600 450 600 ns max
Write Pulsewidth 100 120 100 120 100 130 ns min See Figure 1
t
W
Address Enable Setup Time 100 100 100 ns min See Figure 1
t
S
Address Enable Hold Time 10 10 10 ns min See Figure 1
t
H
Reset Pulsewidth 100 100 100 ns min See Figure 2
t
RS
OFF Isolation 68 68 68 dB typ V
50 50 50 dB min V
(OFF) 555pF typV
C
S
(OFF)
C
D
ADG526A 44 44 44 pF typ V
= 0.8 V, RL = 1 kΩ, CL = 15 pF
EN
= 3.5 V rms, f = 100 kHz
S
= 0.8 V
EN
= 0.8 V
EN
ADG527A 22 22 pF typ
Q
, Charge Injection 444pC typR
INJ
= 0 Ω, VS = 0 V; Test Circuit 11
S
POWER SUPPLY
I
DD
0.6 0.6 0.6 mA typ VIN = V
INL
or V
INH
1.5 1.5 1.5 mA max
Power Dissipation 11 11 11 mW typ
25 25 25 mW max
*Sample tested at 25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
–3–
ADG526A/ADG527A
WARNING!
ESD SENSITIVE DEVICE
TIMING DIAGRAMS
3V
WR
0V
3V
EN A0, A1, A2, (A3)
0V
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level-sensitive; therefore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
1.5V
2.0V
Figure 1.
t
W
t
S
0.8V
t
H
3V
RS
SWITCH
OUTPUT
0V
V
O
0V
1.5V
t
RS
t
(RS)
OFF
0.8V
O
Figure 2.
Figure 2 shows the Reset Pulsewidth, tRS, and Reset Turn-off
Time, t
OFF
(RS).
Note: All digital input signals rise and fall times measured from
10% to 90% of 3 V, t
= tF = 20 ns.
R
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted.)
1
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
V
SS
Analog Inputs
2
Voltage at S, D . . . . . . . . . . . . . . . . VSS – 2 V to VDD +2 V
. . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA
Digital Inputs
2
Voltage at A, EN, WR, RS . . . . . . . . . VSS – 4 V to VDD +4 V
. . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First
Power Dissipation (Any Package)
Up to 75°C by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40°C to +85°C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.
2
Overvoltage at A, EN, WR, RS, S, or D will be clamped by diodes. Current should
be limited to the maximum rating above.
ORDERING GUIDE
1
Model
Temperature Range Package Option
ADG526AKN –40°C to +85°C N-28
ADG526AKR –40°C to +85°C R-28
ADG526AKP –40°C to +85°C P-28A
ADG526ABQ –40°C to +85°CQ-28
ADG526ATQ
ADG526ATE
3
–55°C to +125°CQ-28
3
–55°C to +125°C E-28A
ADG527AKN –40°C to +85°C N-28
ADG527AKR –40°C to +85°C R-28
ADG527AKP –40°C to +85°C P-28A
ADG527ABQ –40°C to +85°CQ-28
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
See Analog Devices Military Products Databook (1990) for military data.
2
E = Leadless Ceramic Chip Carrier; N = Narrow Plastic DIP; P = Plastic
Leaded Chip Carrier; Q = CERDIP; R = 0.3" Small Outline IC (SOIC).
3
Standard Military Drawing (SMD) assigned by DESC. SMD numbers are:
5962-89710013X (ADG526ATE/883B)
5962-8971001XX (ADG526ATQ/883B)
2
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG526A/ADG527A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
REV. B
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