Datasheet ADG526AKP, ADG526AKN, ADG526ABQ, ADG527AKR, ADG527AKP Datasheet (Analog Devices)

CMOS Latched

a

FEATURES
44 V Supply Maximum Rating

to VDD Analog Signal Range

V

SS

Single/Dual Supply Specifications
Wide Supply Ranges (10.8 V to 16.5 V)
Microprocessor Compatible (100 ns WR Pulse)
Extended Plastic Temperature Range (–40ⴗC to +85ⴗC)
Low Leakage (20 pA Typ)
Low Power Dissipation (28 mW Max)
Available in DIP, SOIC, PLCC, and LCCC Packages
Superior Alternative to: DG526, DG527

GENERAL DESCRIPTION

8-/16-Channel Analog Multiplexers

The ADG526A and ADG527A are CMOS monolithic analog
multiplexers with 16 channels and dual 8 channels respectively.
On-chip latches facilitate microprocessor interfacing. The
ADG526A switches one of 16 inputs to a common output
depending on the state of four binary addresses and an enable
input. The ADG527A switches one of eight differential inputs
to a common differential output depending on the state of three
binary addresses and an enable input. Both devices have TTL
and 5 V CMOS logic compatible digital inputs.

The ADG526A and ADG527A are designed on an enhanced
LC2MOS process which gives an increased signal capability of

to VDD and enables operation over a wide range of supply

V

SS

voltages. The devices can comfortably operate anywhere in the

10.8 V to 16.5 V single or dual supply range. These multiplex­ers also feature high switching speeds and low R

ON

.

ADG526A/ADG527A

FUNCTIONAL BLOCK DIAGRAM

ADG526A

S1

S16

WR

PRODUCT HIGHLIGHTS

DECODER/

LATCHES

A0

A1 A2 A3 EN

S1A

S8A

D

S1B

S8B

WR

RS

1. Single/Dual Supply Specifications with a Wide Tolerance:
The devices are specified in the 10.8 V to 16.5 V range for
both single and dual supplies.

2. Easily Interfaced: The ADG526A and ADG527A can be
easily interfaced with microprocessors. The WR signal latches
the state of the Address control lines and the Enable line.
The RS signal clears both the address and enable data in the
latches resulting in no output (all switches off). RS can be
tied to the microprocessor reset pin.

3. Extended Signal Range: The enhanced LC
results in a high breakdown and an increased analog signal
range of V

to VDD.

SS

4. Break-Before-Make Switching: Switches are guaranteed
break-before-make so that input signals are protected against
momentary shorting.

5. Low Leakage: Leakage currents in the range of 20 pA make
these multiplexers suitable for high precision circuits.

ADG527A

DECODER/

LATCHES

A0 A1 A2 EN

2

MOS processing

DA

DB

RS

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

ADG526A/ADG527A–SPECIFICATIONS

Dual Supply

Parameter 25ⴗC +85ⴗC25°C+85ⴗC25ⴗC +125ⴗC Unit Comments

ANALOG

Analog Signal Range V

R

R
R
I

I

I

I

DIGITAL CONTROL

V
V
I
CIN Digital Input Capacitance 8 8 8 pF max

DYNAMIC CHARACTERISTICS*

t

t

t

t

t
t
t
t
OFF Isolation 68 68 68 dB typ V

C
C

Q

POWER SUPPLY

I

I

Power Dissipation 10 10 10 mW typ

*Sample tested at 25ⴗC to ensure compliance.

Specifications subject to change without notice.

SWITCH

ON

Drift 0.6 0.6 0.6 %/°C typ –10 V ≤ VS ≤ +10 V, IDS = 1 mA

ON

Match 555% typ–10 V ≤ VS ≤ +10 V, IDS = 1 mA

ON

(OFF), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = ±10 V, V2 = ⴟ10 V; Test Circuit 2

S

(OFF), Off Output Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = ⴟ10 V, Test Circuit 3

D

ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max

(ON), On Channel Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = ⴟ10 V; Test Circuit 4

D

ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max

, Differential Off Output

DIFF

Leakage (ADG527A Only) 25 25 nA max V1 = ±10 V, V2 = ⴟ10 V; Test Circuit 5

, Input High Voltage 2.4 2.4 2.4 V min

INH

, Input Low Voltage 0.8 0.8 0.8 V max

INL

or I

INL

INH

TRANSITION

OPEN

(EN, WR) 200 200 200 ns typ Test Circuit 8 and 9

ON

(EN, RS) 200 200 200 ns typ Test Circuit 8 and 10

OFF

Write Pulsewidth 100 120 100 120 100 130 ns min See Figure 1

W

Address Enable Setup Time 100 100 100 ns min See Figure 1

S

Address Enable Hold Time 10 10 10 ns min See Figure 1

H

Reset Pulsewidth 100 100 100 ns min See Figure 2

RS

(OFF) 555pF typV

S

(OFF)

D

ADG526A 44 44 44 pF typ V
ADG527A 22 22 pF typ

, Charge Injection 444pC typR

INJ

DD

SS

(VDD = +10.8 V to +16.5 V, VSS = –1O.8 V to –16.5 V unless otherwise noted.)

ADG526A/ADG527A ADG526A

K Version B Version T Version

–40ⴗC to –40ⴗC to –55ⴗC to

V

SSVSS

V

DDVDD

SS

V

DDVDD

V

SS

280 280 280 Ω typ –10 V ≤ VS ≤ +10 V, IDS = 1 mA;

450 600 450 600 450 600 Ω max
300 400 300 400 Ω max V

1 50 1 50 1 50 nA max

111µA max VIN = 0 to V

200 200 200 ns typ V1 = ± 10 V, V2 = ⴟ10 V; Test Circuit 6
300 400 300 400 300 400 ns max
50 50 50 ns typ Test Circuit 7
25 10 25 10 25 10 ns min

300 400 300 400 300 400 ns max

300 400 300 400 300 400 ns max

50 50 50 dB min V

0.6 0.6 0.6 mA typ VIN = V

1.5 1.5 1.5 mA max

20 20 20 µA typ VIN = V

0.2 0.2 0.2 mA max

28 28 28 mW max

V

SSVSS

V

DDVDD

V min
V max

300 400 Ω max V

Test Circuit 1

= 15 V (± 10%), VSS = –15 V (± 10%)

DD

= 15 V (± 5%), VSS = –15 V (± 5%)

DD

DD

= 0.8 V, RL = 1 kΩ, CL = 15 pF,

EN

= 7 V rms, f = 100 kHz

V

S

= 7 V rms, f = 100 kHz

S

= 0.8 V

EN

= 0.8 V

EN

= 0 Ω, VS = 0 V; Test Circuit 11

S

or V

INL

INH

or V

INL

INH

–2–

REV. B

ADG526A/ADG527A

Single Supply

(VDD = 10.8 V to 16.5 V, VSS = GND to 0 V unless otherwise noted.)

ADG526A/ADG527A ADG526A

K Version B Version T Version

–40ⴗC to –40ⴗC to –55ⴗC to

Parameter 25ⴗC +85ⴗC25°C +85ⴗC25ⴗC +125ⴗC Unit Comments

ANALOG SWITCH

Analog Signal Range V

R

ON

SSVSS

V

DDVDD

SS

V

DDVDD

V

SS

500 500 500 Ω typ 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA;

V

SS

V

DDVDD

V

SS

V min
V max

V

Test Circuit 1

700 1000 700 1000 700 1000 Ω max

Drift 0.6 0.6 0.6 %/°C typ 0 V ≤ VS ≤ 10 V, IDS = 0.5 mA

R

ON

Match 555% typ0 V ≤ VS ≤ 10 V, IDS = 0.5 mA

R

ON

(OFF), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = 10 V/0 V, V2 = 0 V/10 V;

I

S

Test Circuit 2

1 50 1 50 1 50 nA max

(OFF), Off Output Leakage 0.04 0.04 0.04 nA typ V1 = 10 V/0 V, V2 = 0 V/10 V;

I

D

Test Circuit 3
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max

(ON), On Channel Leakage 0.04 0.04 0.04 nA typ V1 = 10 V/0 V, V2 = 0 V/10 V;

I

D

Test Circuit 4
ADG526A 1 200 1 200 1 200 nA max
ADG527A 1 100 1 100 nA max

, Differential Off Output

I

DIFF

Leakage (ADG527A only) 25 25 nA max V1 = 10 V/0 V, V2 = 0 V/10 V;

Test Circuit 5

DIGITAL CONTROL

Input High Voltage 2.4 2.4 2.4 V min

V

INH,

, Input Low Voltage 0.8 0.8 0.8 V max

V

INL

I

INL

or I

INH

111µA max VIN = 0 to V

DD

CIN Digital Input Capacitance 8 8 8 pF max

DYNAMIC CHARACTERISTICS*

t

TRANSITION

300 300 300 ns typ V1 = 10 V/0 V, V2 = 0 V/10 V;
450 600 450 600 450 600 ns max Test Circuit 6

t

OPEN

50 50 50 ns typ Test Circuit 7
25 10 25 10 25 10 ns min

(EN, WR) 250 250 250 ns typ Test Circuits 8 and 9

t

ON

450 600 450 600 450 600 ns max

(EN, RS) 250 250 250 ns typ Test Circuits 8 and 10

t

OFF

450 600 450 600 450 600 ns max

Write Pulsewidth 100 120 100 120 100 130 ns min See Figure 1

t

W

Address Enable Setup Time 100 100 100 ns min See Figure 1

t

S

Address Enable Hold Time 10 10 10 ns min See Figure 1

t

H

Reset Pulsewidth 100 100 100 ns min See Figure 2

t

RS

OFF Isolation 68 68 68 dB typ V

50 50 50 dB min V

(OFF) 555pF typV

C

S

(OFF)

C

D

ADG526A 44 44 44 pF typ V

= 0.8 V, RL = 1 kΩ, CL = 15 pF

EN

= 3.5 V rms, f = 100 kHz

S

= 0.8 V

EN

= 0.8 V

EN

ADG527A 22 22 pF typ

Q

, Charge Injection 444pC typR

INJ

= 0 Ω, VS = 0 V; Test Circuit 11

S

POWER SUPPLY

I

DD

0.6 0.6 0.6 mA typ VIN = V

INL

or V

INH

1.5 1.5 1.5 mA max

Power Dissipation 11 11 11 mW typ

25 25 25 mW max

*Sample tested at 25°C to ensure compliance.

Specifications subject to change without notice.

REV. B

–3–

ADG526A/ADG527A

WARNING!

ESD SENSITIVE DEVICE

TIMING DIAGRAMS

3V

WR

0V

3V

EN A0, A1, A2, (A3)

0V

Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level-sensitive; there­fore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.

1.5V

2.0V

Figure 1.

t

W

t

S

0.8V

t

H

3V

RS

SWITCH

OUTPUT

0V

V

O

0V

1.5V

t

RS

t

(RS)

OFF

0.8V

O

Figure 2.

Figure 2 shows the Reset Pulsewidth, tRS, and Reset Turn-off
Time, t

OFF

(RS).

Note: All digital input signals rise and fall times measured from
10% to 90% of 3 V, t

= tF = 20 ns.

R

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted.)

1

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V

V

SS

Analog Inputs

2

Voltage at S, D . . . . . . . . . . . . . . . . VSS – 2 V to VDD +2 V

. . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA

Pulsed Current S or D

1 ms Duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA

Digital Inputs

2

Voltage at A, EN, WR, RS . . . . . . . . . VSS – 4 V to VDD +4 V

. . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First

Power Dissipation (Any Package)

Up to 75°C by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature

Commercial (K Version) . . . . . . . . . . . . . . . –40°C to +85°C

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.

2

Overvoltage at A, EN, WR, RS, S, or D will be clamped by diodes. Current should

be limited to the maximum rating above.

ORDERING GUIDE

1

Model

Temperature Range Package Option

ADG526AKN –40°C to +85°C N-28
ADG526AKR –40°C to +85°C R-28
ADG526AKP –40°C to +85°C P-28A
ADG526ABQ –40°C to +85°CQ-28
ADG526ATQ
ADG526ATE

3

–55°C to +125°CQ-28

3

–55°C to +125°C E-28A

ADG527AKN –40°C to +85°C N-28
ADG527AKR –40°C to +85°C R-28
ADG527AKP –40°C to +85°C P-28A
ADG527ABQ –40°C to +85°CQ-28

NOTES

1

To order MIL-STD-883, Class B processed parts, add /883B to part number.
See Analog Devices Military Products Databook (1990) for military data.

2

E = Leadless Ceramic Chip Carrier; N = Narrow Plastic DIP; P = Plastic
Leaded Chip Carrier; Q = CERDIP; R = 0.3" Small Outline IC (SOIC).

3

Standard Military Drawing (SMD) assigned by DESC. SMD numbers are:
5962-89710013X (ADG526ATE/883B)
5962-8971001XX (ADG526ATQ/883B)

2

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG526A/ADG527A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

ADG526A/ADG527A

TRUTH TABLES

ADG526A

A3 A2 Al A0 EN WR RS ON SWITCH

XXXXX g 1 Retains Previous Switch Condition
XXXXX X 0 NONE (Address and Enable Latches Cleared)
XXXX0 0 1 NONE
00001011
00011012
00101013
00111014
01001015
01011016
01101017
01111018
10001019
100110110
101010111
101110112
110010113
110110114
111010115
111110116

X = Don’t Care

ADG527A

A2 Al A0 EN WR RS ON SWITCH PAIR

XXXXg 1 Retains Previous Switch Condition
XXXXX 0 NONE (Address and EnableLatches Cleared)
XXX0 0 1 NONE
00010 1 1
00110 1 2
01010 1 3
01110 1 4
10010 1 5
10110 1 6
11010 1 7
11110 1 8

X = Don’t Care

REV. B

–5–

ADG526A/ADG527A

DIP, SOIC LCCC PLCC

1

V

DD

2

NC

3

RS

4

S16

5

S15

6

S14

ADG526A

7

S13

TOP VIEW

(Not to Scale)

8

S12

9

S11

10

S10

11

S9

12

GND

13

WR

14

A3

NC = NO CONNECT

V

1

DD

2

DB

3

RS

4

S8B

5

S7B

6

S6B

ADG527A

7

S5B

S4B

S3B

S2B

GND

TOP VIEW

(Not to Scale)

8

9

10

11

S1B

12

13

WR

14

NC

NC = NO CONNECT

PIN CONFIGURATIONS

DD

DD

28

D

27

V

SS

26

S8

25

S7

24

S6

23

S5

22

S4

21

S3

20

S2

19

S1

18

EN

17

A0

16

A1

15

A2

28

DA

V

27

SS

26

S8A

25

S7A

24

S6A

23

S5A

22

S4A

21

S3A

20

S2A

19

S1A

18

EN

17

A0

16

A1

15

A2

S15

S14

S13

S12

S11

S10

5

6

7

8

9

10

11

S9

RS

NC

S16

4 3 2 1 28 27 26

ADG526A

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18

A3

WR

GND

NC = NO CONNECT

SS

V

D

V

S8

25

S7

24

S6

23

S5

22

S4

21

S3

20

S2

19

S1

A2

A1

A0

EN

S15

S14

S13

S12

S11

S10

S9

S7B

S6B

S5B

S4B

S3B

S2B

S1B

S16

RS

4 3 2 1 28 27 26

5

6

7

8

9

10

11

NC = NO CONNECT

5

6

7

8

9

10

11

NC = NO CONNECT

ADG526A

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18

A3

WR

GND

S8B

RS

4 3 2 1 28 27 26

ADG527A

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18

NC

WR

GND

NC

DB

SS

V

D

V

S8

25

S7

24

S6

23

S5

22

S4

21

S3

20

S2

19

S1

A2

A1

A0

EN

DD

SS

V

DA

V

S8A

25

S7A

24

S6A

23

S5A

22

S4A

21

S3A

20

S2A

19

S1A

A2

A1

A0

EN

–6–

REV. B

SUPPLY VOLTAGE – V

800

5

t

TRANSITION

– ns

600

400

300

6 7 8 9 10 11 12 13 15

100

14

700

500

200

DUAL
SUPPLY

SINGLE
SUPPLY

Typical Performance Characteristics–

ADG526A/ADG527A

The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.

700

1.9

600

500

400

– ⍀

ON

R

300

200

100

0

–20

–15 –10 –5 0 5 101520

VD (VS) – V

V
V

DD

SS

= 10.8V
= 0V

VDD = 15V
V

= 0V

SS

TPC 1. RON as a Function of VD (VS): Dual Supply Voltage,
T

= 25°C

A

700

600

500

400

– ⍀

ON

R

300

VDD = +10.8V

= –10.8V

V

SS

V

= +5V

DD

= –5V

V

SS

1.8

1.7

TRIGGER LEVEL – V

1.6

1.5
6 7 8 9 10 11 12 13 15

5

SUPPLY VOLTAGE – V

14

TPC 4. Trigger Levels vs. Power Supply Voltage, Dual or
Single Supply, T

= 25°C

A

200

100

0

–20

VDD = +15V

= –15V

V

SS

–15 –10 –5 0 5 101520

VD (VS) – V

TPC 2. RON as a Function of VD (VS); Single Supply
Voltage, T

100

10

LEAKAGE CURRENT – nA

0.1

TPC 3. Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply

= 25°C

A

VDD = +16.5V

= –16.5V

V

SS

(ON)

I

D

I

(OFF)

D

1

35 45 55 65 75 85 95 105

25

TEMPERATURE – ⴗC

IS (OFF)

115 125

Voltages Reduce)

REV. B

TPC 5. t
Supplies, T
V1 = V

T
T

–7–

1.0

0.8

0.6

– mA

DD

I

0.4

0.2

PC 6. I

= 25°C

A

TRANSITION

DD/VSS

5

DD

vs. Supply Voltage: Dual and Single

= 25°C (Note: For VDD and / VSS/ <10 V;

A

, V2 = VSS/VDD; See Test Circuit 6)

6 7 8 9 10 11 12 13 16

SUPPLY VOLTAGE – V

14

15 17

vs. Supply Voltage: Dual or Single Supply,

ADG526A/ADG527A

SD

V

S

Test Circuit 1. R

A

(OFF)

I

S

V2V1

–Test Circuits

I

DS

V1

V1

RON =

I

DS

ON

V

V

DD

SS

V

V

DD

SS

D

0.8V

EN

GND

V

V

DD

SS

V

DDVSS

EN

V1

GND

Test Circuit 4. ID (ON)

V

DD

V

DD

ADG527A

V1

GND

D

I

(ON)

A

2.4V

V

SS

V

SS

EN

DA

DB

D

V2

0.8V

A

A

V2

Test Circuit 2. IS (OFF)

V

V

DD

SS

V

V

DD

SS

EN

V1

GND

Test Circuit 3. ID (OFF)

3V

0V

50%

D

0.8V

90%

I

A

(OFF)

D

V2

ADDRESS
DRIVE (V

90%

OUTPUT

= IDA (OFF) – I

I

DIFF

Test Circuit 5. I

V

V

DD

SS

V

V

DD

SS

A3

)

IN

V

50⍀

IN

A2

A1

A0

S2 THRU S15

ADG526A*

2.4V

EN

RS

GND

S1

S16

D

WR

OUTPUT

1M⍀

(OFF)

DB

DIFF

V1

V2

35pF

t

TRANSITION

t

TRANSITION

*SIMILAR CONNECTION FOR ADG527A

Test Circuit 6. Switching Time of Multiplexer, t

–8–

TRANSITION

REV. B

ADG526A/ADG527A

V

V

DD

SS

V

V

DD

SS

3V

0V

t

OPEN

50%

ADDRESS
DRIVE (V

OUTPUT

)

IN

V

IN

50⍀

A3

A2

A1

A0

ADG526A*

2.4V

*SIMILAR CONNECTION FOR ADG527A

EN

RS

Test Circuit 7. Break-Before-Make Delay, t

S2 THRU S15

S16

GND

WR

V

DDVSS

S1

D

OPEN

OUTPUT

1k⍀

5V

35pF

3V

50%

0V

90%

t

ON

(EN)

ENABLE
DRIVE (VIN)

OUTPUT

10%

t

OFF

(EN)

V

2.4V

IN

50⍀

*SIMILAR CONNECTION FOR ADG527A

Test Circuit 8. Enable Delay, tON (EN), t

V

2.4V

)

IN

50⍀

IN

20%

(WR)
DRIVE (V

OUTPUT

V

3V

50%

0V

t

ON

(WR)

V

EN
A3

A2

A1

A0

ADG526A*

RS

WR

RS

A3

A2

A1

A0

EN

DD

DD

S2 THRU S16

GND

V

DDVSS

S2 THRU S16

ADG526A*

GND

(EN)

OFF

V

SS

V

SS

S1

OUTPUT

D

WR

S1

1k⍀

D

5V

5V

OUTPUT

1k⍀

35pF

35pF

REV. B

NOTE
DEVICE MUST BE RESET PRIOR TO
APPLYING WR PULSE

Test Circuit 9. Write Turn-On Time, tON (WR)

*SIMILAR CONNECTION FOR ADG527A

–9–

ADG526A/ADG527A

V

DDVSS

V

V

DD

2.4V

3V

50%

0V

t

OFF

(RS)

RS DRIVE (V

80%
OUTPUT

)

IN

V

50⍀

IN

EN

A3

A2

A1

A0

ADG526A*

WR

RS

SS

S2 THRU S16

GND

S1

D

OUTPUT

1k⍀

5V

35pF

NOTE
DEVICE WR MUST PULSED LOW
PRIOR TO APPLYING RS PULSE

Test Circuit 10. Reset Turn-Off Time, t

3V

V

IN

0V

V

O

Q

= CL ⴛ ⌬V

INJ

⌬V

O

O

V

S

*SIMILAR CONNECTION FOR ADG527A

V

DD

V

DD

A0

A1

A2

ADG526A*

A3

S1

R

S

V

IN

*SIMILAR CONNECTION FOR ADG527A

50⍀

EN

GND

V

V

WR

(RS)

OFF

SS

SS

RS

2.4V

D

V

C
1nF

L

O

Test Circuit 11. Charge Injection

TERMINOLOGY

R

ON

R

Match Difference between the RON of any two channels

ON

Drift Change in RON versus temperature

R

ON

I

(OFF) Source terminal leakage current when the switch is off

S

I

(OFF) Drain terminal leakage current when the switch is off

D

(ON) Leakage current that flows from the closed switch into the body

I

D

V

(VD) Analog voltage on terminal S or D

S

C

(OFF) Channel input capacitance for “OFF’ condition

S

(OFF) Channel output capacitance for “OFF” condition

C

D

C

IN

t

(EN) Delay time between the 50% and 90% points of the digital input and switch “ON” condition

ON

(EN) Delay time between the 50% and 10% points of the digital input and switch “OFF” condition

t

OFF

t

TRANSITION

Ohmic resistance between terminals D and S

Digital input capacitance

Delay time between the 50% and 90% points of the digital inputs
and switch “ON” condition when switching from one address state to another

t

OPEN

“OFF” time measured between 50% points of both switches when switching from one address

state to another
V
V
I
V
V
I
I

INL

INH

INL

DD

SS

DD

SS

(I

INH

Maximum input voltage for Logic “0”

Minimum input voltage for Logic “1”

) Input current of the digital input

Most positive voltage supply

Most negative voltage supply

Positive supply current

Negative supply current

–10–

REV. B

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

ADG526A/ADG527A

28-Lead Plastic DIP (Suffix N)

(N-28)

1.450 (36.830)

1.440 (35.580)

PIN 1

0.200

(5.080)

MAX

SEATING

PLANE

28

1

0.020 (0.508)

0.015 (0.381)

0.105 (2.670)

0.096 (2.420)

15

0.550 (13.970)

0.530 (13.470)

14

0.060 (1.580)

0.020 (0.560)

0.175 (4.450)

0.120 (3.050)

0.606 (15.400)

0.594 (15.090)

15ⴗ

0.012 (0.306)

0ⴗ

0.008 (0.203)

28-Terminal Leadless Ceramic Chip Carrier (Suffix E)

(E-28A)

0.300 (7.62)

0.100 (2.54)

0.064 (1.63)

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075
(1.91)

REF

0.055 (1.40)

0.045 (1.14)

0.075

(1.91)

REF

BSC

0.150

(3.51)

25

28

1

BOTTOM

VIEW

BSC

26

19

18

0.200
(5.08)
BSC

4

5

11

12

0.015 (0.38)
MIN

0.028 (0.71)

0.022 (0.56)

0.050
(1.27)
BSC

45ⴗ TYP

28-Lead Cerdip (Suffix Q)

(Q-28)

1.49 (37.84) MAX

PIN 1

0.22

(5.59)

MAX

28

114

GLASS

SEALANT

0.11 (2.79)

0.099 (2.28)

0.02 (0.5)

0.016 (0.406)

0.06 (1.52)

0.05 (1.27)

15

0.525 (13.33)

0.515 (13.08)

0.125

(3.175)

MIN

0.62 (15.74)

0.59 (14.93)

15°

0°

0.012 (0.305)

0.008 (0.203)

28-Terminal Plastic Leaded Chip Carrier (Suffix P)

(P-28A)

0.180 (4.57)

0.050
(1.27)
BSC

0.165 (4.19)

0.110 (2.79)

0.085 (2.16)

0.025 (0.63)

0.015 (0.38)

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.040 (1.01)

0.025 (0.64)

0.430 (10.92)

0.048 (1.21)

0.042 (1.07)

0.020

(0.50)

0.048 (1.21)

0.042 (1.07)

4

5

11

12

0.456 (11.58)

R

0.450 (11.43)

0.495 (12.57)

0.485 (12.32)

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.056 (1.42)

0.042 (1.07)

26

25

19

18

SQ

SQ

0.18 (4.57)
MAX

0.390 (9.91)

REV. B

28-Lead SOIC (R) Package

0.512 (13.00)

0.496 (12.60)

28 15

1

0.0500

0.012 (0.3)

0.004 (0.1)

(1.27)

BSC

0.019 (0.49)

0.014 (0.35)

(R-28)

14

0.104 (2.65)

0.093 (2.35)

–11–

0.300 (7.60)

0.292 (7.40)

0.419 (10.65)

0.319 (10.00)

0.013 (0.32)

0.009 (0.23)

0.005 (1.27)

0.016 (0.40)

ADG526A/ADG527A

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Edits to Specifications Table, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to Specifications Table, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Removal of one PIN CONFIGURATION and diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

C01532–0–2/02(B)

–12–

PRINTED IN U.S.A.

REV. B