4.5 pF off source capacitance
10 pF off drain capacitance
−0.6 pC charge injection
Low on resistance: 160 Ω typical
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
V
to VSS analog signal range
DD
Human body model (HBM) ESD rating
4 kV I/O port to supplies
1 kV I/O port to I/O port
4 kV all other pins
APPLICATIONS
Automatic test equipment
Data acquisition
Instrumentation
Avio nics
Audio and video switching
Communication systems
Triple/Quad SPDT Switches
ADG5233/ADG5234
FUNCTIONAL BLOCK DIAGRAMS
ADG5233
S1A
D1
S1B
S2B
D2
S2A
LOGIC
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR
A 1 INPUT LO GIC.
Figure 1. ADG5233 TSSOP and LFCSP_VQ
ADG5234
D1
S1B
IN1
IN2
S2B
D2
SWITCHES S HOWN FOR
A 1 INPUT LOG IC.
Figure 2. ADG5234 TSSOP
S3B
D3
S3A
S4A
D4
S4B
IN4
IN3
S3B
D3
S3A
09919-001
09919-002
GENERAL DESCRIPTION
The ADG5233 and ADG5234 are monolithic industrial CMOS
analog switches comprising three independently selectable
single-pole, double throw (SPDT) switches and four independently selectable SPDT switches, respectively.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An
input on the (LFCSP and TSSOP packages) is used to
ADG5233
enable or disable the device. When disabled, all channels are
switched off.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
these devices suitable for video signal switching.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
EN
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors
thereby preventing latch-up even under severe overvoltage
conditions.
2. Ultralow Capacitance and −0.6 pC Charge Injection.
3. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5233/ADG5234 can be operated from dual supplies
up to ±22 V.
4. Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5233/ADG5234 can be operated from a single-rail
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 160 Ω typ VS = ±10 V, IS = −1 mA; see Figure 26
200 250 280 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between
Channels, ∆R
ON
3.5 Ω typ V
8 9 10 Ω max
On-Resistance Flatness, R
38 Ω typ VS = ±10 V, IS = −1 mA
FLAT (ON)
50 65 70 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.02 nA typ
±0.1 ±0.2 ±0.4 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ
±0.1 ±0.2 ±0.4 nA max
Channel On Leakage, ID (On), IS (On) ±0.08 nA typ VS = VD = ±10 V; see Figure 25
±0.2 ±0.3 ±0.9 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0
INH
0.8 V max
INL
or I
0.002 μA typ VIN = V
INH
V min
±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
170 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
210 250 280 ns max VS = 10 V; see Figure 31
tON (EN)
175 ns typ R
215 255 290 ns max VS = 10 V; see Figure 33
t
(EN)
OFF
80 ns typ R
100 115 125 ns max VS = 10 V; see Figure 33
Break-Before-Make Time Delay, tD 60 ns typ RL = 300 Ω, CL = 35 pF
30 ns min VS1 = VS2 = 10 V; see Figure 32
Charge Injection, Q
−0.6 pC typ
INJ
Off Isolation −75 dB typ
Channel-to-Channel Crosstalk −80 dB typ
−3 dB Bandwidth 205 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 30
Insertion Loss −6.3 dB typ
CS (Off) 4.5 pF typ VS = 0 V, f = 1 MHz
CD (Off) 10 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 15 pF typ VS = 0 V, f = 1 MHz
= ±10 V, IS = −1 mA
S
V
= ±10 V, VD = m10 V; see Figure 28
S
V
= ±10 V, VD = m10 V; see Figure 28
S
or VDD
GND
= 300 Ω, CL = 35 pF
L
= 300 Ω, CL = 35 pF
L
= 0 V, RS = 0 Ω, CL = 1 nF; see
V
S
Figure 34
= 50 Ω, CL = 5 pF, f = 1 MHz; see
R
L
Figure 29
= 50 Ω, CL = 5 pF, f = 1 MHz;
R
L
Figure 27
= 50 Ω, CL = 5 pF, f = 1 MHz;
R
L
see Figure 30
Rev. 0 | Page 3 of 24
ADG5233/ADG5234
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 45 μA typ Digital inputs = 0 V or VDD
55 70 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/V max GND = 0 V
1
Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 140 Ω typ VS = ±15 V, IS = −1 mA; see Figure 26
160 200 230 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match Between
Channels, ∆R
ON
3.5 Ω typ V
8 9 10 Ω max
On-Resistance Flatness, R
33 Ω typ VS = ±15 V, IS = −1 mA
FLAT (ON)
45 55 60 Ω max
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V
Source Off Leakage, IS (Off) ±0.02 nA typ
±0.1 ±0.2 ±0.4 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ
±0.1 ±0.2 ±0.4 nA max
Channel On Leakage, ID (On), IS (On) ±0.08 nA typ VS = VD = ±15 V; see Figure 25
±0.2 ±0.3 ±0.9 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.002 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
170 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
200 235 260 ns max VS = 10 V; see Figure 31
tON (EN)
165 ns typ R
200 240 265 ns max VS = 10 V; see Figure 33
t
OFF
(EN)
80 ns typ R
95 105 115 ns max VS = 10 V; see Figure 33
Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF
30 ns min VS1 = VS2 = 10 V; see Figure 32
Charge Injection, Q
0 pC typ
INJ
Off Isolation −75 dB typ
Channel-to-Channel Crosstalk −80 dB typ
−3 dB Bandwidth 210 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 30
Insertion Loss −5.5 dB typ
= ±15 V, IS = −1 mA
S
V
= ±15 V, VD = m15 V; see Figure 28
S
V
= ±15 V, VD = m15 V; see Figure 28
S
or VDD
GND
= 300 Ω, CL = 35 pF
L
= 300 Ω, CL = 35 pF
L
= 0 V, RS = 0 Ω, CL = 1 nF; see
V
S
Figure 34
= 50 Ω, CL = 5 pF, f = 1MHz; see
R
L
Figure 29
= 50 Ω, CL = 5 pF, f = 1 MHz; see
R
L
Figure 27
= 50 Ω, CL = 5 pF, f = 1 MHz;
R
L
see Figure 30
Rev. 0 | Page 4 of 24
ADG5233/ADG5234
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
CS (Off) 4.5 pF typ VS = 0 V, f = 1 MHz
CD (Off) 10 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 15 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +22 V, VSS = −22 V
IDD 50 μA typ Digital inputs = 0 V or VDD
70 110 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/V max GND = 0 V
1
Guaranteed by design; not subject to production test.