Datasheet ADG5212 Datasheet (ANALOG DEVICES)

High Voltage Latch-Up Proof,

3

FEATURES

Latch-up proof
3 pF off source capacitance
5 pF off drain capacitance

0.07 pC charge injection
Low leakage: 0.2 nA maximum at 85ºC
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
V

to VDD analog signal range

SS

APPLICATIONS

Automatic test equipment
Data acquisition
Instrumentation
Avio nics
Audio and video switching
Communication systems

Quad SPST Switches

ADG5212/ADG5213

FUNCTIONAL BLOCK DIAGRAMS

S1

IN1

IN2

ADG5212

IN

IN4

SWITCHES SHOWN FO R A LOGIC 1 INPUT.

D1

S2

D2

S3

D3

S4

D4

Figure 1.

IN1

IN2

ADG5213

IN3

IN4

S1

D1

S2

D2

S3

D3

S4

D4

09767-001

GENERAL DESCRIPTION

The ADG5212/ADG5213 contain four independent single­pole/single-throw (SPST) switches. The ADG5212 switches
turn on with Logic 1. The ADG5213 has two switches with
digital control logic similar to that of the ADG5212; however,
the logic is inverted on the other two switches. Each switch
conducts equally well in both directions when on, and each
switch has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.

The ADG5212 and ADG5213 do not have a V
inputs are compatible with 3 V logic inputs over the full
operating supply range.

The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and­hold applications, where low glitch and fast settling are required.
Fast switching speed together with high signal bandwidth make
the parts suitable for video signal switching.

pin. The digital

L

PRODUCT HIGHLIGHTS

1. Trench Isolation Guards Against Latch-Up.

A dielectric trench separates the P and N channel transistors,
thereby preventing latch-up even under severe overvoltage
conditions.

2. Ultralow Capacitance and <1 pC Charge Injection.

3. Dual-Supply Operation.

For applications where the analog signal is bipolar, the
ADG5212/ADG5213 can be operated from dual supplies of
up to ±22 V.

4. Single-Supply Operation.

For applications where the analog signal is unipolar, the
ADG5212/ADG5213 can be operated from a single rail
power supply of up to 40 V.

5. 3 V Logic-Compatible Digital Inputs.

V

INH

6. No V

= 2.0 V, V

Logic Power Supply Required.

L

= 0.8 V.

INL

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADG5212/ADG5213

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

±15 V Dual Supply ....................................................................... 3

±20 V Dual Supply ....................................................................... 4

12 V Single Supply........................................................................ 5

36 V Single Supply........................................................................ 6

REVISION HISTORY

4/11—Revision 0: Initial Version

Continuous Current per Channel, Sx or Dx..............................7

Absolute Maximum Ratings ............................................................8

ESD Caution...................................................................................8

Pin Configurations and Function Descriptions............................9

Typical Performance Characteristics........................................... 10

Test Circuits..................................................................................... 14

Terminology .................................................................................... 16

Trench Isolation.............................................................................. 17

Applications Information.............................................................. 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. 0 | Page 2 of 20

ADG5212/ADG5213

SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V max
On Resistance, RON 160 Ω typ VS = ±10 V, IS = −1 mA,

200 250 280 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between Channels, ∆RON 2 Ω typ VS = ±10 V, IS = −1 mA
8 9 10 Ω max
On-Resistance Flatness, R

38 Ω typ VS = ±10 V, IS = −1 mA

FLAT(ON)

50 65 70 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) 0.01 nA typ

0.1 0.2 0.4 nA max
Drain Off Leakage, ID (Off) 0.01 nA typ

0.1 0.2 0.4 nA max
Channel On Leakage, ID (On), IS (On) 0.02 nA typ VS = VD = ±10 V, see Figure 26

0.2 0.25 0.9 nA max
DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INL

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

tON 175 ns typ RL = 300 Ω, CL = 35 pF
210 255 280 ns max VS = 10 V, see Figure 30
t

140 ns typ RL = 300 Ω, CL = 35 pF

OFF

170 195 215 ns max VS = 10 V, see Figure 30
Break-Before-Make Time Delay, tD

40 ns typ RL = 300 Ω, CL = 35 pF

(ADG5213 Only)
20 ns min VS1 = VS2 = 10 V, see Figure 29
Charge Injection, Q

0.07 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF,

INJ

Off Isolation −105 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

Channel-to-Channel Crosstalk −105 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

−3 dB Bandwidth 435 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 28
Insertion Loss −6.8 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

CS (Off) 3 pF typ VS = 0 V, f = 1 MHz
CD (Off) 5 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 8 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 45 μA typ Digital inputs = 0 V or VDD
55 70 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

see Figure 24

V

= ±10 V, VD = ∓10 V,

S

see Figure 23

V

= ±10 V, VD = ∓10 V,

S

see Figure 23

or VDD

GND

see Figure 31

see Figure 25

see Figure 27

see Figure 28

Rev. 0 | Page 3 of 20

ADG5212/ADG5213

±20 V DUAL SUPPLY

VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V max
On Resistance, RON 140 Ω typ

160 200 230 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match Between

Channels, ∆R

ON

1.5 Ω typ VS = ±15 V, IS = −1 mA

8 9 10 Ω max
On-Resistance Flatness, R

33 Ω typ VS = ±15 V, IS = −1 mA

FLAT(ON)

45 55 60 Ω max
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V

Source Off Leakage, IS (Off) 0.01 nA typ

0.1 0.2 0.4 nA max
Drain Off Leakage, ID (Off) 0.01 nA typ

0.1 0.2 0.4 nA max
Channel On Leakage, ID (On), IS (On) 0.02 nA typ VS = VD = ±15 V, see Figure 26

0.2 0.25 0.9 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.002 μA typ VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS1

tON 155 ns typ RL = 300 Ω, CL = 35 pF
195 235 255 ns max VS = 10 V, see Figure 30
t

145 ns typ RL = 300 Ω, CL = 35 pF

OFF

165 185 210 ns max VS = 10 V, see Figure 30
Break-Before-Make Time Delay, tD

35 ns typ R

(ADG5213 Only)
20 ns min VS1 = VS2 = 10 V, see Figure 29
Charge Injection, Q

−0.5 pC typ

INJ

Off Isolation −105 dB typ

Channel-to-Channel Crosstalk −105 dB typ

−3 dB Bandwidth 460 MHz typ

Insertion Loss −6 dB typ

CS (Off) 2.8 pF typ VS = 0 V, f = 1 MHz
CD (Off) 4.8 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 8 pF typ VS = 0 V, f = 1 MHz

= ±15 V, IS = −1 mA,

V

S

see Figure 24

V

= ±15 V, VD = ∓15 V,

S

Figure 23

see

V

= ±15 V, VD = ∓15 V,

S

Figure 23

see

or VDD

GND

= 300 Ω, CL = 35 pF

L

= 0 V, RS = 0 Ω, CL = 1 nF,

V

S

see Figure 31

= 50 Ω, CL = 5 pF, f = 1 MHz,

R

L

see Figure 25

= 50 Ω, CL = 5 pF, f = 1 MHz,

R

L

see Figure 27

= 50 Ω, CL = 5 pF, see

R

L

Figure 28

= 50 Ω, CL = 5 pF, f = 1 MHz,

R

L

see Figure 28

Rev. 0 | Page 4 of 20

ADG5212/ADG5213

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = +22 V, VSS = −22 V

IDD 50 μA typ Digital inputs = 0 V or VDD
70 110 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD/VSS ±9/±22 V min/V max GND = 0 V

1

Guaranteed by design; not subject to production test.

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V max
On Resistance, RON 350 Ω typ VS = 0 V to 10 V, IS = −1 mA,

see

Figure 24

500 610 700 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match Between Channels, ∆RON 4 Ω typ VS = 0 V to 10 V, IS = −1 mA
20 21 22 Ω max

On-Resistance Flatness, R
280 335 370 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) 0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V,

0.1 0.2 0.4 nA max

Drain Off Leakage, ID (Off) 0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V,

0.1 0.2 0.4 nA max

Channel On Leakage, ID (On), IS (On) 0.02 nA typ VS = VD = 1 V/10 V,

0.2 0.25 0.9 nA max
DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INH

INL

or I

INL

INH

±0.1 μA max

Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1

tON 235 ns typ RL = 300 Ω, CL = 35 pF

290 360 410 ns max VS = 8 V, see Figure 30

t

165 ns typ RL = 300 Ω, CL = 35 pF

OFF

205 235 260 ns max VS = 8 V, see Figure 30

Break-Before-Make Time Delay, tD

(ADG5213 Only)
50 ns min VS1 = VS2 = 8 V, see Figure 29
Charge Injection, Q

−0.5 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF,

INJ

Off Isolation −105 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

Channel-to-Channel Crosstalk −105 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

−3 dB Bandwidth 340 MHz typ RL = 50 Ω, CL = 5 pF, see

160 Ω typ VS = 0 V to 10 V, IS = −1 mA

FLAT(ON)

see Figure 23

see Figure 23

see Figure 26

2.0 V min

0.8 V max

0.002 μA typ VIN = V

GND

85 ns typ RL = 300 Ω, CL = 35 pF

see Figure 31

see Figure 25

see Figure 27

Figure 28

or VDD

Rev. 0 | Page 5 of 20

ADG5212/ADG5213

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Insertion Loss −11 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

CS (Off) 3.5 pF typ VS = 6 V, f = 1 MHz
CD (Off) 5.5 pF typ VS = 6 V, f = 1 MHz
CD (On), CS (On) 9 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD 40 μA typ Digital inputs = 0 V or VDD
65 μA max
VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

36 V SINGLE SUPPLY

VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V max
On Resistance, RON 150 Ω typ VS = 0 V to 30 V, IS = −1 mA,

170 215 245 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match Between Channels, ∆RON 1.6 Ω typ VS = 0 V to 30 V, IS = −1 mA
8 9 10 Ω max

On-Resistance Flatness, R
50 60 65 Ω max
LEAKAGE CURRENTS VDD =39.6 V, VSS = 0 V

Source Off Leakage, IS (Off) 0.01 nA typ VS = 1 V/30 V, VD = 30 V/1 V,

0.1 0.2 0.4 nA max

Drain Off Leakage, ID (Off) 0.01 nA typ VS = 1 V/30 V, VD = 30 V/1 V,

0.1 0.2 0.4 nA max

Channel On Leakage, ID (On), IS (On) 0.02 nA typ VS = VD = 1 V/30 V,

0.2 0.25 0.9 nA max
DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INH

INL

or I

INL

INH

±0.1 μA max

Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1

tON 190 ns typ RL = 300 Ω, CL = 35 pF

230 255 265 ns max VS = 18 V, see Figure 30

t

175 ns typ RL = 300 Ω, CL = 35 pF

OFF

215 230 245 ns max VS = 18 V, see Figure 30

Break-Before-Make Time Delay, tD

(ADG5213 Only)
25 ns min VS1 = VS2 = 18 V, see Figure 29
Charge Injection, Q

−0.5 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF,

INJ

Off Isolation −105 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

Channel-to-Channel Crosstalk −105 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

35 Ω typ VS = 0 V to 30 V, IS = −1 mA

FLAT(ON)

2.0 V min

0.8 V max

0.002 μA typ VIN = V

45 ns typ RL = 300 Ω, CL = 35 pF

see Figure 28

see Figure 24

see Figure 23

see Figure 23

see Figure 26

or VDD

GND

see Figure 31

see Figure 25

Figure 27

Rev. 0 | Page 6 of 20

ADG5212/ADG5213

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

−3 dB Bandwidth 410 MHz typ RL = 50 Ω, CL = 5 pF,

Insertion Loss −6.8 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,

CS (Off) 3 pF typ VS = 18 V, f = 1 MHz
CD (Off) 5 pF typ VS = 18 V, f = 1 MHz
CD (On), CS (On) 8 pF typ VS = 18 V, f = 1 MHz

POWER REQUIREMENTS VDD = 39.6 V

IDD 80 μA typ Digital inputs = 0 V or VDD
100 130 μA max
VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1

Guaranteed by design; not subject to production test.

CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx

Table 5.

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, Sx or Dx

VDD = +15 V, VSS = −15 V

TSSOP (θJA = 112.6°C/W) 18 10 5 mA maximum
LFCSP (θJA = 30.4°C/W) 32 15 6 mA maximum

VDD = +20 V, VSS = −20 V

TSSOP (θJA = 112.6°C/W) 29 16 8 mA maximum
LFCSP (θJA = 30.4°C/W) 50 22 9 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 18 12 7 mA maximum
LFCSP (θJA = 30.4°C/W) 32 17 8 mA maximum

VDD = 36 V, VSS = 0 V

TSSOP (θJA = 112.6°C/W) 34 18 8 mA maximum
LFCSP (θJA = 30.4°C/W) 59 24 9 mA maximum

see Figure 28

see Figure 28

Rev. 0 | Page 7 of 20

ADG5212/ADG5213

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1

Digital Inputs1

Peak Current, Sx or Dx Pin

Continuous Current, Sx or Dx2 Data + 15%
Temperature

Operating Range −40°C to +125°C
Storage Range −65°C to +150°C
Junction 150°C

Thermal Impedance, θJA

16-Lead TSSOP (4-Layer Board) 112.6°C/W
16-Lead LFCSP (4-Layer Board) 30.4°C/W

Reflow Soldering Peak

Temperature, Pb Free

1

Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.

Limit current to the maximum ratings given.

2

See Table 5.

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first
60 mA (pulsed at 1 ms, 10%

duty cycle maximum)

260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any
one time.

ESD CAUTION

Rev. 0 | Page 8 of 20

ADG5212/ADG5213

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

2

IN1

1S1

2

3GND

4S4

D1

16

ADG5212/

ADG5213

TOP VIEW

(Not to Scale)

5

D4

1

IN1

D1

2

S1

3

ADG5212/

V

4

SS

5

GND

(Not to Scal e)

S4

6

D4

7

8

IN4

NC = NO CONNECT

ADG5213

TOP VIEW

16

IN2

D2

15

S2

14

V

13

DD

12

NC

S3

11

D3

10

9

IN3

Figure 2. TSSOP Pin Configuration

V

SS

09767-002

NOTES

1. EXPOSED PAD TIED TO SUBSTRATE, V

2. NC = NO CONNECT .

Figure 3. LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 IN1 Logic Control Input.

2 16 D1 Drain Terminal. This pin can be an input or an output.

3 1 S1 Source Terminal. This pin can be an input or an output.

4 2 VSS Most Negative Power Supply Potential.

5 3 GND Ground (0 V) Reference.

6 4 S4 Source Terminal. This pin can be an input or an output.

7 5 D4 Drain Terminal. This pin can be an input or an output.

8 6 IN4 Logic Control Input.

9 7 IN3 Logic Control Input.

10 8 D3 Drain Terminal. This pin can be an input or an output.

11 9 S3 Source Terminal. This pin can be an input or an output.

12 10 NC No Connect. These pins are open.

13 11 VDD Most Positive Power Supply Potential.

14 12 S2 Source Terminal. This pin can be an input or an output.

15 13 D2 Drain Terminal. This pin can be an input or an output.

16 14 IN2 Logic Control Input.

N/A1 EP Exposed pad

Exposed Pad. The exposed pad is connected internally. For increased reliability of the
solder joints and maximum thermal capability, it is recommended that the pad be

.

SS

1

N/A means not applicable.

soldered to the substrate, V

D

IN2

14

13

15

12 S2

V

11

DD

10 NC

9S3

8

7

6

D3

IN4

IN3

.

SS

09767-003

Table 8. ADG5212 Truth Table

ADG5212 INx Switch Condition

1 On

0 Off

Table 9. ADG5213 Truth Table

ADG5213 INx S1, S4 S2, S3

0 Off On

1 On Off

Rev. 0 | Page 9 of 20

ADG5212/ADG5213

TYPICAL PERFORMANCE CHARACTERISTICS

160

TA = 25°C

140

120

VDD = +18V
V

= –18V

SS

160

140

120

TA = 25°C

VDD = 32.4V

= 0V

V

SS

100

V

80

60

ON RESISTANCE ()

40

20

0

–25 –20 –15 –10 –5 0 5 10 15 20 25

Figure 4. R

= +20V

DD

V

= –20V

SS

VS, VD (V)

as a Function of VS, VD (Dual Supply)

ON

V
V

DD
SS

= +22V

= –22V

250

TA = 25°C

200

150

100

ON RESISTANCE ( )

VDD = +16.5V
V

= –16.5V

SS

50

0

–20 –15 –10 –5 0 5 10 15 20

Figure 5. R

VDD = +15V
V

= –15V

SS

VS, VD (V)

as a Function of VS, VD (Dual Supply)

ON

VDD = +9V
V

= –9V

SS

VDD = +13.2V
V

= –13.2V

SS

500

ON RESISTANCE ()

450

400

350

300

250

200

150

100

50

0

TA = 25°C

01412108642

Figure 6. R

as a Function of VS, VD (Single Supply)

ON

VDD = 9V

= 0V

V

SS

VDD = 10.8V
V

SS

VS, VD (V)

= 0V

VDD = 12V
V

SS

= 0V

VDD = 13.2V
V

SS

= 0V

100

80

60

ON RESISTANCE ( )

40

20

0

043530252015105

09767-104

Figure 7. R

as a Function of VS, VD (Single Supply)

ON

VDD = 36V
V

SS

VS, VD (V)

= 0V

VDD = 39.6V

= 0V

V

SS

0

09767-107

250

VDD = +15V
V

= –15V

SS

200

150

100

ON RESISTANCE ()

50

0

–15 –10 –5 0 5 10 15

09767-105

Figure 8. R

as a Function of VS, VD for Different Temperatures,

ON

TA = +125°C

T

= +85°C

A

= +25°C

T

A

T

= –40°C

A

VS,VD (V)

09767-108

±15 V Dual Supply

200

180

160

140

120

100

80

ON RESISTANCE ()

60

40

20

VDD = +20V

= –20V

V

SS

0

–20 –15 –10 –5 0 5 10 2015

09767-106

Figure 9. R

as a Function of VS, VD for Different Temperatures,

ON

= +125°C

T

A

T

= +85°C

A

= +25°C

T

A

T

= –40°C

A

VS,VD (V)

09767-109

±20 V Dual Supply

Rev. 0 | Page 10 of 20

ADG5212/ADG5213

500

450

= +125°C

400

340

T

A

T

A

= +85°C

300

= +25°C

T

250

200

ON RESISTANCE ( )

150

A

= –40°C

T

A

100

50

VDD = 12V

= 0V

V

SS

0

024681012

VS,VD (V)

Figure 10. R

as a Function of VS, VD for Different Temperatures,

ON

12 V Single Supply

250

VDD = 36V

= 0V

V

SS

200

T

= +125°C

150

100

ON RESISTANCE ( )

A

T

A

T

A

T

A

= +85°C

= +25°C

= –40°C

50

0

03530252015105

VS,VD (V)

Figure 11. R

as a Function of VS,VD for Different Temperatures,

ON

36 V Single Supply

40

20

0

–20

–40

–60

–80

LEAKAGE CURRENT (p A)

–100

VDD = +15V

–120

V

= –15V

SS

V

= +10V/–10V

BIAS

–140

0 255075100125

I

, IS (ON) + +

D

TEMPERATURE (° C)

I

(OFF) – +

D

(OFF) + –

I

D

, IS (ON) – –

I

D

(OFF) + –

I

S

(OFF) – +

I

S

Figure 12. Leakage Currents vs. Temperature, ±15 V Dual Supply

09767-110

09767-111

09767-112

100

I

, IS (ON) + +

(OFF) + –

I

50

I

(OFF) – +

D

S

0

D

(OFF) – +

I

S

–50

(OFF) + –

I

–100

LEAKAGE CURRENT (p A)

–150

VDD = +20V
V

= –20V

SS

V

= +15V/–15V

BIAS

–200

0 255075100125

D

I

, IS (ON) – –

D

TEMPERATURE (° C)

Figure 13. Leakage Currents vs. Temperature, ±20 V Dual Supply

40

20

0

–20

–40

–60

–80

LEAKAGE CURRENT (p A)

–100

VDD = 12V

–120

V

= 0V

SS

V

= 1V/10V

BIAS

–140

0 255075100125

I

, IS (ON) + +

D

(OFF) – +

I

D

TEMPERATURE (° C)

(OFF) + –

I

D

(OFF) + –

I

S

, IS (ON) – –

I

D

(OFF) – +

I

S

Figure 14. Leakage Currents vs. Temperature, 12 V Single Supply

50

(OFF) + –

I

S

0

–50

–100

–150

LEAKAGE CURRENT (p A)

–200

VDD = 36V
V

= 0V

SS

V

BIAS

–250

0 255075100125

= 1V/30V

I

, IS (ON) + +

D

TEMPERATURE (° C)

I

(OFF) + –

D

(OFF) – +

I

D

I

(OFF) – +

S

I

, IS (ON) – –

D

Figure 15. Leakage Currents vs. Temperature, 36 V Single Supply

09767-113

09767-114

09767-115

Rev. 0 | Page 11 of 20

ADG5212/ADG5213

0

TA = 25°C
V

= +15V

DD

V

= –15V

–20

SS

–40

–60

–80

OFF ISOLATION (dB)

–100

0

TA = 25°C
V

= +15V

DD

V

= –15V

SS

–20

–40

–60

ACPSRR (dB)

–80

NO DECOUPLING CAPACITORS

–120

–140

10k 100k 1G100M10M1M

FREQUENCY (Hz)

Figure 16. Off Isolation vs. Frequency, ±15 V Dual Supply

0

TA = 25°C
V

= +15V

DD

V

= –15V

–20

SS

–40

–60

–80

CROSSTALK (dB)

–100

–120

–140

10k 100k 1G100M10M1M

FREQUENCY (Hz)

Figure 17. Crosstalk vs. Frequency, ±15 V Dual Supply

6

TA = 25°C
SOURCE TO DRAIN

5

4

3

2

1

CHARGE INJECTI ON (pC)

0

–1

V
V

= +15V

DD

= –15V

SS

V
V

DD
SS

V
V

= +12V

= 0V

DD

= –20V

SS

= +20V

V

DD

V

SS

= +36V

= 0V

–100

–120

1k 10k 100k 10M1M

09767-120

FREQUENCY (Hz)

DECOUPLING CAPACITORS

09767-123

Figure 19. ACPSRR vs. Frequency, ±15 V Dual Supply

0

TA = 25°C
V

= +15V

DD

–2

V

= –15V

SS

–4

–6

–8

–10

–12

ATTENUATION (dB)

–14

–16

–18

–20

100k 1G100M10M1M

09767-121

FREQUENCY (Hz)

09767-125

Figure 20. Bandwidth

12

TA = 25°C
V

= +15V

DD

V

= –15V

SS

10

8

6

4

CAPACITANCE (pF )

2

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

–2

–20 –10 0 10 20 30 40

VS (V)

Figure 18. Charge Injection vs. Source Voltage

09767-122

Rev. 0 | Page 12 of 20

0

–15 –10 –5 0 5 10 15

V

(V)

S

Figure 21. Capacitance

09767-127

ADG5212/ADG5213

0

TA = 25°C
V

= +15V

DD

V

= –15V

SS

–20

T

(+12V)

–40

T

–60

TIME (ns)

–80

–100

–120

–40 –20 120100806040200

(+36V)

ON

Figure 22. t

ON

(±15V)

T

(±20V)

OFF

09767-126

T

T

(+36V)

OFF

(+12V)

T

OFF

T

TEMPERATURE (°C)

, t

Times vs. Temperature

ON

OFF

OFF

(±15V) TON (±20V)

ON

Rev. 0 | Page 13 of 20

ADG5212/ADG5213

V

V

V

V

V

V

V

V

V

TEST CIRCUITS

IS (OFF) ID (OFF)

S

SD

A A

Figure 23. Off Leakage

SD

V

D

09767-015

S

ID (ON)

A

V

D

09767-016

Figure 26. On Leakage

I

DS

V1

SD

S

RON = V1/I

DS

Figure 24. On Resistance

DD

0.1µF

NETWORK

ANALYZER

V

OUT

R

L

50

V

S

CHANNEL-TO-CHANNEL CROSSTAL K = 20 log

09767-014

V

S1

S2

Figure 27. Channel-to-Channel Crosstalk

SS

0.1µF

V

DD

GND

V

OUT

V

SS

Dx

R

L

50

S

09767-021

DD

SS

0.1µF

V

DD

INx

V

IN

GND

0.1µF

NETWORK

V

SS

Sx

50

Dx

ANALYZER

50

V

OUT

R

L

50

V

S

V

IN

INx

0.1µF

DD

V

SS

0.1µF

NETWORK

V

DD

SS

Sx

Dx

GND

ANALYZER

50

V

OUT

R

L

50

V

S

OFF ISOLATION = 20 log

Figure 25. Off Isolation

V

OUT

V

S

09767-020

OFF ISOLATION = 20 log

Figure 28. Bandwidth

V

WITH SWITCH

OUT

V

WITHOUT SWITCH

OUT

09767-028

Rev. 0 | Page 14 of 20

ADG5212/ADG5213

V

V

V

VDDV

0.1µF

IN1,
IN2

S1 D1

S2 D2

V

S1

V

S2

DD

V

DD

ADG5213

GND

S

V

V

0.1µF

INx

SS

0.1µF

SS

R

L

R

L

300

C

L

35pF

V

OUT2

300

C

L

35pF

V

OUT1

Figure 29. Break-Before-Make Time Delay, t

V

DD

SS

0.1µF

V

V

V

DD

SS

V

C

L

35pF

OUT

Sx

GND

Dx

R

L

300

IN

V

OUT

V

OUT1

V

OUT2

ADG5212

V

IN

0V

0V

90%

0V

D

50% 50%

90% 90%

t

ON

50% 50%

90%

t

D

t

OFF

90%

90%

t

D

09767-017

09767-018

Figure 30. Switching Times

SS

V

V

DD

SS

C
1nF

V

OUT

L

R

S

V

S

SD

IN

GND

V

IN

V

OUT

ADG5212

Q

INJ

ON

= CL × V

OUT

V

OFF

OUT

09767-019

Figure 31. Charge Injection

Rev. 0 | Page 15 of 20

ADG5212/ADG5213

TERMINOLOGY

IDD

I

represents the positive supply current.

DD

I

SS

I

represents the negative supply current.

SS

, VS

V

D

V

and VS represent the analog voltage on Terminal Dx and

D

Terminal Sx, respectively.

R

ON

R

represents the ohmic resistance between Terminal Dx and

ON

Ter m in a l S x .

ΔR

ON

represents the difference between the RON of any two

ΔR

ON

channels.

R

FLAT(ON)

Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by R

(Off)

I

S

I

(Off) is the source leakage current with the switch off.

S

(Off)

I

D

I

(Off) is the drain leakage current with the switch off.

D

(On), IS (On)

I

D

I

(On) and IS (On) represent the channel leakage currents with

D

the switch on.

V

INL

V

is the maximum input voltage for Logic 0.

INL

V

INH

V

is the minimum input voltage for Logic 1.

INH

I

, I

INL

INH

I

INL

and I

represent the low and high input currents of the

INH

digital inputs.

C

(Off)

D

C

(Off) represents the off switch drain capacitance, which is

D

measured with reference to ground.

C

(Off)

S

C

(Off) represents the off switch source capacitance, which is

S

measured with reference to ground.

C

(On), CS (On)

D

C

(On) and CS (On) represent on switch capacitances, which

D

are measured with reference to ground.

FLAT(ON)

.

C

IN

C

is the digital input capacitance.

IN

t

ON

t

represents the delay between applying the digital control

ON

input and the output switching on (see Figure 30).

t

OFF

t

represents the delay between applying the digital control

OFF

input and the output switching off (see Figure 30).

t

D

represents the off time measured between the 80% point of

t

D

both switches when switching from one address state to
another.

Off Isolation

Off isolation is a measure of unwanted signal coupling through
an off switch.

Charge Injection

Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.

Crosstalk

Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.

Bandwidth

Bandwidth is the frequency at which the output is attenuated
by 3 dB.

On Response

On response is the frequency response of the on switch.

Insertion Loss

Insertion loss is the loss due to the on resistance of the switch.

AC Power Supply Rejection Ratio (ACPSRR)

AC power supply rejection ratio (ACPSRR) is the ratio of the
amplitude of signal on the output to the amplitude of the modula­tion. This is a measure of the ability of the device to avoid coupling
noise and spurious signals that appear on the supply voltage pin to
the output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p.

Rev. 0 | Page 16 of 20

ADG5212/ADG5213

TRENCH ISOLATION

In the ADG5212 and ADG5213, an insulating oxide layer

(trench) is placed between the NMOS and the PMOS transistors

of each CMOS switch. Parasitic junctions, which occur between

the transistors in junction isolated switches, are eliminated, and

the result is a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and NMOS

transistors form a diode that is reverse-biased under normal

operation. However, during overvoltage conditions, this diode

can become forward-biased. A silicon controlled rectifier (SCR)

type circuit is formed by the two transistors, causing a significant

amplification of the current that, in turn, leads to latch-up. With

trench isolation, this diode is removed and the result is a latch-

up proof switch.

NMOS PMOS

PWELL NWELL

TRENCH

BURIED OXIDE L AYER

HANDLE WAFER

Figure 32. Trench Isolation

09767-022

Rev. 0 | Page 17 of 20

ADG5212/ADG5213

APPLICATIONS INFORMATION

The ADG52xx family of switches and multiplexers provides a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5212/ADG5213 high voltage switches
allow single-supply operation from 9 V to 40 V and dual-supply
operation from ±9 V to ±22 V.

Rev. 0 | Page 18 of 20

ADG5212/ADG5213

S

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

EATING

PLANE

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40

BSC

0.20

0.09
8°

0°

Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

4.10

4.00 SQ

3.90

0.65

BSC

0.45

0.40

0.35

0.05 MAX

0.02 NOM

0.20 REF

0.35

0.30

0.25

13

12

9

8

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

EXPOSED

PAD

0.75

0.60

0.45

P

N

I

1

R

A

O

T

N

I

D

C

16

1

4

5

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

I

2.70

2.60 SQ

2.50

0.20 MIN

TO

COMPLIANT

JEDEC STANDARDS MO-220-WGGC.

08-16-2010-C

Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-16-17)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADG5212BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5212BRUZ-RL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5212BCPZ-RL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-17
ADG5213BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5213BRUZ-RL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5213BCPZ-RL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-17

1

Z = RoHS Compliant Part.

Rev. 0 | Page 19 of 20

ADG5212/ADG5213

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09767-0-4/11(0)

Rev. 0 | Page 20 of 20