Analog Devices ADG508F 9F 28F d Datasheet

4/8 Channel Fault-Protected

a

FEATURES
Low On Resistance (300 ⍀ Typ)
Fast Switching Times

250 ns Max

t

ON

250 ns Max

t

OFF

Low Power Dissipation (3.3 mW Max)
Fault and Overvoltage Protection (–40 V to +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped within Power

Supplies if an Overvoltage Occurs
Latch-Up Proof Construction
Break before Make Construction
TTL and CMOS Compatible Inputs

APPLICATIONS
Existing Multiplexer Applications (Both Fault-Protected

and Nonfault-Protected)
New Designs Requiring Multiplexer Functions

GENERAL DESCRIPTION

The ADG508F, ADG509F, and ADG528F are CMOS analog
multiplexers, the ADG508F and ADG528F comprising eight
single channels and the ADG509F comprising four differential
channels. These multiplexers provide fault protection. Using a
series n-channel, p-channel, n-channel MOSFET structure,
both device and signal source protection is provided in the event
of an overvoltage or power loss. The multiplexer can withstand
continuous overvoltage inputs from –40 V to +55 V. During
fault conditions, the multiplexer input (or output) appears as an
open circuit and only a few nanoamperes of leakage current will
flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.

The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1, and A2. The ADG509F switches one of four differen­tial inputs to a common differential output as determined by the
2-bit binary address lines A0 and A1. The ADG528F has on-chip
address and control latches that facilitate microprocessor inter­facing. An EN input on each device is used to enable or disable
the device. When disabled, all channels are switched OFF.

PRODUCT HIGHLIGHTS

1. Fault Protection.
The ADG508F/ADG509F/ADG528F can withstand con­tinuous voltage inputs from –40 V to +55 V. When a fault
occurs due to the power supplies being turned off, all the
channels are turned off and only a leakage current of a few
nanoamperes flows.

*Patent Pending.

Analog Multiplexers

ADG508F/ADG509F/ADG528F*

FUNCTIONAL BLOCK DIAGRAMS

ADG508F/ADG528F

S1

D

S8

ONLY

WR

RS

1 OF 8

DECODER

A0

A1 A2 EN

ADG528F

2. ON channel turns off while fault exists.

3. Low R

ON.

4. Fast Switching Times.

5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.

6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p and n-channel MOSFETs
thereby preventing latch-up.

ORDERING GUIDE

Model Temperature Range Package Option*

ADG508FBN –40°C to +85°C N-16
ADG508FBRN –40°C to +85°C R-16N
ADG508FBRW –40°C to +85°C R-16W

ADG509FBN –40°C to +85°C N-16
ADG509FBRN –40°C to +85°C R-16N
ADG509FBRW –40°C to +85°C R-16W

ADG528FBN –40°C to +85°C N-18
ADG528FBP –40°C to +85°C P-20A

*N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); RN = 0.15" Small

Outline IC (SOIC), RW = 0.3" Small Outline IC (SOIC).

S1A

S4A

S1B

S4B

ADG509F

1 OF 4

DECODER

A1

A0

EN

DA

DB

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

ADG508F/ADG509F/ADG528F–SPECIFICATIONS

Dual Supply

(V

= +15 V ⴞ 10%, V

DD

= –15 V ⴞ 10%, GND = 0 V, unless otherwise noted)

SS

B Version

–40ⴗC to

Parameter +25ⴗC +85ⴗC Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range V

+ 3 V min

SS

VDD – 1.5 V max

R

ON

300 350 Ω typ –10 V < VS < +10 V, IS = 1 mA;

VDD = +15 V ± 10%, VSS = –15 V ± 10%

400 Ω max –10 V < VS < +10 V, IS = 1 mA;

= +15 V ± 5%, VSS = –15 V ± 5%

V

R

Drift 0.6 %/°C typ VS = 0 V, IS = 1 mA

ON

DD

RON Match 5 % max VS = 0 V, IS = 1 mA

LEAKAGE CURRENTS

Source OFF Leakage IS (OFF) ± 0.02 nA typ VD = ± 10 V, VS = ⫿10 V;

± 1 ± 50 nA max Test Circuit 2

Drain OFF Leakage I

(OFF) ± 0.04 nA typ VD = ± 10 V, VS = ⫿10 V;

D

ADG508F/ADG528F ± 1 ± 60 nA max Test Circuit 3
ADG509F ± 1 ± 30 nA max

Channel ON Leakage I

, IS (ON) ± 0.04 nA typ VS = VD = ± 10 V;

D

ADG508F/ADG528F ± 1 ± 60 nA max Test Circuit 4
ADG509F ± 1 ± 30 nA max

FAULT

Output Leakage Current ± 0.02 nA typ VS = ± 33 V, VD = 0 V, Test Circuit 3

(With Overvoltage) ± 2 ± 2 µA max

Input Leakage Current ± 0.005 µA typ V

= ± 25 V, VD = ⫿10 V, Test Circuit 5

S

(With Overvoltage) ± 2 µA max

Input Leakage Current ± 0.001 µA typ VS = ± 25 V, VD = VEN = A0, A1, A2 = 0 V

(With Power Supplies OFF) ± 2 µA max Test Circuit 6

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

INL

or I

INH

INH

2.4 V min

0.8 V max
± 1 µA max VIN = 0 or V

DD

CIN, Digital Input Capacitance 5 pF typ

DYNAMIC CHARACTERISTICS

t

TRANSITION

1

200 ns typ RL = 1 MΩ, CL = 35 pF;
300 400 ns max VS1 = ± 10 V, VS8 = ⫿10 V; Test Circuit 7

t

OPEN

50 ns typ RL = 1 kΩ, CL = 35 pF;
25 10 ns min VS = 5 V; Test Circuit 8

t

(EN, WR) 200 ns typ RL = 1 kΩ, CL = 35 pF;

ON

250 400 ns max V

t

(EN, RS) 200 ns typ RL = 1 kΩ, CL = 35 pF;

OFF

= 5 V; Test Circuit 9

S

250 400 ns max VS = 5 V; Test Circuit 9

, Settling Time

t

SETT

0.1% 1 µs typ RL = 1 kΩ, CL = 35 pF;

0.01% 2.5 µs typ VS = 5 V

ADG528F Only

, Write Pulsewidth 100 120 ns min

t

W

tS, Address, Enable Setup Time 100 ns min

, Address, Enable Hold Time 10 ns min

t

H

tRS, Reset Pulsewidth 100 ns min
Charge Injection 4 pC typ VS =0V,RS=0Ω,CL= 1 nF; Test Circuit 12
OFF Isolation 68 dB typ R

= 1 kΩ, CL = 15 pF, f = 100 kHz;

L

50 dB min VS = 7 V rms; Test Circuit 13

CS (OFF) 5 pF typ

(OFF)

C

D

ADG508F/ADG528F 50 pF typ

ADG509F 25 pF typ

POWER REQUIREMENTS

I

DD

I

SS

NOTES

1

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

0.1 0.2 mA max VIN = 0 V or 5 V

0.1 0.1 mA max

REV. D–2–

ADG508F/ADG509F/ADG528F

Table I. ADG508F Truth Table

A2 A1 A0 EN ON Switch

X X X 0 NONE

00011

00112

01013

01114

10015

10116

11017

11118

X = Don’t Care

Table III. ADG528F Truth Table

A2 A1 A0 EN WR RS ON Switch

X XXXg 1 Retains Previous Switch Condition
X XXXX0NONE (Address and Enable Latches Cleared)
X X X 0 0 1 NONE
0 001011
0 011012
0 101013
0 111014
1 001015
1 011016
1 101017
1 111018

X = Don’t Care

Table II. ADG509F Truth Table

A1 A0 EN ON Switch Pair

X X 0 NONE
0011
0112
1013
1114

X = Don’t Care

TIMING DIAGRAMS (ADG528F)

3V

WR

A0, A1, A2

EN

50%

0V

3V

0V

t

W

2V

50%

t

S

t

0.8V

H

Figure 1.

Figure 1 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive; there-

fore, while WR is held low, the latches are transparent and the

switches respond to the address and enable inputs. This input

data is latched on the rising edge of WR.

3V

RS

SWITCH
OUTPUT

0V

V

O

0V

50%

50%

t

RS

t

(RS)

OFF

0.8V

O

Figure 2.

Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turn­off Time, t

OFF

(RS).

Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. t

= tF = 20 ns.

R

REV. D

–3–

ADG508F/ADG509F/ADG528F

WR

A0

RS

A1

S1

S2

S3

S5

S6

EN

V

SS

A2

S4 S7

D

S8

V

DD

GND

1

2

18

17

5

6

7

14

13

12

3

4

16

15

811

910

TOP VIEW

(Not to Scale)

ADG528F

EN

V

SS

S3

S1

S2

A0

WR

A1

NC

RS

1931220

4

5

8

6

7

12 1391110

18

17

14

16

15

TOP VIEW

(Not to Scale)

ADG528F

A2

GND

S6

V

DD

S5

S4

D

S7

S8

NC

NC = NO CONNECT

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V

V

SS

, VA Digital Input . . . . . . . – 0.3 V to VDD + 2 V or 20 mA,

V

EN

Whichever Occurs First

VS, Analog Input Overvoltage with Power ON . . . . . VSS – 25 V

+ 40 V

to V

V

, Analog Input Overvoltage with Power OFF

S

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 V to +55 V

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA

Peak Current, S or D

(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Plastic Package

, Thermal Impedance

θ

JA

16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117°C

18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C

SOIC Package

, Thermal Impedance

θ

JA

Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77°C/W

Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

PLCC Package

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

ADG508F/ADG509F PIN CONFIGURATIONS

DIP/SOIC DIP/SOIC

1

A0

2

EN

3

V

SS

ADG508F

4

S1

TOP VIEW

5

S2

(Not to Scale)

6

S3

7

S4

DS8

89

16

A1

15

A2

14

GND

13

V

DD

12

S5

11

S6

S7

10

A0

1

EN

2

3

V

SS

ADG509F

S1A

4

TOP VIEW

5

S2A

(Not to Scale)

6

S3A

7

S4A

89

DA DB

16

15

14

13

12

11

10

ADG528F PIN CONFIGURATIONS

DIP PLCC

A1

GND

V

DD

S1B

S2B

S3B

S4B

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG508F/ADG509F/ADG528F features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. D