Datasheet ADG465BRT, ADG465BRM Datasheet (Analog Devices)

Single Channel Protector

a

FEATURES
Fault and Overvoltage Protection up to ⴞ40␣ V

Signal Paths Open Circuit with Power Off

Signal Path Resistance of R
44 V Supply Maximum Ratings
Low On Resistance 80 ⍀ Typ
1 nA Max Path Current Leakage @ +25ⴗC
Low Power Dissipation 0.8␣ ␮W Typ
Latchup-Proof Construction

APPLICATIONS
ATE Equipment
Sensitive Measurement Equipment
Hot-Insertion Rack Systems
ADC Input Channel Protection

GENERAL DESCRIPTION

The ADG465 is a single channel protector in an SOT-23 pack­age. The channel protector is placed in series with the signal
path, and will protect sensitive components from voltage tran­sience in the signal path whether or not the power supplies are
present. Because the channel protection works regardless of the
presence of the supplies, the channel protectors are ideal for use
in applications where correct power sequencing cannot always
be guaranteed to protect analog inputs (e.g., hot-insertion rack
systems). This is discussed further, and some example circuits
are given, in the Applications section of this data sheet.

A channel protector consists of an n-channel MOSFET, a
p-channel MOSFET and an n-channel MOSFET, connected in
series. The channel protector behaves like a series resistor dur­ing normal operation, i.e., (V

+ 2 V) < VIN < (VDD – 1.5 V).

SS

When a channel’s analog input exceeds the power supplies
(including V

and VSS = 0 V), one of the MOSFETs will

DD

switch off, clamping the output to either V
Circuitry and signal source protection is provided in the event of
an overvoltage or power loss. The channel protectors can with­stand overvoltage inputs from –40 V to +40 V. See the Circuit
Information section of this data sheet.

The ADG465 can operate from both bipolar and unipolar
supplies. The channels are normally on when power is con­nected, and open circuit when power is disconnected. With

power supplies of ±15 V, the on-resistance of the ADG465 is
80 Ω typ, with a leakage current of ±1 nA max. When power

is disconnected, the input leakage current is approximately

±5 nA typ.

The ADG465 is available in a 6-lead plastic surface mount

SOT-23 package, and an 8-lead µSOIC package.

with Power On

ON

+ 2 V or VDD – 1.5 V.

SS

in an SOT-23 Package

ADG465

FUNCTIONAL BLOCK DIAGRAM

VDDV

SS

V

V

IN

V

IN

V

DD

D1

ADG465

OUTPUT CLAMPED
@ V

PRODUCT HIGHLIGHTS

1. Fault Protection.
The ADG465 can withstand continuous voltage inputs from
–40 V to +40 V. When a fault occurs due to the power sup­plies being turned off, or due to an overvoltage being applied
to the ADG465, the output is clamped. When power is turned
off, current is limited to the nanoampere level.

2. Low Power Dissipation.

3. Low R

80 Ω typ.

ON

4. Trench Isolation Latchup-Proof Construction.
A dielectric trench separates the p- and n-channel MOSFETs
thereby preventing latchup.

DD

– 1.5V

V

S1

V

OUT

V

OUT

V

DD

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

ADG465–SPECIFICATIONS

Dual Supply

Parameter +25ⴗC B Units Test Conditions/Comments

FAULT PROTECTED CHANNEL

Fault-Free Analog Signal Range

R

ON

∆R

ON

LEAKAGE CURRENTS

Channel Output Leakage, I

(Without Fault Condition) ±0.1 ±1 nA typ

Channel Input Leakage, I

(With Fault Condition) ±0.2 ±0.4 nA typ V

Channel Input Leakage, I

(With Power Off and Fault) ±0.5 ±2 nA typ V

Channel Input Leakage, I

(With Power Off and Output S/C) ±0.005 ±0.1 µA typ V

POWER REQUIREMENTS

I

DD

I

SS

V

DD/VSS

NOTES

1

Temperature range is as follows: B Version: – 40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

1

(VDD = +15 V, VSS = –15 V, GND = 0 V, unless otherwise noted)

2

VSS + 1.2 V min Output Open Circuit

– 0.8 V max

V

DD

80 Ω typ –10 V ≤ VS ≤ +10 V, I
95 115 Ω max
45 Ω max –5 V ≤ VS ≤ +5 V

S(ON)

±1 ±5 nA max

D(ON)

±2 ±5 nA max

D(OFF)

±2 ±10 nA max V

D(OFF)

±0.015 ±0.5 µA max

±0.05 µA typ
±0.5 ±5 µA max
±0.05 µA typ
±0.5 ±5 µA max

0 0 V min

±20 ±20 V max

VS = V

V

= ±10 V

D

= ±25 V

S

= Open Circuit

D

VDD = 0 V, V

= ±35 V

S

= Open Circuit

D

VDD = 0 V, V

= ±35 V, V

S

= 0 V

SS

= 0 V

SS

= 0 V

D

= 1 mA

S

–2–

–2–

REV. A

REV. A

ADG465

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V

V

, VD, Analog Input Overvoltage with Power ON

S

. . . . . . . . . . . . . . . . . . . . . . . . . VSS – 20 V to VDD + 20 V

, VD, Analog Input Overvoltage with Power OFF

V

S

1

2

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –35 V to +35 V

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .20 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .40 mA

(Pulsed at 1 ms, 10% Duty Cycle Max)

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

SOT-23 Package

, Thermal Impedance . . . . . . . . . . . . . . . . . . . 230°C/W

θ

JA

µSOIC Package

, Thermal Impedance . . . . . . . . . . . . . . . . . . . 205°C/W

θ

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at S or D will be clamped by the channel protector, see Circuit

Information section of the data sheet.

PIN CONFIGURATIONS

(RT-6)

V

1

D1

ADG465

NC

2

TOP VIEW

(Not to Scale)

V

3

SS

NC = NO CONNECT

6

V

DD

5

NC

4

V

S1

(RM-8)

1

NC

ADG465

V

2

DD

TOP VIEW

(Not to Scale)

V

3

S1

45

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

Pin Pin
RT-6 RM-8 Pin Description

17 V

, this is one terminal of the channel protec-

D1

tor. The channel protector is bidirectional so this

terminal may be used as an input or an output.
2 1, 4 NC, this is a no connect pin.
36 V

, Negative Power Supply (0 V to –20 V).

SS

The clamping point for a negative overvoltage is

also defined by V

, see Overvoltage Protection

SS

section.
43 V

, this is one terminal of the channel protec-

S1

tor. The channel protector is bidirectional so this

terminal may be used as an output or an input.
5 5, 8 NC, this is a no connect pin.
62 V

, Positive Power Supply (0 V to 20 V). The

DD

clamping point for a positive overvoltage is also

defined by V

, see Overvoltage Protection

DD

section.

8

NC
V

7

D1

V

6

SS

NCNC

ORDERING GUIDE

Model Temperature Range Package Descriptions Brand Package Options

ADG465BRT –40°C to +85°C 6-Lead Plastic Surface Mount SOT-23 S1B RT-6
ADG465BRM –40°C to +85°C 8-Lead µSOIC S1B RM-8

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.

WARNING!

Although the ADG465 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

ESD SENSITIVE DEVICE

ADG465

—Typical Performance Characteristics

140

TEMP = +258C

130

120

110

100

– V

ON

90

R

80

70

60

50

–10 10–5

VDD = +5V
VSS = –5V

VDD = +10V
VSS = –10V

05

VD, VS – Volts

VDD = +16.5V
VSS = –16.5V

Figure 1. On Resistance as a Function of VDD and V
(Input Voltage)

125

115

105

– V
R

V

= +15V

DD

VSS = –15V

95

85

ON

75

65

55

+1258C

+808C

+258C

POSITIVE OVERVOLTAGE ON INPUT

R

= 100kV

LOAD

= 100pF

C

LOAD

VDD = +10V
V

= –10V

SS

15

10

5

Volts

0

–5

Ch1 500mV5.00V Ch2 5.00V M50.0ns Ch1

D

Figure 3. Positive Overvoltage Transience Response

NEGATIVE OVERVOLTAGE ON INPUT

5

0

–5

Volts
–10

–15

5V TO –15V

STEP INPUT

–5V TO +15V
STEP INPUT

CHANNEL PROTECTOR

OUTPUT

R

= 100kV

LOAD

= 100pF

C

LOAD

V

= +10V

DD

= –10V

V

SS

CHANNEL PROTECTOR

OUTPUT

45

–10 10–5 0 5

VD, VS – Volts

Figure 2. On Resistance as a Function of Temperature

(Input Voltage)

and V

D

10V TO +10V INPUT

10

20

Ch1 500mV5.00V Ch2 5.00V M100ns Ch1

20V

V

OUTPUT

V

Figure 5. Overvoltage Ramp

CLAMP

CLAMP

Ch1 500mV5.00V

Ch2 5.00V M50.0ns Ch1

Figure 4. Negative Overvoltage Transience Response

R

= 100kV

LOAD

= +5V

V

DD

= –5V

V

SS

= 4.5V

= 4V

–4–

REV. A

ADG465

CIRCUIT INFORMATION

Figure 6 below shows a simplified schematic of a channel pro­tector circuit. The circuit is comprised of four MOS transis­tors—two NMOS and two PMOS. One of the PMOS devices
does not lie directly in the signal path, but is used to connect the
source of the second PMOS device to its backgate. This has the
effect of lowering the threshold voltage and increasing the
input signal range of the channel for normal operation. The
source and backgate of the NMOS devices are connected for the
same reason. During normal operation the channel protectors

have a resistance of 80␣ Ω typ. The channel protectors are very

low power devices; even under fault conditions the supply cur­rent is limited to sub-microampere levels. All transistors are
dielectrically isolated from each other using a trench isolation
method. This makes it impossible to latch up the channel pro­tectors. For an explanation, see Trench Isolation section.

V

SS

PMOS

NMOSNMOS

PMOS

V

DD

V

SS

V

DD

– VTP where VTP is the threshold voltage of the PMOS

V

SS

device (2␣ V typ). If the input voltage exceeds these threshold
voltages, the output of the channel protector (no load) is
clamped at these threshold voltages. However, the channel
protector output will clamp at a voltage inside these thresholds
if the output is loaded. For example, with an output load of

1␣ kΩ, V

clamp at V

= 15␣ V and a positive overvoltage. The output will

DD

– V

DD

– ∆V = 15␣ V – 1.5␣ V – 0.6␣ V = 12.9␣ V

TN

where ∆V is due to I. R voltage drops across the channels of the

MOS devices (see Figure 8). As can be seen from Figure 8, the
current during fault condition is determined by the load on the
output (i.e., V

CLAMP/RL

). However, if the supplies are off, the

fault current is limited to the nanoampere level.

Figures 7, 9 and 10 show the operating conditions of the signal
path transistors during various fault conditions. Figure 7 shows
how the channel protectors operate when a positive overvoltage
is applied to the channel protector.

V

– VTN*

DD

(+13.5V)

POSITIVE

OVERVOLTAGE

(+20V)

*V

NMOS

SATURATED

= NMOS THRESHOLD VOLTAGE (+1.5V)

TN

PMOS

(–15V)VDD (+15V) VDD (+15V)

V

SS

NON­SATURATED

NMOS

NON­SATURATED

Figure 6. The Channel Protector Circuit

Overvoltage Protection

When a fault condition occurs on the input of a channel pro­tector, the voltage on the input has exceeded some threshold
voltage set by the supply rail voltages. The threshold voltages
are related to the supply rails as follows: for a positive overvolt­age, the threshold voltage is given by V

– VT where VTN is the

DD

threshold voltage of the NMOS transistor (1.5␣ V typ). In the
case of a negative overvoltage the threshold voltage is given by

OVERVOLTAGE

OPERATION

(SATURATED)

(+20V)

VT = 1.5V

V

D

+

N

SPACE CHARGE

EFFECTIVE

REGION

V

G

(VDD = +15V)

–

P

V

S

+

N

N-CHANNEL

(VG – VT = 13.5V)

Figure 8. Positive Overvoltage Operation on the Channel Protector

Figure 7. Positive Overvoltage on the Channel Protector

The first NMOS transistor goes into a saturated mode of opera­tion as the voltage on its Drain exceeds the Gate voltage (V
the threshold voltage (V

). This situation is shown in Figure 8.

TN

The potential at the source of the NMOS device is equal to V

DD

) –

DD

–VTN. The other MOS devices are in a nonsaturated mode of
operation.

(+13.5V)

+

N

DV

PMOS

NONSATURATED

NMOS

OPERATION

I

OUT

R

V

L

CLAMP

REV. A

–5–

ADG465

When a negative overvoltage is applied to the channel protector
circuit, the PMOS transistor enters a saturated mode of operation
as the drain voltage exceeds V

– VTP. See Figure 9 below. As in

SS

the case of the positive overvoltage, the other MOS devices are
nonsaturated.

NEGATIVE

NEGATIVE

OVERVOLTAGE

(–20V)

OVERVOLTAGE

(–20V)

NMOS

NON­SATURATED

= PMOS THRESHOLD VOLTAGE (+2V)

*V

TP

PMOS

(–15V)VDD (+15V) VDD (+15V)

V

SS

SATURATED

V

– VTP*

SS

(–13V)

NMOS

NON­SATURATED

Figure 9. Negative Overvoltage on the Channel Protector

The channel protector is also functional when the supply rails
are down (e.g., power failure) or momentarily unconnected
(e.g., rack system). This is where the channel protector has an
advantage over more conventional protection methods such as
diode clamping (see Applications Information). When V
V

equal 0␣ V, all transistors are off and the current is limited to

SS

DD

and

microampere levels (see Figure 10).

(0V)

POSITIVE OR

NEGATIVE

OVERVOLTAGE

NMOS

OFF OFF OFF

PMOS

VSS (0V)VDD (0V) VDD (0V)

NMOS

TRENCH ISOLATION

The MOS devices that make up the channel protector are
isolated from each other by an oxide layer (trench) (see Figure

11). When the NMOS and PMOS devices are not electrically
isolated from each other, there exists the possibility of “latchup”
caused by parasitic junctions between CMOS transistors. Latchup
is caused when P-N junctions that are normally reverse biased,
become forward biased, causing large currents to flow. This can
be destructive.

CMOS devices are normally isolated from each other by
Junction Isolation. In Junction Isolation, the N and P wells of the
CMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latchup. With Trench Isolation, this diode is removed; the result
is a latchup-proof circuit.

V

G

V

S

T
R
E
N
C
H

P-CHANNEL N-CHANNEL

+

P

–

N

V

D

+

P

BURIED OXIDE LAYER

SUBSTRATE (BACKGATE)

V

T

N

R
E
N
C

P

H

V

G

V

S

+

–

D

T

+

N

R
E
N
C
H

Figure 11. Trench Isolation

Figure 10. Channel Protector Supplies Equal to Zero Volts

–6–

REV. A

ADG465

APPLICATIONS INFORMATION
Overvoltage and Power Supply Sequencing Protection

The ADG465 is ideal for use in applications where input over­voltage protection is required and correct power supply sequencing
cannot always be guaranteed. The overvoltage protection en­sures that the output voltage of the channel protector will not
exceed the threshold voltages set by the supplies (see Circuit
Information section) when there is an overvoltage on the input.
When the input voltage does not exceed these threshold volt-

ages, the channel protector behaves like a series resistor (80␣ Ω

typ). The resistance of the channel protector does vary slightly
with operating conditions (see Typical Performance Graphs).

The power sequencing protection is afforded by the fact that
when the supplies to the channel protector are not connected,
the channel protector becomes a high resistance device. Under
this condition all transistors in the channel protector are off and
the only currents that flow are leakage currents, which are at the

µA level.

EDGE

+5V

–5V

ANALOG IN

–2.5V TO +2.5V

LOGIC

LOGIC

GND

CONNECTOR

V

DD

V

SS

ADG465

ADC

CONTROL

LOGIC

channel protectors. In this way, the outputs of the channel
protectors are clamped well below V

and VSS until the

DD

capacitors are charged. The diodes ensure that the supplies on
the channel protector never exceed the supply rails of the board
when it is being disconnected. Again, this ensures that signals
on the inputs of the CMOS devices never exceed the supplies.

High Voltage Surge Suppression

The ADG465 are not intended for use in high voltage applica­tions such as surge suppression. The ADG465 has breakdown
voltages of V

– 20 V and VDD + 20 V on the inputs when the

SS

power supplies are connected. When the power supplies are
disconnected, the breakdown voltages on the input of the chan-

nel protector are ±35␣ V. In applications where inputs are likely

to be subject to overvoltages exceeding the breakdown voltages
quoted for the channel protectors, transient voltage suppressors
(TVSs) should be used. These devices are commonly used to
protect vulnerable circuits from electric overstress such as that
caused by electrostatic discharge, inductive load switching and
induced lightning. However, TVSs can have a substantial

standby (leakage) current (300␣ µA typ) at the reverse standoff

voltage. The reverse standoff voltage of a TVS is the normal
peak operating voltage of the circuit. In addition, TVSs offer no
protection against latchup of sensitive CMOS devices when the
power supplies are off. To provide the best leakage current
specification and circuit protection, the best solution is to use a
channel protector in conjunction with a TVS.

Figure 13 shows an input protection scheme that uses both a
TVS and channel protector. The TVS is selected with a reverse
standoff voltage much greater than the operating voltage of the
circuit (TVSs with higher breakdown voltages tend to have
better standby leakage current specifications), but inside
the breakdown voltage of the channel protector. This circuit
protects the circuitry whether or not the power supplies are
present.

= –5V

VDD = +5V

V

SS

Figure 12. Overvoltage and Power Supply Sequencing
Protection

Figure 12 shows a typical application requiring overvoltage and
power supply sequencing protection. The application shows a
Hot-Insertion rack system. This involves plugging a circuit
board or module into a live rack via an edge connector. In this
type of application it is not possible to guarantee correct power
supply sequencing. Correct power supply sequencing means that
the power supplies should be connected prior to any external
signals. Incorrect power sequencing can cause a CMOS device
to “latch up,” see Trench Isolation section. This is true of most
CMOS devices, regardless of the functionality. RC networks
are used on the supplies of the channel protector (Figure 12)
to ensure that the rest of the circuitry is powered up before the

REV. A

–7–

ADG465

TVSs
BREAKDOWN
VOLTAGE = 20V

ADC

Figure 13. High Voltage Protection

ADG465

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

6-Lead Plastic Surface Mount SOT-23 Package

(RT-6)

0.122 (3.10)

0.106 (2.70)

4 5 6

0.071 (1.80)

0.059 (1.50)

0.051 (1.30)

0.035 (0.90)

PIN 1

0.006 (0.15)

0.000 (0.00)

1

0.075 (1.90)

2

BSC

0.020 (0.50)

0.010 (0.25)

0.118 (3.00)

0.098 (2.50)

3

0.037 (0.95) BSC

0.057 (1.45)

0.035 (0.90)

SEATING
PLANE

0.009 (0.23)

0.003 (0.08)

8-Lead ␮SOIC

(RM-8)

108

08

C2217a–0–9/98

0.022 (0.55)

0.014 (0.35)

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)
SEATING

PLANE

0.122 (3.10)

0.114 (2.90)

8

1

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.018 (0.46)

0.008 (0.20)

5

4

0.199 (5.05)

0.187 (4.75)

0.043 (1.09)

0.037 (0.94)

0.011 (0.28)

0.003 (0.08)

0.120 (3.05)

0.112 (2.84)

33°
27°

0.028 (0.71)

0.016 (0.41)

PRINTED IN U.S.A.

–8–

REV. A