Analog Devices ADG439F, ADG438F Datasheet

High Performance 4/8 Channel

S1

S8

A0

D

A1 A2 EN

ADG438F

1 OF 8

DECODER

A0

ADG439F

A1 EN

S1A

DA

S4A

S1B

S4B

DB

1 OF 4

DECODER

a

FEATURES
Fast Switching Times

t

250 ns max

ON

t

150 ns max

OFF

Fault and Overvoltage Protection (–40 V, +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped Within Power

Supplies If an Overvoltage Occurs
Latch-Up Proof Construction
Break Before Make Construction
TTL and CMOS Compatible Inputs

APPLICATIONS
Data Acquisition Systems
Industrial and Process Control Systems
Avionics Test Equipment
Signal Routing Between Systems
High Reliability Control Systems

Fault-Protected Analog Multiplexers

ADG438F/ADG439F*

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

The ADG438F/ADG439F are CMOS analog multiplexers, the
ADG438F comprising 8 single channels and the ADG439F
comprising four differential channels. These multiplexers pro­vide fault protection. Using a series n-channel, p-channel, n­channel MOSFET structure, both device and signal source
protection is provided in the event of an overvoltage or power
loss. The multiplexer can withstand continuous overvoltage
inputs from –40 V to +55 V. During fault conditions, the multi­plexer input (or output) appears as an open circuit and only a
few nanoamperes of leakage current will flow. This protects not
only the multiplexer and the circuitry driven by the multiplexer,
but also protects the sensors or signal sources which drive the
multiplexer.

The ADG438F switches one of eight inputs to a common out­put as determined by the 3-bit binary address lines A0, A1 and
A2. The ADG439F switches one of four differential inputs to a
common differential output as determined by the 2-bit binary
address lines A0 and A1. An EN input on each device is used to
enable or disable the device. When disabled, all channels are
switched OFF.

*Patent Pending.

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

PRODUCT HIGHLIGHTS

1. Fault Protection.
The ADG438F/ADG439F can withstand continuous volt­age inputs up to –40 V or +55 V. When a fault occurs due
to the power supplies being turned off, all the channels
are turned off and only a leakage current of a few nano­amperes flows.

2. ON channel turns OFF while fault exists.

3. Low R

ON.

4. Fast Switching Times.

5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.

6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p- and n-channel MOSFETs
thereby preventing latch-up.

7. Improved OFF Isolation.
Trench isolation enhances the channel-to-channel isolation
of the ADG438F/ADG439F.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ADG438F/ADG439F–SPECIFICATIONS

1

Dual Supply

(V

= +15 V, V

DD

= –15 V, GND = 0 V, unless otherwise noted)

SS

B Version

–40ⴗC to –40ⴗC to

Parameter +25ⴗC +85ⴗC +105ⴗC Units Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range V

R

ON

∆R

ON

R

Drift 0.6 %/°C typ V

ON

RON Match 3 3 3 % max V

+ 1.2 VSS + 1.2 V min

SS

VDD – 0.8 VDD – 0.8 V max

400 400 Ω max –10 V < V

5 5 % max –5 V < VS < +5 V, IS = 1 mA;

S

S

< +10 V, IS = 1 mA;

S

= 0 V, IS = 1 mA

= ±10 V, I

= 1 mA

S

LEAKAGE CURRENTS

Source OFF Leakage I

Drain OFF Leakage I

ADG438F ±0.5 ±5 ±30 nA max Test Circuit 3

(OFF) ±0.01 nA typ VD = ±10 V, V

S

(OFF) ±0.01 nA typ VD = ±10 V, V

D

±0.5 ±2 ±5 nA max Test Circuit 2

= ⫿10 V;

S

= ⫿10 V;

S

ADG439F ±0.5 ±5 ±15 nA max

Channel ON Leakage ID, I

ADG438F ±0.5 ±5 ±30 nA max Test Circuit 4

(ON) ±0.01 nA typ V

S

= V

S

= ±10 V;

D

ADG439F ±0.5 ±5 ±15 nA max

FAULT

Output Leakage Current ±0.02 nA typ V

(With Overvoltage) ±0.1 ±2 ±10 µA max

Input Leakage Current ±0.005 µA typ VS = ±25 V, V

(With Overvoltage) ±0.1 ±1 ±2 µA max

Input Leakage Current ±0.001 µA typ VS = ±25 V, V

(With Power Supplies OFF) ±0.1 ±1 ±4 µA max Test Circuit 6

= –33 V, +33 V or +50 V, VD = 0 V, Test Circuit 3

S

= ⫿10 V, Test Circuit 5

D

= VEN = A0, A1, A2 = 0 V

D

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current

I

or I

INL

CIN, Digital Input Capacitance 5 pF typ

INH

DYNAMIC CHARACTERISTICS

t

TRANSITION

t

OPEN

t

(EN) 200 ns typ R

ON

t

(EN) 110 ns typ R

OFF

t

, Settling Time

SETT

0.1% 0.5 0.5 µs typ RL = 1 kΩ, C

INH

INL

2

170 ns typ R
220 300 320 ns max V
10 10 10 ns min R

250 300 300 ns max VS = +5 V; Test Circuit 9

150 180 180 ns max VS = +5 V; Test Circuit 9

0.01% 1.7 1.7 µs typ V

Charge Injection 4 pC typ VS =0V,R
OFF Isolation 80 dB typ R

Channel-to-Channel Crosstalk 85 dB typ R

2.4 2.4 V min

0.8 0.8 V max

±1 ±1 µA max V

= 0 or V

IN

= 1 MΩ, C

L

= ±10 V, V

S1

= 1 kΩ, C

L

VS = +5 V; Test Circuit 8

= 1 kΩ, C

L

= 1 kΩ, C

L

= +5 V

S

= 1 kΩ, C

L

VS = 7 V rms; Test Circuit 11

= 1 kΩ, C

L

VS = 7 V rms; Test Circuit 12

DD

= 35 pF;

L

= ⫿10 V; Test Circuit 7

S8

= 35 pF;

L

= 35 pF;

L

= 35 pF;

L

= 35 pF;

L

=0Ω,C

S

= 1 nF; Test Circuit 10

L

= 15 pF, f = 100 kHz;

L

= 15 pF, f = 100 kHz;

L

CS (OFF) 5 pF typ
CD (OFF)

ADG438F 50 pF typ
ADG439F 25 pF typ

POWER REQUIREMENTS

I

DD

I

SS

NOTES

1

Temperature range is as follows: B Version: –40°C to +105°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

0.05 mA typ VIN = 0 V or 5 V

0.15 0.25 0.25 mA max

0.01 mA typ

0.02 0.04 0.04 mA max

–2– REV. D

ADG438F/ADG439F

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V

V

SS

, VA Digital Input . . . . . . . – 0.3 V to VDD + 2 V or 20 mA,

V

EN

Whichever Occurs First

, Analog Input Overvoltage with Power ON . . . . . VSS – 25 V

V

S

, Analog Input Overvoltage with Power OFF

V

S

to V

+ 40 V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 V to +55 V

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA

Peak Current, S or D

(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic Package

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W

θ

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC Package

, Thermal Impedance

θ

JA

Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W

Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

ORDERING GUIDE

Model Temperature Range Package Option*

ADG438FBN –40°C to +105°C N-16
ADG438FBR –40°C to +105°C R-16N

ADG439FBN –40°C to +105°C N-16
ADG439FBR –40°C to +105°C R-16N
ADG439FBRW –40°C to +105°C R-16W

*N = Plastic DIP; R-16N = 0.15" Small Outline IC (SOIC); R-16W = 0.3"

Small Outline IC (SOIC).

Table I. ADG438F Truth Table

A2 A1 A0 EN ON SWITCH

XXX0 NONE
00011
00112
01013
01114
10015
10116
11017
11118

X = Don’t Care

Table II. ADG439F Truth Table

A1 A0 EN ON SWITCH PAIR

X X 0 NONE
0011
0112
1013
1114

X = Don’t Care

ADG438F/ADG439F PIN CONFIGURATIONS

DIP/SOIC DIP/SOIC

1

A0

2

EN

3

V

SS

ADG438F

4

S1

TOP VIEW

5

S2

(Not to Scale)

S3

6
7

S4

DS8

89

16

A1

15

A2
GND

14

V

13

DD

S5

12

S6

11

S7

10

1

A0

2

EN

V

3

SS

4

S1A

5

S2A

6

S3A

7

S4A

89

DA

ADG439F

TOP VIEW

(Not to Scale)

16

A1

15

GND

14

V

DD

S1B

13
12

S2B

11

S3B

10

S4B
DB

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG438F/ADG439F features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. D

WARNING!

ESD SENSITIVE DEVICE

ADG438F/ADG439F

2000

1000

0

–15 –5 155010–10

500

1750

1500

1250

750

250

VD (VS) – Volts

R

ON

– V

TA = +258C

VDD = +5V
V

SS

= –5V

VDD = +10V
V

SS

= –10V

VDD = +15V
V

SS

= –15V

1m

1m

1p

–50 –30 5010–20 20–40

1n

30 40

100m

10m

10n

100n

10p

100p

–10 0

V

IN

– INPUT VOLTAGE – Volts

I

S

– INPUT LEAKAGE – A

OPERATING RANGE

VDD = 0V
V

SS

= 0V

V

D

= 0V

60

1m

1m

1p

–50 –30 5010–20 20–40

1n

30 40

100m

10m

10n

100n

10p

100p

–10 0

V

IN

– INPUT VOLTAGE – Volts

I

D

– OUTPUT LEAKAGE – A

OPERATING RANGE

VDD = +15V
VSS = –15V
VD = 0V

60

TERMINOLOGY

V

DD

V

SS

GND Ground (0 V) reference.

R

ON

∆R

ON

R

Drift Change in RON when temperature changes

ON

R

Match Difference between the RON of any two

ON

I

(OFF) Source leakage current when the switch is

S

I

(OFF) Drain leakage current when the switch is off.

D

I

, IS (ON) Channel leakage current when the switch is

D

V

(VS) Analog voltage on terminals D, S.

D

C

(OFF) Channel input capacitance for “OFF”

S

C

(OFF) Channel output capacitance for “OFF”

D

C

, CS (ON) “ON” switch capacitance.

D

C

IN

t

(EN) Delay time between the 50% and 90% points

ON

t

(EN) Delay time between the 50% and 90% points

OFF

t

TRANSITION

t

OPEN

V

INL

V

INH

I

(I

INL

INH

Off Isolation A measure of unwanted signal coupling

Charge Injection A measure of the glitch impulse transferred

I

DD

I

SS

Most positive power supply potential.

Most negative power supply potential.

Ohmic resistance between D and S.

RON variation due to a change in the analog
input voltage with a constant load current.

by one degree Celsius.

channels.

off.

on.

condition.

condition.

Digital input capacitance.

of the digital input and switch “ON”
condition.

of the digital input and switch “OFF”
condition.

Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.

“OFF” time measured between 80% points of
both switches when switching from one
address state to another.

Maximum input voltage for Logic “0”.

Minimum input voltage for Logic “1”.

) Input current of the digital input.

through an “OFF” channel.

from the digital input to the analog output
during switching.

Positive supply current.

Negative supply current.

Typical Performance Graphs

Figure 1. On Resistance as a Function of VD (VS)

Figure 2. Input Leakage Current as a Function of V
(Power Supplies OFF) During Overvoltage Conditions

Figure 3. Output Leakage Current as a Function of V
(Power Supplies ON) During Overvoltage Conditions

–4– REV. D

S

S

100

10

0.01
25 45 6555 7535 85 95 105

1

0.1

TEMPERATURE – 8C

LEAKAGE CURRENTS – nA

IS (OFF)

ID (OFF)

ID (ON)

VDD = +15V
V

SS

= –15V

V

D

= +10V

VS = –10V

260

240

100

10 1512 1311

120

14

t

ON

(EN)

VIN = +2V

220

200

180

160

140

t – ns

V

SUPPLY

– Volts

t

OFF

(EN)

t

TRANSITION

280

240

100

25 10565 8545

120

t

ON

(EN)

220

200

180

160

140

t – ns

TEMPERATURE – 8C

t

OFF

(EN)

t

TRANSITION

260

VDD = +15V
V

SS

= –15V

V

IN

= +5V

2000

1750

1500

1250

– V

1000

ON

R

750

500

250

0

–15 –5 155010–10

+858C

V

D

(VS) – Volts

+1058C

VDD = +15V

= –15V

V

SS

+258C

Figure 4. On Resistance as a Function of VD (VS) for
Different Temperatures

1m

100m

10m

1m

100n

10n

1n

– INPUT LEAKAGE – A

S

I

100p

10p

1p

–50 –30 6010–20 20–40 30 40–10 0 50

OPERATING RANGE

V

– INPUT VOLTAGE – Volts

S

VDD = +15V
V

= –15V

SS

= 0V

V

D

Figure 5. Input Leakage Current as a Function of V
(Power Supplies ON) During Overvoltage Conditions

ADG438F/ADG439F

Figure 7. Leakage Currents as a Function of Temperature

S

Figure 8. Switching Time vs. Power Supply

0.3

VDD = +15V
V

= –15V

–14 –6 142–2 6–10

SS

T

= +258C

A

VS, VD – Volts

0.2

0.1

0.0

LEAKAGE CURRENTS – nA
–0.1

–0.2

Figure 6. Leakage Currents as a Function of VD (VS)

IS (OFF)

ID (ON)

ID (OFF)

10

Figure 9. Switching Time vs. Temperature

–5–REV. D

ADG438F/ADG439F

Q1 Q2 Q3

+55V

OVERVOLTAGE

n-CHANNEL

MOSFET IS

OFF

Q1 Q2 Q3

–40V

OVERVOLTAGE

n-CHANNEL

MOSFET IS

ON

p-CHANNEL

MOSFET IS

OFF

V

D

S1
S2
S8

V

S

V

SS

V

DD

I

D

(OFF)

V

SS

V

DD

+0.8V

D

EN

A

THEORY OF OPERATION

The ADG438F/ADG439F multiplexers are capable of with­standing overvoltages from –40 V to +55 V, irrespective of
whether the power supplies are present or not. Each channel of
the multiplexer consists of an n-channel MOSFET, a p-channel
MOSFET and an n-channel MOSFET, connected in series.
When the analog input exceeds the power supplies, one of the
MOSFETs will switch off, limiting the current to sub-microamp
levels, thereby preventing the overvoltage from damaging any
circuitry following the multiplexer. Figure 12 illustrates the
channel architecture that enables these multiplexers to with­stand continuous overvoltages.

When an analog input of V

+ 1.2 V to VDD – 0.8 V is applied

SS

to the ADG438F/ADG439F, the multiplexer behaves as a
standard multiplexer, with specifications similar to a standard

multiplexer, for example, the on-resistance is 180 Ω typically.

However, when an overvoltage is applied to the device, one of
the three MOSFETs will turn off.

Figures 10 to 13 show the conditions of the three MOSFETs for
the various overvoltage situations. When the analog input ap­plied to an ON channel approaches the positive power supply
line, the n-channel MOSFET turns OFF since the voltage on
the analog input exceeds the difference between V

OVERVOLTAGE

+55V

n-CHANNEL

MOSFET IS

OFF

Q1 Q2 Q3

V

DD

V

SS

and the

DD

Figure 10. +55 V Overvoltage Input to the ON Channel

n-channel threshold voltage (VTN). When a voltage more nega­tive than V

is applied to the multiplexer, the p-channel

SS

MOSFET will turn off since the analog input is more negative
than the difference between V
voltage (V

TP

).

and the p-channel threshold

SS

When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will remain off when an overvoltage occurs.

Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches on
the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off since the gate to source voltage applied to this
MOSFET is negative.

During fault conditions, the leakage current into and out of the
ADG438F/ADG439F is limited to a few microamps. This pro­tects the multiplexer and succeeding circuitry from over stresses
as well as protecting the signal sources which drive the multi­plexer. Also, the other channels of the multiplexer will be
undisturbed by the overvoltage and will continue to operate
normally.

Figure 12. +55 V Overvoltage with Power OFF

Test Circuits

OVERVOLTAGE

–40V

n-CHANNEL

MOSFET IS

ON

Q1 Q2 Q3

p-CHANNEL

V

SS

V

DD

MOSFET IS

OFF

Figure 11. –40 V Overvoltage on an OFF Channel with
Multiplexer Power ON

I

DS

I

(OFF)

V1

S

V

S

= V1/I

R

ON

DS

Test Circuit 1. On Resistance

D

S

A

V

S

S1
S2
S8

V

D

Test Circuit 2. IS (OFF)

Figure 13. –40 V Overvoltage with Power OFF

V

V

V

DD

DD

SS

V

SS

D

EN

+0.8V

Test Circuit 3. ID (OFF)

–6– REV. D

ADG438F/ADG439F

V

DD

ADG438F*

GND

t

TRANSITION

0V0V

SS

S1

S8

D

90%

V

S

DD

V

DD

V

SS

V

SS

D

EN

ADDRESS

DRIVE (VIN)

V

OUT

3V

+0.8V

0V A

V

D

* SIMILAR CONNECTION FOR ADG439F

V
A2
A1
A0
EN

Test Circuit 6. Input Leakage Current
(with Power Supplies OFF)

50%

t

TRANSITION

90%

50%

V

S1
S2
S8

V

S

Test Circuit 4. ID (ON)

V

DD

V

SS

V

SS

DD

EN

I

(ON)

D

D

A

V

D

+2.4V

A

V

S

Test Circuit 5. Input Leakage Current

V

S1

S2
S8

(with Overvoltage)

V

V

V

A2

V

IN

50V

+2.4V

A1
A0

EN

* SIMILAR CONNECTION FOR ADG439F

DD

V

DD

S2 THRU S7

ADG438F*

GND

SS

SS

V

S1

S1

V

S8

S8

D

R

L

1MV

C

L

35pF

V

OUT

Test Circuit 7. Switching Time of Multiplexer, t

V

V

V

A2

V

50V

IN

+2.4V

A1
A0

ADG438F*

EN

* SIMILAR CONNECTION FOR ADG439F

DD

DD

S2 THRU S7

GND

SS

ADDRESS

V

OUT

3V

V

SS

S1

S8

D

R

L

1kV

V

S

C

L

35pF

DRIVE (VIN)

V

OUT

Test Circuit 8. Break-Before-Make Delay, t

V

V

DD

SS

V

V

A2
A1
A0

DD

S2 THRU S8

SS

S1

V

S

DRIVE (VIN)

ADG438F*

EN

V

50V

IN

* SIMILAR CONNECTION FOR ADG439F

GND

D

R

L

1kV

C

L

35pF

V

OUT

ENABLE

OUTPUT

3V

0V

V

O

0V

Test Circuit 9. Enable Delay, tON (EN), t

TRANSITION

OPEN

(EN)

OFF

50%

80%

0.9V

t

t

OPEN

O

ON

(EN)

50%

80%

0.9V

t

OFF

O

(EN)

–7–REV. D

ADG438F/ADG439F

A2

V

OUT

V

SS

V

DD

D

A1

A0

EN

GND

ADG438F*

1kV

V

SS

V

DD

S1

V

S

2.4V

S2

S8

1kV

CROSSTALK = 20 LOG V

OUT/VIN

* SIMILAR CONNECTION FOR ADG439F

16

9

81

0.3937 (10.00)

0.3859 (9.80)

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0500
(1.27)

BSC

0.0099 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

88
08

0.0196 (0.50)

0.0099 (0.25)

3 458

R

S

V

S

V

IN

* SIMILAR CONNECTION FOR ADG439F

V

DD

V

DD

A2
A1

ADG438F*

A0
EN

* SIMILAR CONNECTION FOR ADG439F

GND

V

V

SS

SS

A2
A1
A0
S

EN

S1
S8

D

V

DD

V

DD

ADG438F*

GND

R

L

1kV

V

SS

V

SS

D

C
1nF

V

OUT

L

3V

LOGIC

INPUT (VIN)

0V

V

OUT

Q

INJ

= CL 3 DV

OUT

D V

OUT

Test Circuit 10. Charge Injection

C1992c–0–2/00 (rev. D)

V

V

OUT

S

Test Circuit 11. OFF Isolation

0.210 (5.33)

0.160 (4.06)

0.115 (2.93)

16-Lead SOIC (R-16W)

(Wide Body)

0.4133 (10.50)

0.3977 (10.00)

16 9

MAX

0.022 (0.558)

0.014 (0.356)

Test Circuit 12. Channel-to-Channel Crosstalk

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Plastic (N-16)

0.840 (21.34)

0.745 (18.92)

16

1

PIN 1

0.100

(2.54)

BSC

9

8

0.070 (1.77)

0.045 (1.15)

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.26)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

16-Lead SOIC (R-16N)

(Narrow Body)

81

0.0118 (0.30)

0.0040 (0.10)

0.0500
(1.27)

BSC

PIN 1

0.0192 (0.49)

0.0138 (0.35)

0.1043 (2.65)

0.0926 (2.35)

0.2992 (7.60)

0.2914 (7.40)

SEATING
PLANE

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8°
0°

0.0157 (0.40)

x 45°

–8–

PRINTED IN U.S.A.

REV. D