LC2MOS
a
FEATURES
44 V Supply Maximum Ratings
15 V Analog Signal Range
Low On Resistance (<24 )
Ultralow Power Dissipation (3.9 W)
Low Leakage (<0.25 nA)
Fast Switching Times
<165 ns
t
ON
t
<130 ns
OFF
Break-Before-Make Switching Action
TTL/CMOS Compatible
Plug-in Replacement for DG411/DG412/DG413
APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
GENERAL DESCRIPTION
The ADG431, ADG432 and ADG433 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC
low power dissipation yet gives high switching speed and low on
resistance.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipation making the parts ideally suited for portable and battery
powered instruments.
The ADG431, ADG432 and ADG433 contain four independent SPST switches. The ADG431 and ADG432 differ only in
that the digital control logic is inverted. The ADG431 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG432. The ADG433
has two switches with digital control logic similar to that of the
ADG431 while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON
and has an input signal range which extends to the supplies. In
the OFF condition, signal levels up to the supplies are blocked.
All switches exhibit break before make switching action for use
in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital inputs.
2
MOS process which provides
Precision Quad SPST Switches
ADG431/ADG432/ADG433
FUNCTIONAL BLOCK DIAGRAMS
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG433
IN1
IN2
ADG432
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
IN1
IN2
ADG431
IN3
IN4
SWITCHES SHOWN FOR A LOGIC "1" INPUT
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG431, ADG432 and ADG433 are fabricated on an
enhanced LC
2
MOS process giving an increased signal range
which extends fully to the supply rails.
2. Ultralow Power Dissipation
3. Low R
ON
4. Break-Before-Make Switching
This prevents channel shorting when the switches are configured as a multiplexer.
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG431, ADG432, and ADG433 can be operated from a
single rail power supply. The parts are fully specified with a
single 12 V power supply and will remain functional with
single supplies as low as 5 V.
S1
D1
S2
D2
S3
D3
S4
D4
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
ADG431/ADG432/ADG433–SPECIFICATIONS
1
Dual Supply
(VDD = +15 V 10%, VSS = –15 V 10%, VL = +5 V 10%, GND = O V, unless otherwise noted.)
B Version
–40C to
Parameter +25C +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to V
R
ON
17 Ω typ VD = ± 8.5 V, IS = –10 mA;
SS
24 26 Ω max V
R
vs. VD (VS) 15 % typ
ON
Drift 0.5 %/°C typ
R
ON
V
= +13.5 V, VSS = –13.5 V
DD
RON Match 5 % typ VD = 0 V, IS = –10 mA
LEAKAGE CURRENTS V
Source OFF Leakage I
(OFF) ± 0.05 nA typ VD = ± 15.5 V, VS = ⫿15.5 V;
S
= +16.5 V, VSS = –16.5 V
DD
± 0.25 ± 2 nA max Test Circuit 2
Drain OFF Leakage I
(OFF) ±0.05 nA typ VD = ± 15.5 V, VS = ⫿15.5 V;
D
± 0.25 ± 2 nA max Test Circuit 2
Channel ON Leakage I
, IS (ON) ± 0.1 nA typ VD = VS = ± 15.5 V;
D
± 0.35 ± 3 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.4 V min
0.8 V max
Input Current
I
INL
or I
INH
0.005 µA typ VIN = V
INL
or V
INH
± 0.02 µA max
CIN Digital Input Capacitance 9 pF typ
DYNAMIC CHARACTERISTICS
t
ON
1
90 ns typ RL = 300 Ω, CL = 35 pF;
165 ns max V
t
OFF
60 ns typ RL = 300 Ω, CL = 35 pF;
130 ns max V
Break-Before-Make Time Delay, t
D
25 ns typ RL = 300 Ω, CL = 35 pF;
(ADG433 Only) V
VDD = +15 V, VSS = –15 V
= ± 10 V; Test Circuit 4
S
= ± 10 V; Test Circuit 4
S
= VS2 = +10 V;
S1
Test Circuit 5
Charge Injection 5 pC typ V
= 0 V, RS = 0 Ω, CL = 10 nF;
S
Test Circuit 6
OFF Isolation 68 dB typ R
= 50 Ω, CL = 5 pF, f = 1 MHz;
L
Test Circuit 7
Channel-to-Channel Crosstalk 85 dB typ R
= 50 Ω, CL = 5 pF, f = 1 MHz;
L
Test Circuit 8
(OFF) 9 pF typ f = 1 MHz
C
S
C
(OFF) 9 pF typ f = 1 MHz
D
CD, CS (ON) 35 pF typ f = 1 MHz
POWER REQUIREMENTS V
= +16.5 V, VSS = –16.5 V
DD
Digital Inputs = 0 V or 5 V
I
DD
0.0001 µA typ
0.1 0.2 µA max
I
SS
0.0001 µA typ
0.1 0.2 µA max
I
L
0.0001 µA typ
0.1 0.2 µA max
Power Dissipation 7.7 µW max
NOTES
1
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. C
ADG431/ADG432/ADG433
Single Supply
(VDD = 12 V 10%, VSS = O V, VL = 5 V 10%, GND = O V, unless otherwise noted)
B Version
–40C to
Parameter +25C +85C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
R
ON
28 Ω typ 0 < VD < 8.5 V, IS = –10 mA;
DD
42 45 Ω max V
R
vs. VD (VS) 20 % typ
ON
Drift 0.5 %/°C typ
R
ON
V
= 10.8 V
DD
RON Match 5 % typ VD = 0 V, IS = –10 mA
LEAKAGE CURRENTS V
Source OFF Leakage I
(OFF) ± 0.04 nA typ VD = 12.2/1 V, VS = 1/12.2 V;
S
= 13.2 V
DD
± 0.25 ± 2 nA max Test Circuit 2
Drain OFF Leakage I
(OFF) ±0.04 nA typ VD = 12.2/1 V, VS = 1/12.2 V;
D
± 0.25 ± 2 nA max Test Circuit 2
Channel ON Leakage I
, Is (ON) ± 0.01 nA typ VD = VS = 12.2 V/1 V;
D
± 0.3 ± 3 nA max Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
INL
INH
2.4 V min
0.8 V max
Input Current
I
INL
or I
INH
0.005 µA typ VIN = V
INL
or V
INH
± 0.01 µA max
CIN Digital Input Capacitance 9 pF typ
DYNAMIC CHARACTERISTICS
t
ON
1
165 ns typ RL = 300 Ω, CL = 35 pF;
240 ns max V
t
OFF
60 ns typ RL = 300 Ω, CL = 35 pF;
115 ns max V
Break-Before-Make Time Delay, t
D
25 ns typ RL = 300 Ω, CL = 35 pF;
(ADG433 Only) V
Charge Injection 25 pC typ V
VDD = 12 V, VSS = 0 V
= 8 V; Test Circuit 4
S
= 8 V; Test Circuit 4
S
= VS2 = 10 V; Test Circuit 5
S1
= 0 V, RS = 0 Ω, CL = 10 nF;
S
Test Circuit 6
OFF Isolation 68 dB typ R
= 50 Ω, CL = 5 pF, f = 1 MHz;
L
Test Circuit 7
Channel-to-Channel Crosstalk 85 dB typ R
= 50 Ω, CL = 5 pF, f = 1 MHz;
L
Test Circuit 8
(OFF) 9 pF typ f = 1 MHz
C
S
C
(OFF) 9 pF typ f = 1 MHz
D
CD, CS (ON) 35 pF typ f = 1 MHz
POWER REQUIREMENTS V
= 13.2 V
DD
Digital Inputs = 0 V or 5 V
I
DD
0.0001 µA typ
0.03 0.1 µA max
I
L
0.0001 µA typ
0.03 0.1 µA max V
= 5.25 V
L
Power Dissipation 1.9 µW max
NOTES
1
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
Truth Table (ADG431/ADG432)
ADG431 In ADG432 In Switch Condition
01ON
1 0 OFF
REV. C
Truth Table (ADG433)
Logic Switch 1, 4 Switch 2, 3
0 OFF ON
1 ON OFF
–3–
ADG431/ADG432/ADG433
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted.)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
DD
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
SS
V
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
L
Analog, Digital Inputs
2
. . . . . . . . . . VSS – 2 V to VDD + 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . 470 mW
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W
θ
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 600 mW
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
(DIP/SOIC)
IN1
V
GND
IN4
D1
S1
SS
S4
D4
1
2
ADG431
3
ADG432
4
ADG433
TOP VIEW
5
(Not to Scale)
6
7
8
IN2
16
D2
15
S2
14
V
13
DD
V
12
L
S3
11
D3
10
IN3
9
Model Temperature Range Package Option
ADG431BN –40°C to +85°C N-16
ADG431BR –40°C to +85°C R-16A
ADG431ABR –40°C to +85°C R-16A
ADG432BN –40°C to +85°C N-16
ADG432BR –40°C to +85°C R-16A
ADG432ABR –40°C to +85°C R-16A
ADG433BN –40°C to +85°C N-16
ADG433BR –40°C to +85°C R-16A
ADG433ABR –40°C to +85°C R-16A
NOTES
1
N = Plastic DIP; R = 0.15" Small Outline IC (SOIC).
2
Trench isolated, latch-up proof parts. See Trench Isolation section.
ORDERING GUIDE
1
2
2
2
V
DD
V
SS
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may be
connected to GND.
V
L
Logic power supply (5 V).
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R
ON
Ohmic resistance between D and S.
RON vs. VD (VS) The variation in RON due to a change in the ana-
log input voltage with a constant load current.
R
Drift Change in RON vs. temperature.
ON
R
Match Difference between the RON of any two switches.
ON
IS (OFF) Source leakage current with the switch “OFF.”
I
(OFF) Drain leakage current with the switch “OFF.”
D
ID, IS (ON) Channel leakage current with the switch “ON.”
VD (VS) Analog voltage on terminals D, S.
TERMINOLOGY
CS (OFF) “OFF” switch source capacitance.
C
(OFF) “OFF” switch drain capacitance.
D
CD, CS (ON) “ON” switch capacitance.
C
IN
t
ON
t
OFF
t
D
Crosstalk A measure of unwanted signal which is coupled
Off Isolation A measure of unwanted signal coupling through an
Charge A measure of the glitch impulse transferred from the
Injection digital input to the analog output during switching.
–4–
Input Capacitance to ground of a digital input.
Delay between applying the digital control input
and the output switching on.
Delay between applying the digital control input
and the output switching off.
“OFF” time or “ON” time measured between the
90% points of both switches, when switching
from one address state to another.
through from one channel to another as a result
of parasitic capacitance.
“OFF” switch.
REV. C
Typical Performance Characteristics–ADG431/ADG432/ADG433
50
40
30
–
ON
R
20
10
VDD = +15V
V
= –15V
SS
0
–20 –10
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
VDD = +5V
V
SS
VDD = +10V
V
= –10V
SS
= –5V
01020
TA = 25C
= 5V
V
L
VDD = +12V
V
= –12V
SS
TPC 1. On Resistance as a Function of VD (VS) Dual
Supplies
50
VDD = +15V
V
= –15V
SS
V
= +5V
40
30
–
ON
R
20
10
L
125C
85C
25C
50
40
30
–
ON
R
20
VDD = 5V
= 0V
V
SS
V
DD
V
SS
= 10V
= 0V
VDD = 12V
= 0V
V
SS
TA = 25C
= 5V
V
L
10
0
05
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
VDD = 15V
= 0V
V
SS
10 15 20
TPC 4. On Resistance as a Function of VD (VS) Single
Supply
100mA
VDD = +15V 4 SW
V
10mA
100A
SUPPLY
I
10A
1mA
1A
V
SS
= +5V
L
= –15V
1 SW
I+, I–
I
L
0
–20 –10
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
01020
TPC 2. On Resistance as a Function of VD (VS) for Different
Temperatures
10
VDD = +15V
V
= –15V
SS
V
= +5V
L
0.1
LEAKAGE CURRENT – nA
0.01
0.001
1
VS = 15V
V
D
20 12040
= 15V
(OFF)
I
S
I
(OFF)
D
ID (ON)
60 80 100
TEMPERATURE – C
140
TPC 3. Leakage Currents as a Function of Temperature
100nA
10
1k 10k 100k 1M
FREQUENCY – Hz
TPC 5. Supply Current vs. Input Switching Frequency
0.04
VDD = +15V
V
= –15V
SS
T
= +25C
V
0.02
0.00
LEAKAGE CURRENT – nA
–0.02
–0.04
–20 –10
A
= +5V
L
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
ID (ON)
(OFF)
I
S
I
(OFF)
D
01020
TPC 6. Leakage Currents as a Function of VD (VS)
10M100
REV. C
–5–
ADG431/ADG432/ADG433
+15V
–15V
2200pF
R
C
75
C
C
1000pF
C
H
2200pF
V
OUT
ADG431
ADG432
ADG433
SW1
SW2
S
S
D
D
+15V +5V
–15V
AD845
+15V
–15V
V
IN
AD711
120
100
80
OFF ISOLATION – dB
60
40
100 10M1k
10k 100k 1M
FREQUENCY – Hz
TPC 7. Off Isolation vs. Frequency
110
100
90
80
CROSSTALK – dB
70
60
100 10M1k
10k 100k 1M
FREQUENCY – Hz
TPC 8. Crosstalk vs. Frequency
VDD = +15V
V
= –15V
SS
V
= +5V
L
VDD = +15V
V
= –15V
SS
V
= +5V
L
V
G
V
S
P
N
+
–
P-CHANNEL
T
R
E
N
C
H
V
D
T
+
P
R
E
N
C
H
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
V
S
N
P
+
–
V
G
N-CHANNEL
V
D
T
+
N
R
E
N
C
H
Figure 1. Trench Isolation
APPLICATION
Figure 2 illustrates a precise, fast sample-and-hold circuit.
An AD845 is used as the input buffer while the output operational amplifier is an AD711. During the track mode, SW1 is
closed and the output V
follows the input signal VIN. In
OUT
the hold mode, SW1 is opened and the signal is held by the
hold capacitor C
.
H
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a
polystyrene hold capacitor. The droop rate for the circuit
shown is typically 30 µV/µs.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differential effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensation network R
and CC. This compensation network also reduces
C
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal error
has a maximum value of 5 mV over the ±10 V input range. Both
the acquisition and settling times are 850 ns.
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors from a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. A silicon-controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current which, in turn, leads to latch up.
With trench isolation, this diode is removed, the result being a
latch-up proof switch.
–6–
Figure 2. Fast, Accurate Sample-and-Hold
REV. C
Test Circuits
V
S
I
DS
V1
SD
RON = V1/I
DS
ADG431/ADG432/ADG433
I
IS (OFF)
V
S
A
SD
(OFF)
D
A
V
D
V
S
SD
ID (ON)
A
V
D
Test Circuit 1. On Resistance
0.1F 0.1F
V
S
0.1F 0.1F
V
S1
V
S2
S1 D1
S2
IN1, IN2
V
IN
GND
+15V +5V
V
DDVL
V
0.1F
–15V
IN
SS
Test Circuit 2. Off Leakage
+15V +5V
3V
V
DDVL
SD
V
GND
SS
0.1F
–15V
R
L
300
C
L
35pF
V
OUT
V
ADG431
IN
V
IN
V
OUT
3V
ADG432
t
Test Circuit 4. Switching Times
3V
V
IN
0V
V
OUT1
V
V
OUT1
OUT2
0V
90%
0V
R
C
L1
V
C
L2
35pF
OUT2
300
D2
R
L2
300
L1
35pF
Test Circuit 5. Break-Before-Make Time Delay
50% 50%
50% 50%
90% 90%
ON
t
OFF
50% 50%
90%
t
D
Test Circuit 3. On Leakage
90%
90%
t
D
REV. C
+15V +5V
V
DDVL
C
L
10nF
V
OUT
R
S
V
S
SD
IN
GND
V
–15V
SS
3V
V
IN
V
OUT
Q
INJ
= CL V
OUT
V
OUT
Test Circuit 6. Charge Injection
–7–
ADG431/ADG432/ADG433
+15V +5V
0.1F 0.1F
V
DDVL
SD
V
S
IN
V
IN
V
GND
SS
0.1F
–15V
Test Circuit 7. Off Isolation
V
OUT
R
50
L
V
S
V
OUT
Test Circuit 8. Channel-to-Channel Crosstalk
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
R
50
0.1F 0.1F
V
IN1
L
+15V +5V
V
DDVL
SD
S
D
V
GND
SS
0.1F
–15V
50
V
IN2
NC
CHANNEL-TO-CHANNEL
CROSSTALK = 20 LOG V
S/VOUT
C00050b–0–3/01(C)
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
16-Lead Plastic DIP (Narrow)
(N-16)
0.840 (21.34)
0.745 (18.92)
16
18
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
9
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.26)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
16-Lead SOIC
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
16 9
PIN 1
0.0192 (0.49)
0.0500
(1.27)
0.0138 (0.35)
BSC
0.2440 (6.20)
81
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8
0
0.0500 (1.27)
0.0160 (0.41)
x 45
ADG431/ADG432/ADG433–Revision History
Location Page
Data Sheet changed from REV. B to REV. C.
Changes to Specifications Table (Dual Supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to Specifications Table (Single Supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
16-Lead Cerdip deleted from Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
–8–
REV. C
PRINTED IN U.S.A.
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