Datasheet ADG3301 Datasheet (ANALOG DEVICES)

www.BDTIC.com/ADI

Low Voltage 1.15 V to 5.5 V, Single-Channel

FEATURES

Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 5 µA
No direction pin

APPLICATIONS

SPI®, MICROWIRE® level translation
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communication devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
Portable POS systems
Low cost serial interfaces

GENERAL DESCRIPTION

Bidirectional Logic Level Translator

ADG3301

FUNCTIONAL BLOCK DIAGRAM

V

CCA

A

EN

PRODUCT HIGHLIGHTS

GND

Figure 1.

V

CCY

ADG3301

Y

05517-001

The ADG3301 is a single-channel, bidirectional logic level
translator. It can be used in multivoltage digital system applica­tions such as data transfer between a low voltage DSP/controller
and a higher voltage device. The internal architecture allows the
device to perform bidirectional logic level translation without an
additional signal to set the direction in which the translation
takes place.

The voltage applied to V
the device, while V
operation, V

CCY

must always be less than V

CCA

compatible logic signals applied to the A pin appear as V
compatible levels on the Y pin. Similarly, V
levels applied to the Y pin appear as V

sets the logic levels on the A side of

CCA

sets the levels on the Y side. For proper

. The V

CCY

-compatible logic

CCY

-compatible logic levels

CCA

CCA

-

CCY

-

on the A pin. The enable pin (EN) provides three-state operation
on both the A pin and the Y pin. When the device enable pin is
pulled low, the terminals on both sides of the device are in the
high impedance state. The EN pin is referred to the V

CCA

supply

voltage and driven high for normal operation.

The ADG3301 is available in a compact 6-lead SC70 package
and is guaranteed to operate over the 1.15 V to 5.5 V supply
voltage range and extended −40°C to +85°C temperature range.

1. Bidirectional level translation.

2. Fully guaranteed over the 1.15 V to 5.5 V supply range.

3. No direction pin.

4. Compact 6-lead SC70 package.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADG3301

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights........................................................................... 1

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics............................................. 8

Test Ci r c ui t s..................................................................................... 12

Te r mi n ol o g y .................................................................................... 15

REVISION HISTORY

12/05—Revision 0: Initial Version

Theory of Operation ...................................................................... 16

Level Translator Architecture................................................... 16

Input Driving Requirements..................................................... 16

Output Load Requirements ...................................................... 16

Enable Operation ....................................................................... 16

Power Supplies ............................................................................ 16

Data Rate ..................................................................................... 17

Applications..................................................................................... 18

Layout Guidelines....................................................................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. 0 | Page 2 of 20

ADG3301

www.BDTIC.com/ADI

SPECIFICATIONS

V

= 1.65 V to 5.5 V, V

CCY

Table 1.

Parame ter

1

LOGIC INPUTS/OUTPUTS

A Side

Input High Voltage

V

Input Low Voltage
Output High Voltage V
Output Low Voltage V
Capacitance

3

Leakage Current I

Y Side

Input High Voltage
Input Low Voltage3 V
Output High Voltage V
Output Low Voltage V
Capacitance

3

Leakage Current I

Enable (EN)

Input High Voltage
V
Input Low Voltage
Leakage Current I
Capacitance
Enable Time

3

3

SWITCHING CHARACTERISTICS3

3.3 V ± 0.3 V ≤ V

CCA

≤ V

A→Y Level Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

Y→A Level Translation

Propagation Delay
Rise Time

Fall Time
Maximum Data Rate
Part-to-Part Skew

1.8 V ± 0.15 V ≤ V

CCA

A→Y Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

≤ V

CCA

3

3

3

3

3

, V

CCY

CCY

= 1.15 V to V

, GND = 0 V. All specifications T

CCY

MIN

to T

, unless otherwise noted.

MAX

Symbol Conditions Min Typ2Max Unit

V

IHA

IHA

V

ILA

VY = V

OHA

VY = 0 V, IOL = 20 µA, see Figure 27 0.4 V

OLA

C

A

LA, HiZ

V

IHY

ILY

OHY

OLY

CY

LY, H iZ

V

IHEN

IHEN

V

ILEN

LEN

C

EN

t

EN

= 5 V ± 0.5 V

CCY

V

= 1.15 V V

CCA

V

= 1.2 V to 5.5 V 0.65 × V

CCA

− 0.3 V

CCA

CCA

0.35 × V
, IOH = 20 µA, see Figure 27 V

CCY

− 0.4 V

CCA

f = 1 MHz, EN = 0, see Figure 32 9 pF
VA = 0 V/V

0.65 × V

, EN = 0, see Figure 29 ±1 µA

CCA

V

CCY

0.35 × V

VA = V

, IOH = 20 µA, see Figure 28 V

CCA

− 0.4 V

CCY

VA = 0 V, IOL = 20 µA, see Figure 28 0.4 V
f = 1 MHz, EN = 0, see Figure 33 6 pF
VY = 0 V/V

V

CCA

V

CCA

, EN = 0, see Figure 30 ±1 µA

CCY

= 1.15 V V
= 1.2 V to 5.5 V 0.65 × V

− 0.3 V

CCA

V

CCA

0.35 × V

VEN = 0 V/V

, VA = 0 V, see Figure 31 ±1 µA

CCA

3 pF
RS = RT = 50 Ω, VA = 0 V/V

= 0 V/V

V

Y

= RT = 50 Ω, CL = 50 pF,

R

S

(Y→A), see Figure 34

CCY

(A→Y),

CCA

1 1.8 µs

see Figure 35

t

P, A→Y

t

R, A→Y

t

F, A→Y

D

MAX, A→Y

t

PPSKEW, A→Y

6 10 ns
2 3.5 ns
2 3.5 ns
50 Mbps
3 ns

= RT = 50 Ω, CL = 15 pF,

R

S

see Figure 36

t

P, Y→A

t

R, Y→A

t

F, Y→A

D

MAX, Y→A

t

PPSKEW, Y→A

, V

= 3.3 V ± 0.3 V

CCY

4 7 ns
1 3 ns

3 7 ns
50 Mbps
2 ns

= RT = 50 Ω, CL = 50 pF,

R

S

see Figure 35

t

P, A→Y

t

R, A→Y

t

F, A→Y

D

MAX, A→Y

t

PPSKEW, A→Y

8 11 ns
2 5 ns
2 5 ns
50 Mbps
4 ns

CCA

CCY

CCA

V

V

V

Rev. 0 | Page 3 of 20

ADG3301

www.BDTIC.com/ADI

Parame ter

1

Y→A Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

1.15 V to 1.3 V ≤ V
A→Y Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

Y→A Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

1.15 V to 1.3 V ≤ V
A→Y Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

Y→A Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

2.5 V ± 0.2 V ≤ V
A→Y Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

Y→A Translation

Propagation Delay
Rise Time
Fall Time
Maximum Data Rate
Part-to-Part Skew

CCA

CCA

CCA

≤ V

≤ V

≤ V

Symbol Conditions Min Typ2Max Unit

= RT = 50 Ω, CL = 15 pF,

R

S

see Figure 36

t

P, Y→A

t

R, Y→A

t

F, Y→A

D

MAX, Y→A

t

PPSKEW, Y→A

, V

= 3.3 V ± 0.3 V

CCY

CCY

5 8 ns
2 3.5 ns
2 3.5 ns
50 Mbps
3 ns

= RT = 50 Ω, CL = 50 pF,

R

S

see Figure 35

t

P, A→Y

t

R, A→Y

t

F, A→Y

D

MAX, A→Y

t

PPSKEW, A→Y

9 18 ns
3 5 ns
2 5 ns
40 Mbps
10 ns

= RT = 50 Ω, CL = 15 pF,

R

S

see Figure 36

t

P, Y→A

t

R, Y→A

t

F, Y→A

D

MAX, Y→A

t

PPSKEW, Y→A

, V

= 1.8 V ± 0.3 V

CCY

CCY

5 9 ns
2 4 ns
2 4 ns
40 Mbps
4 ns

= RT = 50 Ω, CL = 50 pF,

R

S

see Figure 35

t

P, A→Y

t

R, A→Y

t

F, A→Y

D

MAX, A→Y

t

PPSKEW, A→Y

12 25 ns
7 12 ns
3 5 ns
25 Mbps
15 ns

= RT = 50 Ω, CL = 15 pF,

R

S

see Figure 36

t

P, Y→A

t

R, Y→A

t

F, Y→A

D

MAX, Y→A

t

PPSKEW, Y→A

, V

= 3.3 V ± 0.3 V

CCY

CCY

14 35 ns
5 16 ns

2.5 6.5 ns
25 Mbps

23.5 ns

= RT = 50 Ω, CL = 50 pF,

R

S

see Figure 35

t

P, A→Y

t

R, A→Y

t

F, A→Y

D

MAX, A→Y

t

PPSKEW, A→Y

7 10 ns

2.5 4 ns
2 5 ns
60 Mbps
4 ns

= RT = 50 Ω, CL = 15 pF,

R

S

see Figure 36

t

P, Y→A

t

R, Y→A

t

F, Y→A

D

MAX, Y→A

t

PPSKEW, Y→A

5 8 ns
1 4 ns
3 5 ns
60 Mbps
3 ns

Rev. 0 | Page 4 of 20

ADG3301

www.BDTIC.com/ADI

Parame ter

1

Symbol Conditions Min Typ2Max Unit

POWER REQUIREMENTS

Power Supply Voltages V
V
Quiescent Power Supply Current I

I

Three-State Mode Power Supply Current I
I

1

Temperature range for the B version is −40°C to +85°C.

2

All typical values are at TA = 25°C, unless otherwise noted.

3

Guaranteed by design, not subject to production test.

CCA

CCY

CCA

CCY

HiZA

HiZY

V

CCA

≤ V

CCY

1.15 5.5 V

1.65 5.5 V
VA = 0 V/V

= V

V

CCA

VA = 0 V/V
V

= V

CCA

V

= V

CCA

V

= V

CCA

, VY = 0 V/V

CCA

= 5.5 V, EN = 1

CCY

, VY = 0 V/V

CCA

= 5.5 V, EN = 1

CCY

= 5.5 V, EN = 0 0.1 5 µA

CCY

= 5.5 V, EN = 0 0.1 5 µA

CCY

CCY

CCY

,

,

0.17 5 µA

0.27 5 µA

Rev. 0 | Page 5 of 20

ADG3301

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

V

to GND −0.3 V to +7 V

CCA

V

to GND V

CCY

Digital Inputs (A) −0.3 V to V
Digital Inputs (Y) −0.3 V to V
EN to GND −0.3 V to +7 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance (4-Layer Board)

6-Lead SC70 494.1°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (< 20 sec) 260(+0/−5)°C

to +7 V

CCA

+ 0.3 V

CCA

+ 0.3 V

CCY

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating may be applied at any one
time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 20

ADG3301

V

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

CCA

ADG3301

A 2

TOP VIEW

(Not to Scale)

GND 3

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

CCA

Power Supply Voltage Input for the A I/O Pin (1.15 V ≤ V
2 A Input/Output A. Referenced to V
3 GND Ground (0 V).
4 EN Active High Enable Input.
5 Y Input/Output Y. Referenced to V
6 V

CCY

Power Supply Voltage Input for the Y I/O Pin (1.65 V ≤ V

CCY

CCA

6

V

CCY

Y5

EN4

05517-002

≤ V

CCA

CCY).

.

.

≤ 5.5V).

CCY

Rev. 0 | Page 7 of 20

ADG3301

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
TA = 25°C

1 CHANNEL

0.9

= 50pF

C

L

0.8

0.7

0.6

(mA)

0.5

CCA

I

0.4

0.3

0.2

0.1

0

0 5 10 15 20 25 30 35 40 45 50

Figure 3. I

V

= 3.3V, V

CCA

V

CCA

DATA RATE (Mbps)

vs. Data Rate (A→Y Level Translation)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

= 1.8V

CCY

CCY

10

TA = 25°C
1 CHANNEL

9

= 50pF

C

L

8

7

6

(mA)

5

CCY

I

4

3

2

1

0

0 5 10 15 20 25 30 35 40 45 50

Figure 4. I

V

= 3.3V, V

CCA

V

DATA RATE (Mbps)

vs. Data Rate (A→Y Level Translation)

CCY

CCA

= 5V

CCY

V

= 1.2V, V

CCA

= 1.8V, V

= 1.8V

CCY

3.0

TA = 25°C
1 CHANNEL
C

= 15pF

L

2.5

V

= 3.3V, V

2.0

(mA)

1.5

CCA

I

1.0

0.5

0

0 5 10 15 20 25 30 35 40 45 50

Figure 5. I

CCA

V

CCA

DATA RATE (Mbps)

vs. Data Rate (Y→A Level Translation)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

CCY

= 1.8V

CCY

CCY

= 3.3V

= 3.3V

= 3.3V

05517-003

05517-004

05517-005

3.0
TA = 25°C
1 CHANNEL
C

= 15pF

L

2.5

2.0

V

= 3.3V, V

CCA

(mA)

1.5

CCY

I

1.0

0.5

0

0 5 10 15 20 25 30 35 40 45 50

Figure 6. I

vs. Data Rate (Y→A Level Translation)

CCY

V

DATA RATE (Mbps)

CCA

CCY

V

CCA

= 1.2V, V

= 5V

= 1.8V, V

CCY

= 1.8V

1.6
TA =25°C
1 CHANNEL

1.4

V

= 1.2V

CCA

V

= 1.8V

CCY

1.2

1.0

(mA)

0.8

CCY

I

0.6

0.4

0.2

0

13 23 33 43 53 63 73

CAPACITIVE LOAD (pF)

Figure 7. I

vs. Capacitive Load at Pin Y for A→Y

CCY

20Mbps

10Mbps

5Mbps

1Mbps

(1.2 V→1.8 V) Level Translation

1.0
TA = 25°C

1 CHANNEL

(mA)

CCA

I

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

= 1.2V

V

CCA

=1.8V

V

CCY

20Mbps

10Mbps
5Mbps

0

13 23 33 43 53

Figure 8. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y→A

CCA

1Mbps

(1.8 V→1.2 V) Level Translation

CCY

= 3.3V

05517-006

05517-007

05517-008

Rev. 0 | Page 8 of 20

ADG3301

www.BDTIC.com/ADI

9

TA = 25°C
1 CHANNEL

8

V

= 1.8V

CCA

V

= 3.3V

CCY

7

6

5

(mA)

4

CCY

I

3

2

1

0

13 23 33 43 53 63 73

Figure 9. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin Y for A→Y

CCY

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

(1.8 V→3.3 V) Level Translation

5.0

TA = 25°C
1 CHANNEL

4.5

V

= 1.8V

CCA

V

= 3.3V

CCY

0

13 23 33 43 53

Figure 10. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y→A

CCA

(mA)

CCA

I

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

(3.3 V→1.8 V) Level Translation

12

TA = 25°C
1 CHANNEL
V

= 3.3V

CCA

10

= 5V

V

CCY

8

6

(mA)

CCY

I

4

2

0

13 23 33 43 53 63 73

Figure 11. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin Y for A→Y

CCY

(3.3 V→5 V) Level Translation

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

50Mbps

30Mbps

20Mbps

10Mbps

5Mbps

05517-009

05517-010

05517-011

7

TA = 25°C
1 CHANNEL
V

= 3.3V

6

CCA

V

= 5V

CCY

5

4

(mA)

3

CCA

I

2

1

0

13 23 33 43 53

Figure 12. I

CAPACITIVE LOAD (pF)

vs. Capacitive Load at Pin A for Y→A

CCA

50Mbps

30Mbps
20Mbps

10Mbps

5Mbps

(5 V→3.3 V) Level Translation

10

TA = 25°C
1 CHANNEL

9

DATA RATE = 50kbps

8

7

6

5

4

RISE TIME(ns)

3

2

1

0

13 23 33 43 53 63 73

V

= 1.2V, V

CCA

V

= 1.8V, V

CCA

V

= 3.3V, V

CCA

CAPACITIVE LOAD (pF)

CCY

= 1.8V

CCY

CCY

Figure 13. Rise Time vs. Capacitive Load at Pin Y

(A→Y Level Translation)

4.0
TA = 25°C
1 CHANNEL

3.5

DATA RATE = 50kbps

3.0

2.5

2.0

1.5

FALL TIME (ns)

1.0

0.5

0

13 23 33 43 53 63 73

V

= 1.2V, V

CCA

V

CCA

V

CCA

CAPACITIVE LOAD (pF)

= 1.8V

CCY

= 1.8V, V

= 3.3V, V

Figure 14. Fall Time vs. Capacitive Load at Pin Y

(A→Y Level Translation)

= 3.3V

= 5V

CCY

CCY

= 3.3V

= 5V

05517-012

05517-013

05517-014

Rev. 0 | Page 9 of 20

ADG3301

www.BDTIC.com/ADI

10

TA = 25°C
1 CHANNEL

9

DATA RATE = 50kbps

8

7

6

5

4

RISE TIME (ns)

3

2

1

0

13 18 23 28 33 38 43 48 53

V

= 1.2V, V

CCA

CAPACITIVE LOAD (pF)

CCY

= 1.8V

V

CCA

= 1.8V, V

V

CCA

CCY

= 3.3V, V

Figure 15. Rise Time vs. Capacitive Load at Pin A

(Y→A Level Translation)

4.0
TA = 25°C
1 CHANNEL

3.5

DATA RATE = 50kbps

3.0

2.5

V

= 1.2V, V

CCA

2.0

1.5

FALL TIME (ns)

1.0

0.5

0

13 18 23 28 33 38 43 48 53

= 1.8V

CCY

CAPACITIVE LOAD (pF)

V

CCA

V

= 1.8V, V

= 3.3V, V

CCA

CCY

Figure 16. Fall Time vs. Capacitive Load at Pin A

(Y→A Level Translation)

14

TA = 25°C
1 CHANNEL
DATA RATE = 50kbps

12

10

8

6

4

PROPAGATION DELAY (ns)

2

0

13 23 33 43 53 63

V

CCA

CAPACITIVE LOAD (pF)

Figure 17. Propagation Delay (t

V

= 1.2V, V

CCA

= 1.8V, V

= 3.3V

CCY

V

= 3.3V, V

CCA

) vs. Capacitive Load at Pin Y

PLH

CCY

CCY

(A→Y Level Translation)

= 3.3V

CCY

= 3.3V

CCY

= 1.8V

= 5V

= 5V

= 5V

05517-015

05517-016

73

05517-017

12

DATA RATE = 50kbps
T

= 25°C

A

1 CHANNEL

10

8

6

4

PROPAGATION DELAY (ns)

2

0

13 23 33 43 53 63 73

CAPACITIVE LOAD (pF)

Figure 18. Propagation Delay (t

V

= 1.2V, V

CCA

V

CCA

V

CCA

) vs. Capacitive Load at Pin Y

PHL

CCY

= 1.8V, V

= 3.3V, V

(A→Y Level Translation)

9

TA = 25°C
1 CHANNEL

8

DATA RATE = 50kbps

7

6

5

4

3

V

= 1.8V, V

CCA

2

PROPAGATION DELAY (ns)

1

0

13 18 23 28 33 38 43 48 53

= 3.3V

CCY

CAPACITIVE LOAD (pF)

Figure 19. Propagation Delay (t

V

= 1.2V, V

CCA

V

CCA

) vs. Capacitive Load at Pin A

PLH

= 3.3V, V

CCY

CCY

(Y→A Level Translation)

9

TA = 25°C
1 CHANNEL

8

DATA RATE = 50kbps

7

6

5

4

V

3

PROPAGATION DELAY (ns)

2

1

0

13 18 23 28 33 38 43 48 53

CCA

CAPACITIVE LOAD (pF)

Figure 20. Propagation Delay (t

V

= 1.2V, V

CCA

= 1.8V, V

= 3.3V

CCY

V

= 3.3V, V

CCA

PHL

CCY

) vs. Capacitive Load at Pin A

CCY

= 5V

(Y→A Level Translation)

= 1.8V

CCY

CCY

= 1.8V

= 5V

= 1.8V

= 3.3V

= 5V

05517-018

05517-019

05517-020

Rev. 0 | Page 10 of 20

ADG3301

www.BDTIC.com/ADI

TA = 25°C
DATA RATE = 25Mbps
C

= 50pF

L

1 CHANNEL

TA = 25°C
DATA RATE = 50Mbps

= 15pF

C

L

1 CHANNEL

400mV/DIV

5ns/DIV

Figure 21. Eye Diagram at Y Output

(1.2 V to 1.8 V Level Translation, 25 Mbps)

TA = 25°C
DATA RATE = 25Mbps

200mV/DIV

5ns/DIV

Figure 22. Eye Diagram at A Output

(1.8 V to 1.2 V Level Translation, 25 Mbps)

TA = 25°C
DATA RATE = 50Mbps

C

= 15pF

L

1 CHANNEL

= 50pF

C

L

1 CHANNEL

05517-021

05517-022

400mV/DIV

3ns/DIV

Figure 24. Eye Diagram at A Output

(3.3 V to 1.8 V Level Translation, 50 Mbps)

TA = 25°C
DATA RATE = 50Mbps
CL = 50pF
1 CHANNEL

1V/DIV

3ns/DIV

Figure 25. Eye Diagram at Y Output

(3.3 V to 5 V Level Translation, 50 Mbps)

TA = 25°C
DATA RATE = 50Mbps

= 15pF

C

L

1 CHANNEL

05517-024

05517-025

500mV/DIV

3ns/DIV

05517-023

Figure 23. Eye Diagram at Y Output

(1.8 V to 3.3 V Level Translation, 50 Mbps)

Rev. 0 | Page 11 of 20

800mV/DIV

3ns/DIV

Figure 26. Eye Diagram at A Output

(5 V to 3.3 V Level Translation, 50 Mbps)

05517-026

ADG3301

www.BDTIC.com/ADI

TEST CIRCUITS

0.1µF

EN

V

CCA

A

K1

ADG3301

GND

V

CCY

0.1µF

Y

EN

V

CCA

K2

0.1µF

A

ADG3301

V

CCY

0.1µF

Y

K

A

I

OH

K2

I

OL

0.1µF

EN

V

CCA

Figure 27. V

A

OH/VOL

ADG3301

GND

Figure 28. VOH/VOL Voltages at Pin Y

Voltages at Pin A

V

CCY

Y

I

OH

0.1µF

GND

05517-030

05517-027

Figure 30. Three-State Leakage Current at Pin Y

V

CCA

0.1µF

K1

I

OL

05517-028

A

K

A

EN

ADG3301

GND

V

CCY

0.1µF

Y

05517-031

Figure 31. EN Pin Leakage Current

0.1µF

EN

V

CCA

ADG3301

V

CCY

0.1µF

EN

V

CCA

ADG3301

V

CCY

A

K

A

GND

Y

05517-029

Figure 29. Three-State Leakage Current at Pin A

EN

V

CCA

A

ADG3301

GND

Figure 33. Capacitance at Pin Y

Rev. 0 | Page 12 of 20

V

CCY

Y

CAPACITANCE

METER

CAPACITANCE

A

Figure 32. Capacitance at Pin A

METER

05517-033

GND

Y

05517-032

ADG3301

www.BDTIC.com/ADI

A→Y DIRECTION

0.1µF

+

10µF

V

CCA

ADG3301

V

CCY

0.1µF

+

10µF

1MΩ

SIGNAL SOURCE

R

S

50Ω

0.1µF

SIGNAL SOURCE

R

S

50Ω

K1

Z0 = 50Ω

+

10µF

K1

1MΩ

Z

= 50Ω

0

1MΩ

V

V

V

V

EN

A

A

EN

EN

R

T

50Ω

Y→A DIRECTION

V

CCA

A

A

15pF

EN GND

R

T

50Ω

GND

ADG3301

V

Y

50pF

CCY

0.1µF

Y

V

Y

V

Y

+

K2

1MΩ

10µF

K2

V

CCA

0V
V

CCA/VCCY

0V
V

CCY/VCCA

0V

V

CCA

0V
V

CCA/VCCY

0V
V

CCY/VCCA

0V

05517-034

V

EN

VA/V

Y

90%
VY/V

A

V

EN

VA/V

Y

VY/V

A

10%

NOTE:

t

IS THE LARGEST OF

EN

t

EN1

t

EN2

t

AND

t

EN1

IN BOTH A→Y AND Y→A DIRECTIONS.

EN2

Figure 34. Enable Time

Rev. 0 | Page 13 of 20

ADG3301

www.BDTIC.com/ADI

V

CCY

0.1µF

YA

V

Y

50pF

+

10µF

0.1µF

15pF

EN

V

CCA

+

10µF

V

A

ADG3301

V

CCY

0.1µF

+

10µF

SIGNAL

SOURCE

R

V
R

50Ω

Y

Z0 = 50Ω

T

YA

50Ω

S

SIGNAL

SOURCE

R

50Ω

S

0.1µF

Z0 = 50Ω

V

50Ω

EN

V

CCA

+

10µF

A

R

T

ADG3301

GND

V

A

50%

t

P, A→Y

90%

50%

10%

t

V

Y

P, A→Y

t

F, A→Y

Figure 35. Switching Characteristics (A→Y Level Translation)

t

R, A→Y

V

Y

50%

V

A

90%
50%

10%

05517-035

Figure 36. Switching Characteristics (Y→A Level Translation)

GND

t

P, Y→A

t

F, Y→A

t

P, Y→A

t

R, Y→A

05517-036

Rev. 0 | Page 14 of 20

ADG3301

www.BDTIC.com/ADI

TERMINOLOGY

V

IHA

Logic input high voltage at Pin A.

V

ILA

Logic input low voltage at Pin A.

V

OHA

Logic output high voltage at Pin A.

V

OLA

Logic output low voltage at Pin A.

C

A

Capacitance measured at Pin A (EN = 0).

I

LA, HiZ

Leakage current at Pin A when EN = 0 (Pin A three-stated).

V

IHY

Logic input high voltage at Pin Y.

V

ILY

Logic input low voltage at Pin Y.

V

OHY

Logic output high voltage at Pin Y.

V

OLY

Logic output low voltage at Pin Y.

C

Y

Capacitance measured at Pin Y (EN = 0).

t

R, A→Y

Rise time when translating logic levels in the A→Y direction.

t

F, A →Y

Fall time when translating logic levels in the A→Y direction.

D

MAX, A→Y

Guaranteed data rate when translating logic levels in the A→Y
direction under the driving and loading conditions specified in
Tabl e 1 .

t

PPSKEW, A→Y

Difference in propagation delay between any one channel and
the same channel on a different part (under same
driving/loading conditions) when translating in the A→Y
direction.

t

P, Y→ A

Propagation delay when translating logic levels in the Y→A
direction.

t

R, Y→A

Rise time when translating logic levels in the Y→A direction.

t

F, Y →A

Fall time when translating logic levels in the Y→ A direction.

D

MAX, Y→A

Guaranteed data rate when translating logic levels in the Y→A
direction under the driving and loading conditions specified in
Tabl e 1 .

I

LY, HiZ

Leakage current at pin and when EN = 0 (Pin A three-stated).

V

IHEN

Logic input high voltage at the EN pin.

V

ILEN

Logic input low voltage at the EN pin.

C

EN

Capacitance measured at EN pin.

I

LEN

Enable (EN) pin leakage current.

t

EN

Three-state enable time for Pin A and Pin Y.

t

P, A→ Y

Propagation delay when translating logic levels in the A→Y
direction.

t

PPSKEW, Y→A

Difference in propagation delay between any one channel and
the same channel on a different part (under the same driving/
loading conditions) when translating in the Y→A direction.

I

CCA

V

CCA

I

CCY

V

CCY

I

HiZA

V

CCA

I

HiZY

V

CCY

Rev. 0 | Page 15 of 20

supply current.

supply current.

supply current during three-state mode (EN = 0).

supply current during three-state mode (EN = 0).

ADG3301

www.BDTIC.com/ADI

THEORY OF OPERATION

The ADG3301 level translator allows the level shifting
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, V
V

(V

≤ V

CCY

CCA

). These supplies set the logic levels on each

CCY

CCA

and

side of the device. When driving the A pin, the device translates
the V

-compatible logic levels to V

CCA

-compatible logic levels

CCY

available at the Y pin. Similarly, because the device is capable of
bidirectional translation, when driving the Y pin the V
patible logic levels are translated to V

-compatible logic levels

CCA

CCY

-com-

available at the A pin. When EN = 0, the A pin and the Y pin
are three-stated. When EN is driven high, the ADG3301 goes
into normal operation mode and performs level translation.

LEVEL TRANSLATOR ARCHITECTURE

The ADG3301 consists of a single bidirectional channel that can
translate logic levels in either the A→Y or the Y→A direction.
It uses a one-shot accelerator architecture that ensures excellent
switching characteristics. Figure 37 shows a simplified block
diagram of the ADG3301 level translator.

V

CCA

6kΩ

U2

U1

P

A

Figure 37. Simplified Block Diagram of an ADG3301 Channel

ONE-SHOT GENERATOR

U4

6kΩ

U3

The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y→A direction is performed using the
inverters U3 and U4. The one-shot generator detects a rising
or falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS transis­tors (T1 and T2) for a rising edge, or the NMOS transistors
(T3 and T4) for a falling edge. This charges/discharges the
capacitive load faster, which results in fast rise and fall times.

V

CCY

T2T1

N

Y

T3T4

05517-037

INPUT DRIVING REQUIREMENTS

To ensure correct operation of the ADG3301, the circuit that
drives the input of an ADG3301 channel must have an output
impedance of less than or equal to 150 Ω and a minimum peak
current driving capability of 36 mA.

OUTPUT LOAD REQUIREMENTS

The ADG3301 level translator is designed to drive CMOS­compatible loads. If current driving capability is required, it is
recommended to use buffers between the ADG3301 outputs
and the load.

ENABLE OPERATION

The ADG3301 provides three-state operation at the A I/O pin
and Y I/O pin by using the enable (EN) pin as shown in Table 4.

Table 4. Truth Table

EN Y I/O Pin A I/O Pin

0 Hi-Z
1 Normal operation

1

High impedance state.

2

In normal operation, the ADG3301 performs level translation.

1

2

1

Hi-Z
Normal operation

2

While EN = 0, the ADG3301 enters into tri-state mode. In this
mode, the current consumption from both the V

CCA

and V

CCY

supplies is reduced, allowing the user to save power, which is
critical especially on battery-operated systems. The EN input pin
can be driven with either V

CCA

- or V

-compatible logic levels.

CCY

POWER SUPPLIES

For proper operation of the ADG3301, the voltage applied to
the V
to V
sequence is V
properly only after both supply voltages reach their nominal
values. It is not recommended to use the part in a system where,
during power-up, V
significant increase in the current taken from the V
For optimum performance, the V
decoupled to GND, and placed as close as possible to the device.

must be always less than or equal to the voltage applied

CCA

. To meet this condition, the recommended power-up

CCY

first and then V

CCY

may be greater than V

CCA

. The ADG3301 operates

CCA

due to a

CCY

CCA

CCA

and V

pins should be

CCY

supply

Rev. 0 | Page 16 of 20

ADG3301

www.BDTIC.com/ADI

DATA RATE

The maximum data rate at which the device is guaranteed to
operate is a function of the V

CCA

and V
nation and the load capacitance. It represents the maximum
frequency of a square wave that can be applied to the I/O pins,
which ensures that the device operates within the datasheet
specifications in terms of output voltage (V

Table 5. Guaranteed Data Rate (Mbps)

V

CCA

1.2 V (1.15 V to 1.3 V) 25 30 40 40

1.8 V (1.65 V to 1.95 V) – 45 50 50

2.5 V (2.3 V to 2.7 V) – – 60 50

3.3 V (3.0 V to 3.6 V) – – – 50
5 V (4.5 V to 5.5 V) – – – –

1

The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.

supply voltage combi-

CCY

and VOH) and

OL

1

1.8 V

(1.65 V to 1.95 V)

power dissipation (the junction temperature does not exceed
the value specified under the Absolute Maximum Ratings
section).

Table 5 shows the guaranteed data rates at which the ADG3301

n operate in both directions (A→Y or Y→A level translation)

ca
for various V

2.5 V

(2.3 V to 2.7 V)

and V

CCA

V

CCY

supply combinations.

CCY

3.3 V

(3.0 V to 3.6 V)

(4.5 V to 5.5 V)

5 V

Rev. 0 | Page 17 of 20

ADG3301

www.BDTIC.com/ADI

APPLICATIONS

The ADG3301 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pin, and the higher voltage logic signals are connected to the
Y pin. The ADG3301 can provide level translation in both
directions from A→Y or Y→A, eliminating the need for a level
translator IC for each direction. The internal architecture allows
the ADG3301 to perform bidirectional level translation without
an additional signal to set the direction in which the translation
is made. This simplifies the design by eliminating the timing
requirements for the direction signal and reduces the number of
ICs used for level translation.

Figure 38 shows an application where a 1.8 V microprocessor
transfers data to or from a 3.3 V peripheral device using the
ADG3301 level translator.

100nF100nF

I/O

MICROPROCESSOR/
MICROCONTROLLER/
DSP

1

V

CCA

ADG3301

2

L

A

3

GND

6

V

CCY

EN

5

Y

4

3.3V1.8V

I/O

H

PERIPHERAL

DEVICE

LAYOUT GUIDELINES

As with any high speed digital IC, the printed circuit board
layout is important for the overall performance of the circuit.
Care should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each V
V

) should be bypassed using low effective series resistance

CCY

pin (V

CC

(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the V

CCA

and V

pins. The parasitic induc-

CCY

tance of the high-speed signal track might cause significant
overshoot. This effect can be reduced by keeping the length of
the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.

CCA

and

GND GND

Figure 38 1.8 V to 3.3 V Level Translation Circuit

05517-038

Rev. 0 | Page 18 of 20

ADG3301

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

2.20

2.00

1.80

2.40

1.35

1.25

1.15
PIN 1

1.30 BSC

1.00

0.90

0.70

0.10 MAX

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203-AB

Figure 39. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]

ORDERING GUIDE

Model Temperature Range Package Description Branding1Package Option

ADG3301BKSZ-REEL
ADG3301BKSZ-REEL72 −40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package S0H KS-6

1

Branding on this package is limited to three characters due to space constraints.

2

Z = Pb-free part.

2

−40°C to +85°C 6-Lead Thin Shrink Small Outline Transistor Package S0H KS-6

4 5 6

2.10

3 2 1

1.80

0.65 BSC

0.40

0.10

0.30

0.15

1.10

0.80

SEATING
PLANE

(KS-6)

Dimensions shown in millimeters

0.22

0.08

0.30

0.10

Rev. 0 | Page 19 of 20

ADG3301

www.BDTIC.com/ADI

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05517-0-12/05(0)

Rev. 0 | Page 20 of 20