FEATURES
100 ps Propagation Delay through the Switch
2 Switches Connect Inputs to Outputs
Data Rates up to 933 Mbps
Single 3.3 V/5 V Supply Operation
Level Translation Operation
Ultralow Quiescent Supply Current (1 nA Typical)
3.5 ns Switching
Standard ‘3257 Type Pinout
APPLICATIONS
Bus Switching
Bus Isolation
Level Translation
Memory Switching/Interleaving
GENERAL DESCRIPTION
The ADG3257 is a CMOS bus switch comprised of four 2:1
multiplexers/demultiplexers with high impedance outputs. The
device is manufactured on a CMOS process. This provides low
power dissipation yet high switching speed and very low ON
resistance, allowing the inputs to be connected to the outputs
without adding propagation delay or generating additional ground
bounce noise.
The ADG3257 operates from a single 3.3 V/5 V supply. The
control logic for each switch is shown in Table I. These switches
are bidirectional when ON. In the OFF condition, signal levels are
blocked up to the supplies.
This bus switch is suited to both switching and level translation
applications. It may be used in applications requiring level
translation from 3.3 V to 2.5 V when powered from 3.3 V.
Additionally, with a diode connected in series with 5 V V
the ADG3257 may also be used in applications requiring 5 V
to 3.3 V level translation.
DD
,
(4-Bit, 1 of 2) Bus Switch
ADG3257
FUNCTIONAL BLOCK DIAGRAM
1A
2A
3A
4A
LOGIC
BE
PRODUCT HIGHLIGHTS
1. 0.1 ns propagation delay through switch
2. 2 Ω switches connect inputs to outputs
3. Bidirectional operation
4. Ultralow power dissipation
5. 16-lead QSOP package
1B
1
1B
2
2B
1
2B
2
3B
1
3B
2
4B
1
4B
2
S
Table I. Truth Table
BESFunction
HXDISABLE
LLA = B
LHA = B
1
2
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Quiescent Power Supply CurrentI
Increase in ICC per Input
7
∆ I
CC
CC
Digital Inputs = 0 V or V
V
= 5.5 V, One Input at 3.0 V;
CC
CC
3.05.5V
0.0011µA
Others at VCC or GND200µA
NOTES
1
Temperature range is: B Version: –40°C to +85°C.
2
See Test Circuits and Waveforms.
3
All typical values are at TA = 25°C, unless otherwise noted.
4
Guaranteed by design, not subject to production test.
5
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6
Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7
This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. D
ADG3257
1
SPECIFICATIONS
ParameterSymbolConditions
(VCC = 3.3 V 10%, GND = 0 V. All specifications T
2
DC ELECTRICAL CHARACTERISTICS
Input High VoltageV
Input Low VoltageV
Input Leakage CurrentI
OFF State Leakage CurrentI
ON State Leakage CurrentI
Maximum Pass Voltage
CAPACITANCE
4
4
INH
INL
I
OZ
OZ
V
P
0 ⱕ VIN ⱕ 3.6 V± 0.01 ± 1µA
0 ⱕ A, B ⱕ V
0 ⱕ A, B ⱕ V
CC
CC
VIN = VCC = 3.3 V, IO = –5 µA2.32.62.8V
A Port OFF CapacitanceCA OFFf = 1 MHz7pF
B Port OFF CapacitanceC
OFFf = 1 MHz5pF
B
A, B Port ON CapacitanceCA, CB ON f = 1 MHz11pF
Control Input CapacitanceC
SWITCHING CHARACTERISTICS
Propagation Delay A to B or B to A, t
Propagation Delay Matching
4
6
PD
Bus Enable Time BE to A or Bt
Bus Disable Time BE to A or Bt
Quiescent Power Supply CurrentI
Increase in ICC per Input
7
∆ I
CC
CC
Digital Inputs = 0 V or V
V
= 3.3 V, One Input at 3.0 V;
CC
Others at VCC or GND200µA
NOTES
1
Temperature range is: B Version: –40°C to +85°C.
2
See Test Circuits and Waveforms.
3
All typical values are at TA = 25°C, unless otherwise noted.
4
Guaranteed by design, not subject to production test.
5
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6
Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7
This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
MIN
CC
to T
, unless otherwise noted.)
MAX
B Version
MinTyp3MaxUnit
2.0V
–0.3+0.8V
± 0.01 ± 1µA
± 0.01 ± 1µA
5Ω
8Ω
3.05.5V
0.001 1µA
REV. D
–3–
ADG3257
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
S
1B
1
1B
2
1A
2B
1
2B
2
2A
GND
V
CC
BE
4B
1
4B
2
4A
3B
1
3B
2
3A
ADG3257
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . 235°C
Stresses above those listed under Absolute Maximum Ratings may cause perma-
*
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
PIN FUNCTION DESCRIPTIONS
MnemonicDescription
BEOutput Enable (Active Low)
SPort Select
AxPort A, Inputs or Outputs
BxPort B, Inputs or Outputs
ADG3257BRQ–40°C to +85°C16-Lead Shrink Small Outline PackageRQ-16
ADG3257BRQ-REEL–40°C to +85°C16-Lead Shrink Small Outline PackageRQ-16
ADG3257BRQ-REEL7–40°C to +85°C16-Lead Shrink Small Outline PackageRQ-16
ADG3257BRQZ*–40°C to +85°C16-Lead Shrink Small Outline PackageRQ-16
ADG3257BRQZ-REEL7*–40°C to +85°C16-Lead Shrink Small Outline PackageRQ-16
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG3257 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. D
Typical Performance Characteristics–ADG3257
20
TA = 25 C
16
12
–
ON
R
8
4
0
01
VCC = 5.0V
VCC = 4.5V
VCC = 5.5V
2345
VA/VB – V
TPC 1. ON Resistance vs. Input
Voltage
20
VCC = 3V
15
–
10
ON
R
5
0
00.5
+85 C
+25 C
–40
C
1.01.52.02.53.0
VA/VB – V
20
TA = 25 C
16
V
CC
00.5
VCC = 3.0V
= 2.7V
VCC = 3.3V
1.01.52.02.53.0
VA/VB – V
12
–
ON
R
8
4
0
TPC 2. ON Resistance vs. Input
Voltage
10m
1m
100
10
CURRENT – A
1
100n
10n
0.1
VCC = 3V
1101001k10k
FREQUENCY – kHz
TA = 25C
VCC = 5V
20
VCC = 5V
15
–
10
ON
R
+85 C
5
0
01
+25 C
–40 C
2345
VA/VB – V
TPC 3. ON Resistance vs. Input
Voltage for Different Temperatures
5
TA = 25C
4
3
2
OUTPUT VOLTAGE – V
1
0
12345
0
VCC = 5.5V
VCC = 5.0V
VCC = 4.5V
INPUT VOLTAGE – V
TPC 4. ON Resistance vs. Input
Voltage for Different Temperatures
3.6
TA = 25C
3
2
1
OUTPUT VOLTAGE – V
0
0.5 1.0 1.52.53.5
0
INPUT VOLTAGE – V
VCC = 3.6V
VCC = 3.3V
VCC = 3.0V
3.02.0
TPC 7. Maximum Pass Voltage
TPC 5. ICC vs. Enable Frequency
40mV/DIV
267ps/DIV
= 5V
V
CC
V
= 2V p-p
IN
622MBPS
20dB ATTENUATION
T
= 25C
A
TPC 8. 622 Mbps Eye Diagram
TPC 6. Maximum Pass Voltage
40mV/DIV
180ps/DIV
V
= 5V
CC
= 2V p-p
V
IN
933MBPS
20dB ATTENUATION
= 25C
T
A
TPC 9. 933 Mbps Eye Diagram
REV. D
–5–
ADG3257
V
CC
V
IN
1
PULSE
GENERATOR
NOTES
1
PULSE GENERATOR FOR ALL PULSES:
2
CL = INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
3
RT IS THE TERMINATION RESISTOR; SHOULD BE EQUAL TO Z
OF THE PULSE GENERATOR.
3
R
T
DUT
V
OUT
t
< 2.5ns,
F
Figure 1. Load Circuit
SWITCH INPUT
t
PHL
OUTPUT
t
PLH
Figure 2. Propagation Delay
ENABLEDISABLE
CONTROL INPUTS
t
PZL
V
OUTPUT
S1 @ 2 V
OUTPUT
S1 @ 2 V
LOW
CC
CC
CC
V
T
t
t
PZH
V
0V
PHZ
T
2 V
S1
R
L
CC
OPEN
GND
APPLICATIONS
Mixed Voltage Operation, Level Translation
Bus switches can be used to provide a solution for mixed voltage
systems where interfacing bidirectionally between 5 V and 3 V
devices is required. To interface between 5 V and 3.3 V buses,
an external diode is placed in series with the 5 V power supply
2
C
R
L
L
t
< 2.5ns.
R
OUT
V
IH
V
T
0V
V
OH
V
T
V
OL
as shown in Figure 4.
3.3V CPU/DSP/
MICROPROCESSOR/
MEMORY
BE
V
= 5V
CC
3.3V TO 5V
3.3V TO 3.3V
5V MEMORY
5V I/O
Figure 4. Level Translation between 5 V and 3.3 V Devices
The diode drops the internal gate voltage down to 4.3 V.
V
IH
V
T
t
PLZ
0V
V
CC
V
+ V
OL
V
OL
V
OH
V
– V
OH
0V
The bus switch limits the voltage present on the output to
V
– External Diode Drop = V
CC
TH
Therefore, assuming a diode drop of 0.7 V and a VTH of 1 V,
the output voltage would be limited to 3.3 V with a logic high.
V
OUT
3.3V
5V SUPPLY
Figure 3. Select, Enable, and Disable Times
SymbolV
R
L
V
∆
C
L
Table II. Switch S1 Condition
TestS1
t
PLH
t
PLZ
t
PHZ
t
SEL
, t
, t
, t
PHL
PZL
PZH
OPEN
2 × V
GND
OPEN
CC
Table III. Test Conditions
= 5 V
CC
10%
VCC = 3.3 V
10%
Unit
500500Ω
300300mV
5050pF
SWITCH OUTPUT
0V5VSWITCH INPUT
V
IN
Figure 5. Input Voltage to Output Voltage
Similarly, the device could be used to translate bidirectionally
between 3.3 V to 2.5 V systems. In this case, there is no need
for an external diode. The internal V
= 3.3 V the bus switch will limit the output voltage to
V
CC
V
– 1 V = 2.3 V
CC
drop is 1 V, so with a
TH
–6–
REV. D
ADG3257
BE
S
LOGIC
SDRAM NO. 1
SDRAM NO. 2
SDRAM NO. 7
SDRAM NO. 8
3.3V
3.3V
2.5V
2.5V
V
OUT
3.3V SUPPLY
ADG3257
2.5V
2.5V
SWITCH OUTPUT
0V
SWITCH INPUT
3.3V
V
IN
Figure 6. 3.3 V to 2.5 V Level Translation Using the
ADG3257 Bus Switch
Memory Switching
This quad bus switch may be used to allow switching between
different memory banks, thus allowing additional memory and
decreasing capacitive loading. Figure 7 illustrates the ADG3257
in such an application.
Figure 7. Allows Additional Memory Modules without
Added Drive or Delay