High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux
a
FEATURES
100 ps Propagation Delay through the Switch
2 Switches Connect Inputs to Outputs
Data Rates up to 933 Mbps
Single 3.3 V/5 V Supply Operation
Level Translation Operation
Ultralow Quiescent Supply Current (1 nA Typical)
3.5 ns Switching
Standard ‘3257 Type Pinout
APPLICATIONS
Bus Switching
Bus Isolation
Level Translation
Memory Switching/Interleaving
GENERAL DESCRIPTION
The ADG3257 is a CMOS bus switch comprised of four 2:1
multiplexers/demultiplexers with high impedance outputs. The
device is manufactured on a CMOS process. This provides low
power dissipation yet high switching speed and very low ON
resistance, allowing the inputs to be connected to the outputs
without adding propagation delay or generating additional ground
bounce noise.
The ADG3257 operates from a single 3.3 V/5 V supply. The
control logic for each switch is shown in Table I. These switches
are bidirectional when ON. In the OFF condition, signal levels are
blocked up to the supplies.
This bus switch is suited to both switching and level translation
applications. It may be used in applications requiring level
translation from 3.3 V to 2.5 V when powered from 3.3 V.
Additionally, with a diode connected in series with 5 V V
the ADG3257 may also be used in applications requiring 5 V
to 3.3 V level translation.
DD
,
(4-Bit, 1 of 2) Bus Switch
ADG3257
FUNCTIONAL BLOCK DIAGRAM
1A
2A
3A
4A
LOGIC
BE
PRODUCT HIGHLIGHTS
1. 0.1 ns propagation delay through switch
2. 2 Ω switches connect inputs to outputs
3. Bidirectional operation
4. Ultralow power dissipation
5. 16-lead QSOP package
1B
1
1B
2
2B
1
2B
2
3B
1
3B
2
4B
1
4B
2
S
Table I. Truth Table
BE S Function
HXDISABLE
LLA = B
LHA = B
1
2
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
ADG3257–SPECIFICATIONS
Parameter Symbol Conditions
1
(VCC = 5.0 V 10%, GND = 0 V. All specifications T
2
to T
MIN
, unless otherwise noted.)
MAX
B Version
Min Typ3Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
OFF State Leakage Current I
ON State Leakage Current I
Maximum Pass Voltage
CAPACITANCE
4
4
INH
INL
I
OZ
OZ
V
P
0 ⱕ VIN ⱕ 5.5 V ± 0.01 ± 1 µA
0 ⱕ A, B ⱕ V
0 ⱕ A, B ⱕ V
CC
CC
VIN = VCC = 5 V, IO = –5 µA 3.9 4.2 4.4 V
2.4 V
–0.3 +0.8 V
± 0.01 ± 1 µA
± 0.01 ± 1 µA
A Port OFF Capacitance CA OFF f = 1 MHz 7 pF
B Port OFF Capacitance CB OFF f = 1 MHz 5 pF
A, B Port ON Capacitance C
Control Input Capacitance C
SWITCHING CHARACTERISTICS
Propagation Delay A to B or B to A, t
Propagation Delay Matching
4
6
PD
Bus Enable Time BE to A or B t
Bus Disable Time BE to A or B t
, CB ON f = 1 MHz 11 pF
A
IN
t
PHL, tPLH
f = 1 MHz 4 pF
5
VA = 0 V, CL = 50 pF 0.10 ns
VA = 0 V, CL = 50 pF 0.0075 0.035 ns
PZH
PHZ
, t
, t
CL = 50 pF, RL = 500 Ω 157.5 ns
PZL
CL = 50 pF, RL = 500 Ω 1 3.5 7 ns
PLZ
Bus Select Time S to A or B
Enable t
Disable t
SEL_EN
SEL_DIS
CL = 50 pF, RL = 500 Ω 812ns
CL = 50 pF, RL = 500 Ω 58ns
Maximum Data Rate VA = 2 V p-p 933 Mbps
DIGITAL SWITCH
ON Resistance R
ON
VA = 0 V
IO = 48 mA, 15 mA, 8 mA, TA = 25°C24Ω
IO = 48 mA, 15 mA, 8 mA 5 Ω
= 2.4 V
V
A
IO = 48 mA, 15 mA, 8 mA, TA = 25°C36Ω
IO = 48 mA, 15 mA, 8 mA 7 Ω
ON Resistance Matching ∆R
ON
VA = 0 V, IO = 48 mA, 15 mA, 8 mA 0.15 Ω
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current I
Increase in ICC per Input
7
∆ I
CC
CC
Digital Inputs = 0 V or V
V
= 5.5 V, One Input at 3.0 V;
CC
CC
3.0 5.5 V
0.001 1 µA
Others at VCC or GND 200 µA
NOTES
1
Temperature range is: B Version: –40°C to +85°C.
2
See Test Circuits and Waveforms.
3
All typical values are at TA = 25°C, unless otherwise noted.
4
Guaranteed by design, not subject to production test.
5
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6
Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7
This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. D
ADG3257
1
SPECIFICATIONS
Parameter Symbol Conditions
(VCC = 3.3 V 10%, GND = 0 V. All specifications T
2
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
OFF State Leakage Current I
ON State Leakage Current I
Maximum Pass Voltage
CAPACITANCE
4
4
INH
INL
I
OZ
OZ
V
P
0 ⱕ VIN ⱕ 3.6 V ± 0.01 ± 1 µA
0 ⱕ A, B ⱕ V
0 ⱕ A, B ⱕ V
CC
CC
VIN = VCC = 3.3 V, IO = –5 µA 2.3 2.6 2.8 V
A Port OFF Capacitance CA OFF f = 1 MHz 7 pF
B Port OFF Capacitance C
OFF f = 1 MHz 5 pF
B
A, B Port ON Capacitance CA, CB ON f = 1 MHz 11 pF
Control Input Capacitance C
SWITCHING CHARACTERISTICS
Propagation Delay A to B or B to A, t
Propagation Delay Matching
4
6
PD
Bus Enable Time BE to A or B t
Bus Disable Time BE to A or B t
IN
t
PHL, tPLH
, t
PZH
, t
PHZ
f = 1 MHz 4 pF
5
VA = 0 V, CL = 50 pF 0.10 ns
VA = 0 V, CL = 50 pF 0.01 0.04 ns
CL = 50 pF, RL = 500 Ω 1 5.5 9 ns
PZL
CL = 50 pF, RL = 500 Ω 1 4.5 8.5 ns
PLZ
Bus Select Time S to A or B
Enable t
Disable t
SEL_EN
SEL_DIS
CL = 50 pF, RL = 500 Ω 812ns
CL = 50 pF, RL = 500 Ω 69 ns
Maximum Data Rate VA = 2 V p-p 933 Mbps
DIGITAL SWITCH
ON Resistance R
ON
VA = 0 V
= 15 mA, 8 mA, TA = 25°C24Ω
I
O
VA = 1 V, IO = 15 mA, 8 mA, TA = 25°C47Ω
ON Resistance Matching ∆R
ON
VA = 0 V, IO = 15 mA, 8 mA 0.2 Ω
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current I
Increase in ICC per Input
7
∆ I
CC
CC
Digital Inputs = 0 V or V
V
= 3.3 V, One Input at 3.0 V;
CC
Others at VCC or GND 200 µA
NOTES
1
Temperature range is: B Version: –40°C to +85°C.
2
See Test Circuits and Waveforms.
3
All typical values are at TA = 25°C, unless otherwise noted.
4
Guaranteed by design, not subject to production test.
5
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6
Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7
This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
MIN
CC
to T
, unless otherwise noted.)
MAX
B Version
Min Typ3Max Unit
2.0 V
–0.3 +0.8 V
± 0.01 ± 1 µA
± 0.01 ± 1 µA
5 Ω
8 Ω
3.0 5.5 V
0.001 1 µA
REV. D
–3–
ADG3257
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
S
1B
1
1B
2
1A
2B
1
2B
2
2A
GND
V
CC
BE
4B
1
4B
2
4A
3B
1
3B
2
3A
ADG3257
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs
to GND . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
QSOP Package
Thermal Impedance . . . . . . . . . . . . . . . . . . 149.97°C/W
θ
JA
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . 235°C
Stresses above those listed under Absolute Maximum Ratings may cause perma-
*
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
PIN FUNCTION DESCRIPTIONS
Mnemonic Description
BE Output Enable (Active Low)
S Port Select
Ax Port A, Inputs or Outputs
Bx Port B, Inputs or Outputs
ORDERING GUIDE
Model Temperature Range Package Descriptions Package Option
ADG3257BRQ –40°C to +85°C 16-Lead Shrink Small Outline Package RQ-16
ADG3257BRQ-REEL –40°C to +85°C 16-Lead Shrink Small Outline Package RQ-16
ADG3257BRQ-REEL7 –40°C to +85°C 16-Lead Shrink Small Outline Package RQ-16
ADG3257BRQZ* –40°C to +85°C 16-Lead Shrink Small Outline Package RQ-16
ADG3257BRQZ-REEL7* –40°C to +85°C 16-Lead Shrink Small Outline Package RQ-16
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG3257 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. D
Typical Performance Characteristics–ADG3257
20
TA = 25 C
16
12
–
ON
R
8
4
0
01
VCC = 5.0V
VCC = 4.5V
VCC = 5.5V
2345
VA/VB – V
TPC 1. ON Resistance vs. Input
Voltage
20
VCC = 3V
15
–
10
ON
R
5
0
0 0.5
+85 C
+25 C
–40
C
1.0 1.5 2.0 2.5 3.0
VA/VB – V
20
TA = 25 C
16
V
CC
0 0.5
VCC = 3.0V
= 2.7V
VCC = 3.3V
1.0 1.5 2.0 2.5 3.0
VA/VB – V
12
–
ON
R
8
4
0
TPC 2. ON Resistance vs. Input
Voltage
10m
1m
100
10
CURRENT – A
1
100n
10n
0.1
VCC = 3V
110100 1k 10k
FREQUENCY – kHz
TA = 25C
VCC = 5V
20
VCC = 5V
15
–
10
ON
R
+85 C
5
0
01
+25 C
–40 C
2345
VA/VB – V
TPC 3. ON Resistance vs. Input
Voltage for Different Temperatures
5
TA = 25C
4
3
2
OUTPUT VOLTAGE – V
1
0
1 2345
0
VCC = 5.5V
VCC = 5.0V
VCC = 4.5V
INPUT VOLTAGE – V
TPC 4. ON Resistance vs. Input
Voltage for Different Temperatures
3.6
TA = 25C
3
2
1
OUTPUT VOLTAGE – V
0
0.5 1.0 1.5 2.5 3.5
0
INPUT VOLTAGE – V
VCC = 3.6V
VCC = 3.3V
VCC = 3.0V
3.02.0
TPC 7. Maximum Pass Voltage
TPC 5. ICC vs. Enable Frequency
40mV/DIV
267ps/DIV
= 5V
V
CC
V
= 2V p-p
IN
622MBPS
20dB ATTENUATION
T
= 25C
A
TPC 8. 622 Mbps Eye Diagram
TPC 6. Maximum Pass Voltage
40mV/DIV
180ps/DIV
V
= 5V
CC
= 2V p-p
V
IN
933MBPS
20dB ATTENUATION
= 25C
T
A
TPC 9. 933 Mbps Eye Diagram
REV. D
–5–
ADG3257
V
CC
V
IN
1
PULSE
GENERATOR
NOTES
1
PULSE GENERATOR FOR ALL PULSES:
2
CL = INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
3
RT IS THE TERMINATION RESISTOR; SHOULD BE EQUAL TO Z
OF THE PULSE GENERATOR.
3
R
T
DUT
V
OUT
t
< 2.5ns,
F
Figure 1. Load Circuit
SWITCH INPUT
t
PHL
OUTPUT
t
PLH
Figure 2. Propagation Delay
ENABLE DISABLE
CONTROL INPUTS
t
PZL
V
OUTPUT
S1 @ 2 V
OUTPUT
S1 @ 2 V
LOW
CC
CC
CC
V
T
t
t
PZH
V
0V
PHZ
T
2 V
S1
R
L
CC
OPEN
GND
APPLICATIONS
Mixed Voltage Operation, Level Translation
Bus switches can be used to provide a solution for mixed voltage
systems where interfacing bidirectionally between 5 V and 3 V
devices is required. To interface between 5 V and 3.3 V buses,
an external diode is placed in series with the 5 V power supply
2
C
R
L
L
t
< 2.5ns.
R
OUT
V
IH
V
T
0V
V
OH
V
T
V
OL
as shown in Figure 4.
3.3V CPU/DSP/
MICROPROCESSOR/
MEMORY
BE
V
= 5V
CC
3.3V TO 5V
3.3V TO 3.3V
5V MEMORY
5V I/O
Figure 4. Level Translation between 5 V and 3.3 V Devices
The diode drops the internal gate voltage down to 4.3 V.
V
IH
V
T
t
PLZ
0V
V
CC
V
+ V
OL
V
OL
V
OH
V
– V
OH
0V
The bus switch limits the voltage present on the output to
V
– External Diode Drop = V
CC
TH
Therefore, assuming a diode drop of 0.7 V and a VTH of 1 V,
the output voltage would be limited to 3.3 V with a logic high.
V
OUT
3.3V
5V SUPPLY
Figure 3. Select, Enable, and Disable Times
Symbol V
R
L
V
∆
C
L
Table II. Switch S1 Condition
Test S1
t
PLH
t
PLZ
t
PHZ
t
SEL
, t
, t
, t
PHL
PZL
PZH
OPEN
2 × V
GND
OPEN
CC
Table III. Test Conditions
= 5 V
CC
10%
VCC = 3.3 V
10%
Unit
500 500 Ω
300 300 mV
50 50 pF
SWITCH OUTPUT
0V 5VSWITCH INPUT
V
IN
Figure 5. Input Voltage to Output Voltage
Similarly, the device could be used to translate bidirectionally
between 3.3 V to 2.5 V systems. In this case, there is no need
for an external diode. The internal V
= 3.3 V the bus switch will limit the output voltage to
V
CC
V
– 1 V = 2.3 V
CC
drop is 1 V, so with a
TH
–6–
REV. D
ADG3257
BE
S
LOGIC
SDRAM NO. 1
SDRAM NO. 2
SDRAM NO. 7
SDRAM NO. 8
3.3V
3.3V
2.5V
2.5V
V
OUT
3.3V SUPPLY
ADG3257
2.5V
2.5V
SWITCH OUTPUT
0V
SWITCH INPUT
3.3V
V
IN
Figure 6. 3.3 V to 2.5 V Level Translation Using the
ADG3257 Bus Switch
Memory Switching
This quad bus switch may be used to allow switching between
different memory banks, thus allowing additional memory and
decreasing capacitive loading. Figure 7 illustrates the ADG3257
in such an application.
Figure 7. Allows Additional Memory Modules without
Added Drive or Delay
REV. D
–7–
ADG3257
OUTLINE DIMENSIONS
16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
0.193
BSC
0.012
0.008
9
8
0.154
BSC
0.069
0.053
SEATING
PLANE
0.236
BSC
0.010
0.006
8
0
0.050
0.016
0.065
0.049
0.010
0.004
COPLANARITY
0.004
16
1
PIN 1
0.025
BSC
COMPLIANT TO JEDEC STANDARDS MO-137AB
Revision History
Location Page
11/04—REV. C to REV. D.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4/03—REV. A to REV. B.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
C02914–0–11/04(D)
06/02—REV. 0 to REV. A.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
–8–
REV. D
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