Analog Devices ADG3257 d Datasheet
High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux
a
FEATURES
100 ps Propagation Delay through the Switch
2 Switches Connect Inputs to Outputs
Data Rates up to 933 Mbps
Single 3.3 V/5 V Supply Operation
Level Translation Operation
Ultralow Quiescent Supply Current (1 nA Typical)
3.5 ns Switching
Standard ‘3257 Type Pinout
APPLICATIONS
Bus Switching
Bus Isolation
Level Translation
Memory Switching/Interleaving
GENERAL DESCRIPTION
The ADG3257 is a CMOS bus switch comprised of four 2:1
multiplexers/demultiplexers with high impedance outputs. The
device is manufactured on a CMOS process. This provides low
power dissipation yet high switching speed and very low ON
resistance, allowing the inputs to be connected to the outputs
without adding propagation delay or generating additional ground
bounce noise.
The ADG3257 operates from a single 3.3 V/5 V supply. The
control logic for each switch is shown in Table I. These switches
are bidirectional when ON. In the OFF condition, signal levels are
blocked up to the supplies.
This bus switch is suited to both switching and level translation
applications. It may be used in applications requiring level
translation from 3.3 V to 2.5 V when powered from 3.3 V.
Additionally, with a diode connected in series with 5 V V
the ADG3257 may also be used in applications requiring 5 V
to 3.3 V level translation.
DD
,
(4-Bit, 1 of 2) Bus Switch
ADG3257
FUNCTIONAL BLOCK DIAGRAM
1A
2A
3A
4A
LOGIC
BE
PRODUCT HIGHLIGHTS
1. 0.1 ns propagation delay through switch
2. 2 Ω switches connect inputs to outputs
3. Bidirectional operation
4. Ultralow power dissipation
5. 16-lead QSOP package
1B
1
1B
2
2B
1
2B
2
3B
1
3B
2
4B
1
4B
2
S
Table I. Truth Table
BE S Function
HXDISABLE
LLA = B
LHA = B
1
2
REV. D
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ADG3257–SPECIFICATIONS
Parameter Symbol Conditions
1
(VCC = 5.0 V 10%, GND = 0 V. All specifications T
2
to T
MIN
, unless otherwise noted.)
MAX
B Version
Min Typ3Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
OFF State Leakage Current I
ON State Leakage Current I
Maximum Pass Voltage
CAPACITANCE
4
4
INH
INL
I
OZ
OZ
V
P
0 ⱕ VIN ⱕ 5.5 V ± 0.01 ± 1 µA
0 ⱕ A, B ⱕ V
0 ⱕ A, B ⱕ V
CC
CC
VIN = VCC = 5 V, IO = –5 µA 3.9 4.2 4.4 V
2.4 V
–0.3 +0.8 V
± 0.01 ± 1 µA
± 0.01 ± 1 µA
A Port OFF Capacitance CA OFF f = 1 MHz 7 pF
B Port OFF Capacitance CB OFF f = 1 MHz 5 pF
A, B Port ON Capacitance C
Control Input Capacitance C
SWITCHING CHARACTERISTICS
Propagation Delay A to B or B to A, t
Propagation Delay Matching
4
6
PD
Bus Enable Time BE to A or B t
Bus Disable Time BE to A or B t
, CB ON f = 1 MHz 11 pF
A
IN
t
PHL, tPLH
f = 1 MHz 4 pF
5
VA = 0 V, CL = 50 pF 0.10 ns
VA = 0 V, CL = 50 pF 0.0075 0.035 ns
PZH
PHZ
, t
, t
CL = 50 pF, RL = 500 Ω 157.5 ns
PZL
CL = 50 pF, RL = 500 Ω 1 3.5 7 ns
PLZ
Bus Select Time S to A or B
Enable t
Disable t
SEL_EN
SEL_DIS
CL = 50 pF, RL = 500 Ω 812ns
CL = 50 pF, RL = 500 Ω 58ns
Maximum Data Rate VA = 2 V p-p 933 Mbps
DIGITAL SWITCH
ON Resistance R
ON
VA = 0 V
IO = 48 mA, 15 mA, 8 mA, TA = 25°C24Ω
IO = 48 mA, 15 mA, 8 mA 5 Ω
= 2.4 V
V
A
IO = 48 mA, 15 mA, 8 mA, TA = 25°C36Ω
IO = 48 mA, 15 mA, 8 mA 7 Ω
ON Resistance Matching ∆R
ON
VA = 0 V, IO = 48 mA, 15 mA, 8 mA 0.15 Ω
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current I
Increase in ICC per Input
7
∆ I
CC
CC
Digital Inputs = 0 V or V
V
= 5.5 V, One Input at 3.0 V;
CC
CC
3.0 5.5 V
0.001 1 µA
Others at VCC or GND 200 µA
NOTES
1
Temperature range is: B Version: –40°C to +85°C.
2
See Test Circuits and Waveforms.
3
All typical values are at TA = 25°C, unless otherwise noted.
4
Guaranteed by design, not subject to production test.
5
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6
Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7
This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. D
ADG3257
1
SPECIFICATIONS
Parameter Symbol Conditions
(VCC = 3.3 V 10%, GND = 0 V. All specifications T
2
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
OFF State Leakage Current I
ON State Leakage Current I
Maximum Pass Voltage
CAPACITANCE
4
4
INH
INL
I
OZ
OZ
V
P
0 ⱕ VIN ⱕ 3.6 V ± 0.01 ± 1 µA
0 ⱕ A, B ⱕ V
0 ⱕ A, B ⱕ V
CC
CC
VIN = VCC = 3.3 V, IO = –5 µA 2.3 2.6 2.8 V
A Port OFF Capacitance CA OFF f = 1 MHz 7 pF
B Port OFF Capacitance C
OFF f = 1 MHz 5 pF
B
A, B Port ON Capacitance CA, CB ON f = 1 MHz 11 pF
Control Input Capacitance C
SWITCHING CHARACTERISTICS
Propagation Delay A to B or B to A, t
Propagation Delay Matching
4
6
PD
Bus Enable Time BE to A or B t
Bus Disable Time BE to A or B t
IN
t
PHL, tPLH
, t
PZH
, t
PHZ
f = 1 MHz 4 pF
5
VA = 0 V, CL = 50 pF 0.10 ns
VA = 0 V, CL = 50 pF 0.01 0.04 ns
CL = 50 pF, RL = 500 Ω 1 5.5 9 ns
PZL
CL = 50 pF, RL = 500 Ω 1 4.5 8.5 ns
PLZ
Bus Select Time S to A or B
Enable t
Disable t
SEL_EN
SEL_DIS
CL = 50 pF, RL = 500 Ω 812ns
CL = 50 pF, RL = 500 Ω 69 ns
Maximum Data Rate VA = 2 V p-p 933 Mbps
DIGITAL SWITCH
ON Resistance R
ON
VA = 0 V
= 15 mA, 8 mA, TA = 25°C24Ω
I
O
VA = 1 V, IO = 15 mA, 8 mA, TA = 25°C47Ω
ON Resistance Matching ∆R
ON
VA = 0 V, IO = 15 mA, 8 mA 0.2 Ω
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current I
Increase in ICC per Input
7
∆ I
CC
CC
Digital Inputs = 0 V or V
V
= 3.3 V, One Input at 3.0 V;
CC
Others at VCC or GND 200 µA
NOTES
1
Temperature range is: B Version: –40°C to +85°C.
2
See Test Circuits and Waveforms.
3
All typical values are at TA = 25°C, unless otherwise noted.
4
Guaranteed by design, not subject to production test.
5
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6
Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7
This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
MIN
CC
to T
, unless otherwise noted.)
MAX
B Version
Min Typ3Max Unit
2.0 V
–0.3 +0.8 V
± 0.01 ± 1 µA
± 0.01 ± 1 µA
5 Ω
8 Ω
3.0 5.5 V
0.001 1 µA
REV. D
–3–
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