Analog Devices ADG3249 Datasheet

2.5 V/3.3 V, 2:1 Multiplexer/
Demultiplexer Bus Switch

ADG3249

FEATURES
225 ps Propagation Delay through the Switch

4.5  Switch Connection between Ports
Data Rate 1.244 Gbps

2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation

3.3 V to 2.5 V

3.3 V to 1.8 V

2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
8-Lead SOT-23 Package

APPLICATIONS

3.3 V to 1.8 V Voltage Translation

3.3 V to 2.5 V Voltage Translation

2.5 V to 1.8 V Voltage Translation
Docking Stations
Memory Switching
Analog Switch Applications

GENERAL DESCRIPTION

The ADG3249 is a 2.5 V or 3.3 V, high performance 2:1 multi­plexer/demultiplexer bus switch. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. This allows the
input to be connected to the output without additional propaga­tion delay or generating additional ground bounce noise.

Each switch of the ADG3249 conducts equally well in both direc­tions when on. The ADG3249 exhibits break-before-make
switching action, preventing momentary shorting when switch­ing channels.

This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from

3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device
is operated from 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition, a level
translating pin (SEL) is included. When SEL is low, V

CC

is
reduced internally, allowing for level translating between 3.3 V
inputs and 1.8 V outputs.

The ADG3249 is available in a tiny 8-lead SOT-23 package.

FUNCTIONAL BLOCK DIAGRAM

ADG3249

A0

A1

PRODUCT HIGHLIGHTS

CONTROL

LOGIC

IN

B

EN

1. 3.3 V or 2.5 V supply operation.

2. Extremely low propagation delay through switch.

3. 4.5 Ω switches connect inputs to outputs.

4. Tiny SOT-23 package.

REV. 0

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ADG3249–SPECIFICATIONS

(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T

1

unless otherwise noted.)

MIN

to T

MAX

,

B Version

Parameter Symbol Conditions Min Typ2Max Unit

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V

Input Low Voltage V

Input Leakage Current I
OFF State Leakage Current I

INH

V

INH

INL

V

INL

I

OZ

ON State Leakage Current 0 ≤ A, B ≤ V
Maximum Pass Voltage V

P

VCC = 2.7 V to 3.6 V 2.0 V
VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 0.8 V
VCC = 2.3 V to 2.7 V 0.7 V

± 0.01 ± 1 µA

0 ≤ A, B ≤ V

CC

CC

± 0.01 ± 1 µA
± 0.01 ±1 µA

VA/VB = VCC = SEL = 3.3 V, IO = –5 µA 2.0 2.5 2.9 V

= VCC = SEL = 2.5 V, IO= –5 µA1.51.82.1V

V

A/VB

VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA 1.5 1.8 2.1 V

CAPACITANCE

A Port Off Capacitance CA OFF f = 1 MHz; EN = V
B Port Off Capacitance C
A, B Port On Capacitance C
Control Input Capacitance C

SWITCHING CHARACTERISTICS

Propagation Delay A to B or B to A, t
Propagation Delay Matching
Bus Enable Time EN to A or B
Bus Disable Time EN to A or B
Bus Enable Time EN to A or B
Bus Disable Time EN to A or B
Bus Enable Time EN to A or B
Bus Disable Time EN to A or B
Break-before-Make Time t
Transition Time t

Maximum Data Rate V
Channel Jitter V

3

OFF f = 1 MHz; EN = V

B

, CB ON f = 1 MHz 8.5 pF

A

IN, CSEL

C

EN

3

4

t

PHL

t

PZH

t

PHZ

t

PZH

t

PHZ

t

PZH

t

PHZ

BBM

TRANS

, t

, t
, t
, t
, t
, t
, t

5

PD

6

6

6

6

6

6

f = 1 MHz 4 pF
f = 1 MHz 6.5 pF

CL = 50 pF, VCC = SEL = 3 V 0.225 ns

PLH

VCC = 3.0 V to 3.6 V; SEL = V

PZL

VCC = 3.0 V to 3.6 V; SEL = V

PLZ

VCC = 3.0 V to 3.6 V; SEL = 0 V 1 3.2 4.5 ns

PZL

VCC = 3.0 V to 3.6 V; SEL = 0 V 1 4.5 7.7 ns

PLZ

VCC = 2.3 V to 2.7 V; SEL = V

PZL

VCC = 2.3 V to 2.7 V; SEL = V

PLZ

RL = 510 Ω, CL = 50 pF 5 10 ns
RL = 510 Ω, CL = 50 pF; SEL = V
R

= 510 Ω, CL = 50 pF; SEL = 0 V 15 22 ns

L

= SEL = 3.3 V; VA/VB = 2 V 1.244 Gbps

CC

= SEL = 3.3 V; VA/VB = 2 V 45 ps p-p

CC

CC

CC

CC

CC

CC

CC

1 3.5 4.8 ns
1 5.5 8.2 ns

1 3.5 4.6 ns
14 5.8 ns

CC

3.5 pF

4.5 pF

5ps

16 29 ns

DIGITAL SWITCH

On Resistance R

On Resistance Matching ⌬R

ON

ON

VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 4.5 8 Ω

= 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA 12 28 Ω

V

CC

V

= 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 5 9 Ω

CC

= 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 9 18 Ω

V

CC

= 3 V, SEL = 0 V VA = 0 V, IBA = 8 mA 5 8 Ω

V

CC

V

= 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA 12 Ω

CC

VCC = 3 V, SEL = VCC, VA = 0 V, IA = 8 mA 0.1 0.5 Ω
VCC = 3 V, SEL = 0 V, VA = 0 V, IA = 8 mA 0.1 0.5 Ω

POWER REQUIREMENTS

V

CC

Quiescent Power Supply Current I

Increase in ICC per Input

NOTES

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Typical values are at 25°C, unless otherwise stated.

3

Guaranteed by design, not subject to production test.

4

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

5

Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.

6

See Timing Measurement Information section.

7

This current applies to the control pin EN only. The A and B ports contribute no significant ac or dc currents as they transition.

Specifications subject to change without notice.

7

⌬I

CC

CC

Digital Inputs = 0 V or VCC; SEL = V
Digital Inputs = 0 V or V

; SEL = 0 V 0.1 0.2 mA

CC

CC

VCC = 3.6 V, EN = 3.0 V; SEL = VCC; IN = V

2.3 3.6 V

0.01 1 µA

CC

0.15 8 µA

REV. 0–2–

ADG3249

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

ADG3249

GND

A1

EN

IN

SEL

V

CC

A0

B

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 206°C/W

␪

JA

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

Table II. Truth Table

EN IN SEL* FUNCTION

HXX Disconnect
LLLA0 = B; 3.3 V to 1.8 V Level Shifting

LLHA0 = B; 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
LHLA1 = B; 3.3 V to 1.8 V Level Shifting
LHHA1 = B; 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting

*SEL = 0 V only when VDD = 3.3 V  10%

PIN CONFIGURATION

8-Lead SOT-23

Table I. Pin Function Descriptions

Pin No. Mnemonic Description

1 EN Enable (Active Low)
2A0 Port A0, Input or Output
3A1 Port A1, Input or Output
4 GND Ground Reference
5B Port B, Input or Output
6INChannel Select

7 SEL Level Translation Select
8V

CC

Positive Power Supply Voltage

ORDERING GUIDE

Model Temperature Range Package Description Package Branding

ADG3249BRJ-R2 –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SHA
ADG3249BRJ-REEL –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SHA
ADG3249BRJ-REEL7 –40°C to +85°CSOT-23 (Small Outline Transistor Package) RJ-8 SHA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3249 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0

–3–

ADG3249

TERMINOLOGY

V

CC

Positive Power Supply Voltage.
GND Ground (0 V) Reference.
V

INH

V

INL

I

I

I

OZ

I

OL

V

P

Minimum Input Voltage for Logic 1.

Maximum Input Voltage for Logic 0.

Input Leakage Current at the Control Inputs.

OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.

ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.

Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when

the switch input voltage is equal to the supply voltage.
R

ON

Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified

amount of current through the switch.
⌬R

ON

C

OFF OFF Switch Capacitance.

X

C

ON ON Switch Capacitance.

X

C

, C

SEL

, C

IN

I

CC

ON Resistance Match between Any Two Channels, i.e., RON max to R

Control Input Capacitance. This consists of IN, SEL, and EN.

EN

ON

min.

Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.

It is measured when all control inputs are at a logic high or low level and the switches are OFF.
⌬I
t

t

PLH

PZH

CC

, t

, t

PHL

PZL

Extra power supply current component for the EN control input when the input is not driven at the supplies.

Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant

R

× CL, where CL is the load capacitance.

ON

Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on

in response to the control signal, EN.
t

PHZ

, t

PLZ

Bus Disable Times. These are the time taken to place the switch in the high impedance OFF state in response to the

control signal. They are measured as the time taken for the output voltage to change by V

from the original

⌬

quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable

and disable times.)
t

BBM

t

TRANS

On or Off Time. Measured between the 90% points of both switches when switching fom one to another.

Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the

OUT signal.
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.

REV. 0–4–