Analog Devices ADG3247 Datasheet

2.5 V/3.3 V, 16-Bit, 2-Port

Level Translating, Bus Switch

ADG3247

FEATURES
225 ps Propagation Delay through the Switch

4.5  Switch Connection between Ports
Data Rate 1.244 Gbps

2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Small Signal Bandwidth 610 MHz
Level Translation

3.3 V to 2.5 V

3.3 V to 1.8 V

2.5 V to 1.8 V

40-Lead 6 mm  6 mm LFCSP and 38-Lead TSSOP

Packages

APPLICATIONS

3.3 V to 1.8 V Voltage Translation

3.3 V to 2.5 V Voltage Translation

2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Plug
Hot Swap
Analog Switching Applications

GENERAL DESCRIPTION

The ADG3247 is a 2.5 V or 3.3 V 16-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.

The ADG3247 is organized as dual 8-bit bus switches with
separate bus enable (BEx) inputs. This allows the device to be
used as two 8-bit digital switches or one 16-bit bus switch. These
bus switches allow bidirectional signals to be switched when ON.
In the OFF condition, signal levels up to the supplies are blocked.

This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs occurs. Similarly, if the device is operated
from a 2.5 V supply and 2.5 V inputs are applied, the device will
translate the outputs to 1.8 V. In addition to this, the ADG3247
has a level translating select pin (SEL). When SEL is low, V

CC

is
reduced internally, allowing for level translation between 3.3 V
inputs and 1.8 V outputs. This makes the device suited to appli­cations requiring level translation between different supplies, such
as converter to DSP/microcontroller interfacing.

FUNCTIONAL BLOCK DIAGRAM

A0

A7

BE1

A8

A15

BE2

PRODUCT HIGHLIGHTS

B0

B7

B8

B15

1. 3.3 V or 2.5 V supply operation

2. Extremely low propagation delay through switch

3. 4.5 W switches connect inputs to outputs

4. Level/voltage translation

5. 40-lead 6 mm ⫻ 6 mm LFCSP and 38-lead TSSOP packages

REV. 0

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Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADG3247–SPECIFICATIONS

(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T

1

noted.)

MIN

to T

, unless otherwise

MAX

Parameter Symbol Conditions Min Typ

B Version

2

Max Unit

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V

Input Low Voltage V

Input Leakage Current I
OFF State Leakage Current I
ON State Leakage Current I
Maximum Pass Voltage V

INH

V

INH

INL

V

INL

I

OZ

OL

P

VCC = 2.7 V to 3.6 V 2.0 V
VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 0.8 V
VCC = 2.3 V to 2.7 V 0.7 V

± 0.01 ± 1 mA

0 ⱕ A, B ⱕ V
0 ⱕ A, B ⱕ V

CC

CC

± 0.01 ± 1 mA
± 0.01 ± 1 mA

VA/VB = VCC = SEL = 3.3 V, IO = –5 mA 2.0 2.5 2.9 V

= VCC = SEL = 2.5 V, IO = –5 mA 1.5 1.8 2.1 V

V

A/VB

VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 mA 1.5 1.8 2.1 V

CAPACITANCE

3

A Port Off Capacitance CA OFF f = 1 MHz 5 pF
B Port Off Capacitance C
A, B Port On Capacitance
Control Input Capacitance C

SWITCHING CHARACTERISTICS

Propagation Delay A to B or B to A, t
Propagation Delay Matching
Bus Enable Time BEx to A or B
Bus Disable Time BEx to A or B
Bus Enable Time BEx to A or B
Bus Disable Time BEx to A or B
Bus Enable Time BEx to A or B
Bus Disable Time BEx to A or B

3

5

PD

6

6

6

6

6

6

OFF f = 1 MHz 5 pF

B

CA, CB ON

IN

4

t

PHL, tPLHCL

t

PZH

t

PHZ

t

PZH

t

PHZ

t

PZH

t

PHZ

f = 1 MHz 10 pF
f = 1 MHz 6 pF

, t

PZLVCC

, t

PLZVCC

, t

PZLVCC

, t

PLZVCC

, t

PZLVCC

, t

PLZVCC

= 50 pF, VCC =

= 3.0 V to 3.6 V;
= 3.0 V to 3.6 V;
= 3.0 V to 3.6 V;
= 3.0 V to 3.6 V;
= 2.3 V to 2.7 V;
= 2.3 V to 2.7 V;

SEL =

3 V 0.225 ns

SEL = V
SEL = V
SEL = 0 V
SEL = 0 V

SEL = V

SEL = V

CC

CC

CC

CC

1 3.2 4.8 ns
1 3.2 4.8 ns

0.5 2.2 3.3 ns

0.5 1.7 2.9 ns

0.5 2.2 3 ns

0.5 1.75 2.6 ns

22.5 ps

Maximum Data Rate VCC = SEL = 3.3 V; VA/VB = 2 V 1.244 Gbps
Channel Jitter VCC = SEL = 3.3 V; VA/VB = 2 V 50 ps p-p

Operating Frequency—Bus Enable f

BEx

10 MHz

DIGITAL SWITCH

On Resistance R

On Resistance Matching DR

ON

ON

VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA

4.5 8
15 28
59
11 18
58
14

0.45

0.65

W
W
W
W
W
W
W
W

POWER REQUIREMENTS

V

CC

Quiescent Power Supply Current I

Increase in ICC per Input

NOTES

1

Temperature range is as follows: B Version: –40∞C to +85∞C.

2

Typical values are at 25∞C, unless otherwise stated.

3

Guaranteed by design, not subject to production test.

4

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

5

Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.

6

See Timing Measurement Information section.

7

This current applies to the control pins (BEx) only. The A and B ports contribute no significant ac or dc currents as they transition.

Specifications subject to change without notice.

7

I
D I

CC

CC

CC

Digital Inputs = 0 V or VCC; SEL = V

CC

Digital Inputs = 0 V or VCC; SEL = 0 V 0.65 1.2 mA
V

= 3.6 V, BE1 = 3.0 V;

CC

BE2 = VCC or GND;

SEL = V

CC

2.3 3.6 V

0.001 1 mA

85 mA

REV. 0–2–

ADG3247

1

2

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V

DC Output Current . . . . . . . . . . . . . . . . . . 25 mA per channel

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

LFCSP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 32°C/W

θ

JA

TSSOP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 98°C/W

θ

JA

Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG3247BCP –40°C to +85°CLead Frame Chip Scale Package (LFCSP) CP-40
ADG3247BCP-REEL7 –40°C to +85°CLead Frame Chip Scale Package (LFCSP) CP-40
ADG3247BRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-38
ADG3247BRU-REEL7 –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-38

Table I. Pin Description

Mnemonic Description

BEx Bus Enable (Active Low)
SEL Level Translation Select

Ax Port A, Inputs or Outputs
Bx Port B, Inputs or Outputs

BEx SEL* Function

LL A = B, 3.3 V to 1.8 V Level Shifting
LH A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
HX Disconnect

*SEL = 0 only when VDD = 3.3 V ± 10%

Table II. Truth Table

PIN CONFIGURATION

40-Lead LFCSP and 38-Lead TSSOP

1

SEL

2

CC

40 A5

39 A4

38 A3

37 A2

A6

1

A7

2

A8

3

A9

4

A10

5

A11

6

A12

7

A13

8

A14

9

A15

10

PIN 1
INDICATOR

ADG3247

TOP VIEW

NC 12

NC 13

NC 14

GND 11

NC = NO CONNECT

36 A1

35 A0

B15 15

B14 16

33 V

34 SEL

B12 18

B13 17

32 BE2

31 BE1

B10 20

B11 19

30 B0
29 B1
28 B2
27 B3
26 B4
25 B5
24 B6
23 B7
22 B8
21 B9

A0

3

A1

ADG3247

4

A2

TOP VIEW

5

A3

(Not to Scale)

6

A4

7

A5

8

A6

9

A7

10

A8

11

A9

12

A10

13

A11

14

A12

A13

15

A14

16

17

A15

18

GND

19

NC

NC = NO CONNECT

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3247 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

38

V

CC

37

BE

36

BE

35

B0

34

B1

33

B2

32

B3

B4

31

30

B5

29

B6

28

B7

27

B8

26

B9

25

B10

24

B11

23

B12

22

B13

21

B14

20

B15

REV. 0

–3–

ADG3247

TERMINOLOGY

V

CC

GND Ground (0 V) Reference.

V

INH

V

INL

I

I

I

OZ

I

OL

V

P

R

ON

⌬R

ON

C

OFF OFF Switch Capacitance.

X

C

ON ON Switch Capacitance.

X

C

IN

I

CC

⌬I

CC

t

, t

PLH

PHL

t

, t

PZH

PZL

t

, t

PHZ

PLZ

Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.

Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.

f

BEx

Positive Power Supply Voltage.

Minimum Input Voltage for Logic 1.

Maximum Input Voltage for Logic 0.

Input Leakage Current at the Control Inputs.

OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.

ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.

Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.

Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.

On Resistance Match between Any Two Channels, i.e., R

Max – R

ON

ON

Min.

Control Input Capacitance. This consists of BEx and SEL.

Quiescent Power Supply Current. It is measured when all control inputs are at a logic HIGH or LOW level and
the switches are OFF.

Extra power supply current component per each BEx control input when the Input is not driven at the supplies.

Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant

⫻ CL, where CL is the load capacitance.

R

ON

Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BEx.

Bus Disable Times. These are the times taken to place the switch in the high impedance OFF state in response to the
control signal. They are measured as the time taken for the output voltage to change by V

from the original quiescent

⌬

level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)

Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable (BEx) can be toggled.

REV. 0–4–