Analog Devices ADG3245 Datasheet
2.5 V/3.3 V, 8-Bit, 2-Port
Level Translating, Bus Switch
ADG3245
FEATURES
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
20-Lead TSSOP and LFCSP Packages
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications
GENERAL DESCRIPTION
The ADG3245 is a 2.5 V or 3.3 V, 8-bit, 2-port digital switch.
It is designed on Analog Devices’ low voltage CMOS process,
which provides low power dissipation yet gives high switching
speed and very low on resistance, allowing inputs to be connected
to outputs without additional propagation delay or generating
additional ground bounce noise.
The switches are enabled by means of the bus enable (BE) input
signal. These digital switches allow bidirectional signals to be
switched when ON. In the OFF condition, signal levels up to
the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition to this, a
level translating select pin (SEL) is included. When SEL is low,
V
is reduced internally, allowing for level translation between
CC
3.3 V inputs and 1.8 V outputs. This makes the device suited to
applications requiring level translation between different supplies,
such as converter to DSP/microcontroller interfacing.
FUNCTIONAL BLOCK DIAGRAM
A0
A7
BE
PRODUCT HIGHLIGHTS
B0
B7
1. 3.3 V or 2.5 V supply operation
2. Extremely low propagation delay through switch
3. 4.5 W switches connect inputs to outputs
4. Level/voltage translation
5. 20-lead TSSOP and LFCSP (4 mm ¥ 4 mm) packages
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
ADG3245–SPECIFICATIONS
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications T
1
otherwise noted.)
MIN
to T
, unless
MAX
B Version
Parameter Symbol Conditions Min Typ2Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
OFF State Leakage Current I
INH
V
INH
INL
V
INL
I
OZ
ON State Leakage Current 0 £ A, B £ V
Maximum Pass Voltage V
P
VCC = 2.7 V to 3.6 V 2.0 V
VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 0.8 V
VCC = 2.3 V to 2.7 V 0.7 V
± 0.01 ± 1 mA
0 £ A, B £ V
CC
CC
± 0.01 ± 1 mA
± 0.01 ± 1 mA
VA/VB = VCC = SEL = 3.3 V, IO = –5 mA 2.0 2.5 2.9 V
= VCC = SEL = 2.5 V, IO= –5 mA1.51.82.1V
V
A/VB
VA/VB = VCC = 3.3 V, SEL = 0 V, IO= –5 mA 1.5 1.8 2.1 V
CAPACITANCE
3
A Port Off Capacitance CA OFF f = 1 MHz 5 pF
B Port Off Capacitance C
A, B Port On Capacitance C
Control Input Capacitance C
SWITCHING CHARACTERISTICS
Propagation Delay A to B or B to A, t
Propagation Delay Matching
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
3
5
PD
6
6
6
6
6
6
Maximum Data Rate V
Channel Jitter V
Operating Frequency—Bus Enable f
OFF f = 1 MHz 5 pF
B
, CB ON f = 1 MHz 10 pF
A
IN
4
t
, t
PHL
t
, t
PZH
t
, t
PHZ
t
, t
PZH
t
, t
PHZ
t
, t
PZH
t
, t
PHZ
BE
f = 1 MHz 6 pF
CL = 50 pF, VCC = SEL = 3 V 0.225 ns
PLH
VCC = 3.0 V to 3.6 V; SEL = V
PZL
VCC = 3.0 V to 3.6 V; SEL = V
PLZ
VCC = 3.0 V to 3.6 V; SEL = 0 V 0.5 2.2 3.3 ns
PZL
VCC = 3.0 V to 3.6 V; SEL = 0 V 0.5 1.7 2.9 ns
PLZ
VCC = 2.3 V to 2.7 V; SEL = V
PZL
VCC = 2.3 V to 2.7 V; SEL = V
PLZ
= SEL = 3.3 V; VA/VB = 2 V 1.244 Gbps
CC
= SEL = 3.3 V; VA/VB = 2 V 50 ps p-p
CC
CC
CC
CC
CC
1 3.2 4.8 ns
1 3.2 4.8 ns
0.5 2.2 3 ns
0.5 1.75 2.6 ns
22.5 ps
10 MHz
DIGITAL SWITCH
On Resistance R
On Resistance Matching ⌬R
ON
ON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 4.5 8 W
V
= 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA 15 28 W
CC
= 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 5 9 W
V
CC
= 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 11 18 W
V
CC
V
= 3 V, SEL = 0 V VA = 0 V, IBA = 8 mA 5 8 W
CC
= 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA 14 W
V
CC
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA 0.45 W
VCC = 3 V, SEL = VCC, VA = 1 V, IBA = 8 mA 0.65 W
POWER REQUIREMENTS
V
CC
Quiescent Power Supply Current I
Increase in ICC per Input
NOTES
1
Temperature range is as follows: B Version: –40∞C to +85∞C.
2
Typical values are at 25∞C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information section.
7
This current applies to the control pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
7
⌬I
CC
CC
Digital Inputs = 0 V or VCC; SEL = V
Digital Inputs = 0 V or V
VCC = 3.6 V, BE = 3.0 V; SEL = V
; SEL = 0 V 0.65 1.2 mA
CC
CC
CC
2.3 3.6 V
0.001 1 mA
130 mA
REV. 0–2–
ADG3245
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . . 25 mA per channel
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
LFCSP Package
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .30.4°C/W
JA
TSSOP Package
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 143°C/W
JA
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG3245BCP –40°C to +85°CLead Frame Chip Scale Package (LFCSP) CP-20
ADG3245BCP-REEL7 –40°C to +85°CLead Frame Chip Scale Package (LFCSP) CP-20
ADG3245BRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-20
ADG3245BRU-REEL7 –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-20
Table I. Pin Description
Mnemonic Description
BE Bus Enable (Active Low)
SEL Level Translation Select
Ax Port A, Inputs or Outputs
Bx Port B, Inputs or Outputs
BE SEL* Function
LL A = B, 3.3 V to 1.8 V Level Shifting
LH
HX Disconnect
*SEL = 0 V only when VDD = 3.3 V ± 10%
Table II. Truth Table
A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting
PIN CONFIGURATION
20-Lead LFCSP and TSSOP
SEL 1
A4 2
A5 3
A6 4
A7 5
20 A3
19 A2
18 A1
17 A0
PIN 1
INDICATOR
ADG3245
TOP VIEW
B7 7
B6 8
B5 9
GND 6
CC
16 V
B4 10
15 BE
14 B0
13 B1
12 B2
11 B3
SEL
A0
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
ADG3245
TOP VIEW
6
(Not to Scale)
7
8
9
10
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3245 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
20
V
CC
19
BE
18
B0
17
B1
16
B2
15
B3
14
B4
13
B5
12
B6
11
B7
REV. 0
–3–
ADG3245
TERMINOLOGY
V
CC
Positive Power Supply Voltage.
GND Ground (0 V) Reference.
V
INH
V
INL
I
I
I
OZ
I
OL
V
P
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device
when the switch input voltage is equal to the supply voltage.
R
ON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
⌬R
ON
C
OFF OFF Switch Capacitance.
X
C
ON ON Switch Capacitance.
X
C
IN
I
CC
On Resistance Match between Any Two Channels, i.e., RON Max – RON Min.
Control Input Capacitance. This consists of BE and SEL.
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic HIGH or LOW level and the switches are OFF.
⌬I
t
t
PLH
PZH
CC
, t
, t
PHL
PZL
Extra power supply current component for the BE control input when the input is not driven at the supplies.
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
R
¥ CL, where CL is the load capacitance.
ON
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BE.
t
PHZ
, t
PLZ
Bus Disable Times. This is the time taken to place the switch in the high impedance OFF state in response to the control
signal. It is measured as the time taken for the output voltage to change by V
from the original quiescent level,
⌬
with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and disable times.)
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
f
BE
Operating Frequency of Bus Enable. This is the maximum frequency at which bus enable (BE) can be toggled.
REV. 0–4–
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