2.5 V/3.3 V, 2-Bit Common Control
A
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FEATURES
225 ps propagation delay through the switch
4.5 Ω switch connection between ports
Data rate 1.5 Gbps
2.5 V/3.3 V supply operation
Selectable level shifting/translation
Level translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small signal bandwidth 710 MHz
8-lead SOT-23 package
APPLICATIONS
3.3 V to 2.5 V voltage translation
3.3 V to 1.8 V voltage translation
2.5 V to 1.8 V voltage translation
Bus switching
Bus isolation
Hot swap
Hot plug
Analog switch applications
Level Translator Bus Switch
ADG3242
FUNCTIONAL BLOCK DIAGRAM
0
A1
BE
Figure 1.
B0
B1
4309-001
GENERAL DESCRIPTION
The ADG3242 is a 2.5 V or 3.3 V, 2-bit, 2-port, common control
digital switch. It is designed on a low voltage CMOS process, and
provides low power dissipation, yet gives high switching speed
and very low on resistance. This allows the inputs to be connected
to the outputs without additional propagation delay or generating
additional ground bounce noise.
These switches are enabled by means of a common bus enable
BE
) input signal. This digital switch allows a bidirectional signal
(
to be switched when on. In the off condition, signal levels up
to the supplies are blocked.
This device is ideal for applications requiring level translation.
hen operated from a 3.3 V supply, level translation from 3.3 V
W
inputs to 2.5 V outputs is allowed. Similarly, if the device is operated from a 2.5 V supply and 2.5 V inputs are applied, the device
translates the outputs to 1.8 V. In addition, a level translating
select pin (
SEL
) is included. When
SEL
is low, VCC is reduced
internally, allowing for level translation between 3.3 V inputs
and 1.8 V outputs. This makes the device suitable for applications
requiring level translation between different supplies, such as
converter to DSP/microcontroller interfacing.
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation.
xtremely low propagation delay through switch.
2. E
3. 4.5 Ω swi
4. L
5. T
tches connect inputs to outputs.
evel/voltage translation.
iny SOT-23 package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
ADG3242
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TABLE OF CONTENTS
Features.............................................................................................. 1
Timing Measurement Information.............................................. 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 6
Terminology .................................................................................... 10
REVISION HISTORY
9/06—Rev. 0 to Rev. A
Bus Switch Applications ................................................................ 12
Mixed Voltage Operation, Level Translation.......................... 12
3.3 V to 2.5 V Translation ......................................................... 12
2.5 V to 1.8 V Translation ......................................................... 12
3.3 V to 1.8 V Translation ......................................................... 12
Bus Isolation................................................................................ 13
Hot Plug and Hot Swap Isolation............................................. 13
Analog Switching ....................................................................... 13
High Impedance during Power-Up/Power-Down................. 13
Outline Dimensions....................................................................... 14
Ordering Guide............................................................................... 14
Updated Format..................................................................Universal
Added Table 4.................................................................................... 5
Changes to the Ordering Guide.................................................... 14
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG3242
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SPECIFICATIONS
VCC = 2.3 V to 3.6 V, GND = 0 V; all specifications T
MIN
to T
, unless otherwise noted.
MAX
Table 1.
B Version
Parameter Symbol Conditions Min Typ2 Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage V
V
Input Low Voltage V
V
VCC = 2.7 V to 3.6 V 2.0 V
INH
= 2.3 V to 2.7 V 1.7 V
CC
VCC = 2.7 V to 3.6 V 0.8 V
INL
= 2.3 V to 2.7 V 0.7 V
CC
Input Leakage Current II ±0.01 ±1 μA
Off State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
On State Leakage Current 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
Maximum Pass Voltage VP
V
V
V
A/VB
A/VB
A/VB
SEL
= VCC =
= VCC =
= 3.3 V, IO = −5 μA
SEL
= 2.5 V, IO = −5 μA
= VCC = 3.3 V,
SEL
= 0 V, IO = −5 μA
2.0 2.5 2.9 V
1.5 1.8 2.1 V
1.5 1.8 2.1 V
CAPACITANCE3
A Port Off Capacitance CA OFF f = 1 MHz 3.5 pF
B Port Off Capacitance CB OFF f = 1 MHz 3.5 pF
A, B Port On Capacitance CA, CB ON f = 1 MHz 7 pF
Control Input Capacitance CIN f = 1 MHz 4 pF
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, t
4
t
PD
PHL
, t
PLH
C
= 50 pF, VCC =
L
SEL
= 3 V
0.225 ns
Propagation Delay Matching5 5 ps
, t
Bus Enable Time BE to A or B6
t
PZH
PZL
, t
Bus Disable Time BE to A or B6
t
PHZ
PLZ
Maximum Data Rate
Channel Jitter
V
= 3.0 V to 3.6 V;
CC
V
= 3.0 V to 3.6 V;
CC
V
= 2.3 V to 2.7 V;
CC
V
= 3.0 V to 3.6 V;
CC
V
= 3.0 V to 3.6 V;
CC
V
= 2.3 V to 2.7 V;
CC
SEL
V
=
= 3.3 V; VA/VB = 2 V
CC
SEL
V
=
= 3.3 V; VA/VB = 2 V
CC
SEL
SEL
SEL
SEL
SEL
SEL
= VCC
= 0 V
= VCC
= VCC
= 0 V
= VCC
1 3.2 4.6 ns
1 3 4 ns
1 3 4 ns
1 3 4 ns
1 2.5 3.8 ns
1 2.5 3.4 ns
1.5 Gbps
45 ps p-p
DIGITAL SWITCH
On Resistance RON
On Resistance Matching ∆RON
V
V
V
V
V
V
V
V
= 3 V,
CC
= 3 V,
CC
= 2.3 V,
CC
= 2.3 V,
CC
= 3 V,
CC
= 3 V,
CC
= 3 V,
CC
= 3 V,
CC
SEL
= VCC, VA = 0 V, IBA = 8 mA
SEL
= VCC, VA = 1.7 V, IBA = 8 mA
SEL
= VCC, VA = 0 V, IBA = 8 mA
SEL
= VCC, VA = 1 V, IBA = 8 mA
SEL
= 0 V, VA = 0 V, IBA = 8 mA
SEL
= 0 V, VA = 1 V, IBA = 8 mA
SEL
= VCC, VA = 0 V, IA = 8 mA
SEL
= 0 V, VA = 0 V, IA = 8 mA
4.5 8 Ω
12 28 Ω
5 9 Ω
9 18 Ω
5 8 Ω
12 Ω
0.1 0.5 Ω
0.1 0.5 Ω
POWER REQUIREMENTS
VCC 2.3 3.6 V
Quiescent Power Supply Current ICC
Increase in ICC per Input7 ∆ICC
1
Temperature range is as follows: B version: −40°C to +85°C.
2
Typical values are at 25°C, unless otherwise stated.
3
Guaranteed by design, not subject to production test.
4
The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5
Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6
See Timing Measurement Information section.
7
This current applies to the Control Pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.
Digital inputs = 0 V or V
Digital inputs = 0 V or V
V
= 3.6 V, BE = 3.0 V;
CC
SEL
;
CC
;
CC
= VCC
SEL
SEL
= VCC
= 0 V
0.01 1 μA
0.1 0.2 mA
0.15 8 μA
1
Rev. A | Page 3 of 16
ADG3242
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ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
VCC to GND −0.5 V to +4.6 V
Digital Inputs to GND −0.5 V to +4.6 V
DC Input Voltage −0.5 V to +4.6 V
DC Output Current 25 mA per channel
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 206°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C
Stresses above those listed under Absolute Maximum Ratings
ma
y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
time.
one
ESD CAUTION
Rev. A | Page 4 of 16
ADG3242
V
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SEL
BE
CC
ADI DIE MARK
BE
1
A0
2
ADG3242
TOP VIEW
3
A1
(Not to Scale)
GND
4
Figure 2. Pin Configuration Figure 3. Die Pad Configuration (Die size: 550 μm × 820 μm)
8
V
CC
7
SEL
B0
6
B1
5
04309-002
B0
B1
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
BE
Bus Enable (Active Low).
2 A0 Port A0, Input or Output.
3 A1 Port A1, Input or Output.
4 GND Ground (0 V) Reference.
5 B1 Port B1, Input or Output.
6 B0 Port B0, Input or Output.
7
SEL
Level Translation Select.
8 VCC Positive Power Supply Voltage.
ADG3242
TOP VIEW
(Not to S cale)
A0
A1
GND
04309-100
Table 4. Die Pad Coordinates (Measured fro
m the Center of the Die)
Mnemonic X(μm) Y(μm)
BE
+93 +303
A0 +102 +150
A1 +168 −139
GND +126 −266
B1 −88 −247
B0 −168 +121
SEL
−111 +279
VCC −7 +303
Table 5. Truth Table
BE
1
Function
SEL
L L A0 = B0, A1 = B1, 3.3 V to 1.8 V Level Shifting.
L H A0 = B0, A1 = B1, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting.
H X Disconnect.
1
SEL
= 0 V only when VDD = 3.3 V ± 10%.
Rev. A | Page 5 of 16
ADG3242
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TYPICAL PERFORMANCE CHARACTERISTICS
40
35
TA = 25°C
SEL = V
CC
VCC= 3V
20
VCC = 3.3V
SEL = V
CC
30
25
(Ω)
20
ON
R
15
10
5
0
0.51.01.52.02.53.0
03
V
(V)
A/VB
VCC= 3.3V
VCC= 3.6V
.5
04309-003
Figure 4. On Resistance vs. Input Voltage
40
TA = 25°C
SEL = V
35
30
25
(Ω)
20
ON
R
15
10
5
CC
VCC= 2.3V
VCC= 2.5V
VCC= 2.7V
15
(Ω)
10
ON
R
5
0
02.0
Figure 7. On Resistance vs. Input Voltage for Different Temperatures
15
VCC = 2.5V
SEL = V
CC
10
(Ω)
ON
R
5
+85°C
+85°C
–40°C
0.5 1.0 1.5
(V)
V
A/VB
+25°C
+25°C
–40°C
04309-006
0
03
0.5 1.0 1.5 2.0 2.5
V
(V)
A/VB
.0
04309-004
Figure 5. On Resistance vs. Input Voltage
40
TA = 25°C
SEL = 0V
35
30
25
(Ω)
20
ON
R
15
10
5
0
0.51.01.52.02.53.0
03
V
A/VB
VCC= 3V
VCC= 3.3V
VCC= 3.6V
(V)
.5
04309-005
0
01.2
Figure 8. On Resistance vs. Input Voltage for Different Temperatures
3.0
TA = 25°C
SEL = V
CC
IO = –5µA
2.5
2.0
(V)
1.5
OUT
V
1.0
0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
03.5
Figure 6. On Resistance vs. Input Voltage
0.5 1.0
(V)
V
A/VB
VCC= 3.6V
VCC= 3V
(V)
V
A/VB
Figure 9. Pass Voltage vs. V
CC
VCC= 3.3V
04309-007
04309-008
Rev. A | Page 6 of 16
ADG3242
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2.5
2.0
TA = 25°C
SEL = V
IO = –5µA
CC
VCC= 2.7V
3.0
2.5
TA = 25°C
V
= 0V
A
BE = 0
1.5
(V)
OUT
V
1.0
0.5
0
0.5 1.0 1. 5 2. 0 2. 5
03
V
A/VB
VCC= 2.3V
(V)
Figure 10. Pass Voltage vs. V
2.5
TA = 25°C
SEL = 0V
I
= –5µA
O
2.0
1.5
(V)
OUT
V
1.0
0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
03
V
A/VB
VCC= 3V
(V)
Figure 11. Pass Voltage vs. V
500
TA = 25°C
450
400
350
300
250
(µA)
CC
I
200
150
100
50
0
050
VCC= 3.3V;
SEL = 0V
5 1015202530354045
Figure 12. I
VCC= SEL = 3.3V
VCC= SEL = 2.5V
ENABLE FREQUENCY (MHz)
vs. Enable Frequency
CC
VCC= 2.5V
CC
VCC= 3.6V
VCC= 3.3V
CC
.0
4309-009
.5
04309-010
04309-011
2.0
(V)
1.5
OUT
V
1.0
0.5
0
00.10
0.02 0.04 0.06 0.08
Figure 13. Output Low Characteristic
3.0
TA = 25°C
V
= V
A
CC
BE = 0
2.5
2.0
(V)
1.5
OUT
V
1.0
VCC= SEL = 2.5V
0.5
V
0
–0.10 0
CC
–0.08 –0.06 –0.04 –0.02
Figure 14. Output High Characteristic
0
TA = 25°C
SEL = V
CC
ON→OFF
–0.2
C
= 1nF
L
–0.4
(pC)
–0.6
INJ
Q
–0.8
–1.0
–1.2
03.02.52.01.51.00.5
Figure 15. Charge Injection vs. Source Voltage
VCC= SEL = 3. 3V
= 3.3V; SE L = 0V
VCC= 2.5V
V
= 3.3V
CC
V
VCC= SEL = 3. 3V
I
(A)
O
I
(A)
O
(V)
A/VB
VCC= 3.3V; SEL = 0V
VCC= SEL = 2. 5V
4309-012
4309-013
4309-014
Rev. A | Page 7 of 16
ADG3242
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2
1
0
–1
–2
–3
–4
TA = 25°C
ATTENUATION (dB)
–5
V
= 3.3V/2.5V
CC
SEL = V
–6
–7
–8
0.03 1000
CC
VIN = 0dBm
N/W ANALYZE R:
R
= RS = 50Ω
L
10.1 10 100
FREQUENCY (MHz)
Figure 16. Bandwidth vs. Frequency
0
TA = 25°C
= 3.3V/2.5V
V
–10
CC
SEL = V
–20
–30
–40
–50
–60
ATTENUATIO N (dB)
–70
–80
–90
–100
0.03 1000
CC
VIN = 0dBm
N/W ANAL YZER:
= RS = 50Ω
R
L
10.1 10 100
FREQUENCY (MHz)
Figure 17. Crosstalk vs. Frequency
0
TA = 25°C
= 3.3V/2.5V
V
–10
CC
SEL = V
–20
–30
–40
–50
–60
ATTENUATION (dB)
–70
–80
–90
–100
0.1 1000
CC
VIN = 0dBm
N/W ANALYZE R:
= RS = 50Ω
R
L
110100
FREQUENCY (MHz)
Figure 18. Off Isolation vs. Fr
equency
04309-015
04309-016
04309-017
4.0
VCC= SEL = 3.3V
3.5
3.0
2.5
2.0
VCC= 3.3V; SEL = 0V
TIME (ns)
1.5
1.0
0.5
0
–20 0 20 40 60
–40 80
TEMPERATURE (°C)
ENABLE
DISABLE
Figure 19. Enable/Disable Time vs. Temperature
4.0
3.5
ENABLE
3.0
2.5
DISABLE
2.0
TIME (ns)
1.5
1.0
0.5
0
–20 0 20 40 60
–40 80
TEMPERATURE (° C)
VCC= SEL = 2. 5V
Figure 20. Enable/Disable Time vs. Temperature
100
VCC= SEL = 3. 3V
90
= 1.5V p-p
V
IN
20dB ATTENUATION
80
70
60
50
40
JITTER (ps p-p)
30
20
10
0
0.5 1.91.71.51.31.10.90.7
DATA RATE (Gb ps)
Figure 21. Jitter vs. Data Rate; PRBS 31
4309-018
04309-019
4309-020
Rev. A | Page 8 of 16
ADG3242
www.BDTIC.com/ADI
100
95
VCC= SEL = 3. 3V
90
= 1.5V p-p
V
IN
20dB ATTENUATION
85
80
75
70
EYE WIDTH (%)
65
60
55
% EYE WIDTH = ((CLOCK PERI OD –
JITTER p -p)/CL OCK PERIOD) × 100%
50
0.5 1.91.71.51.31.10.90.7
DATA RATE (Gb ps)
Figure 22. Eye Width vs. Data Rate; PRBS 31
20mV/DIV
200ps/DIV
4309-021
Figure 24. Eye Pattern; 1.244 Gbps, V
= 2.5V
V
CC
SEL = 2.5V
V
= 1.5V p-p
IN
20dB
ATTENUATION
TA = 25°C
04309-023
= 2.5 V; PRBS 31
CC
= 3.3V
V
CC
50mV/DIV
200ps/DIV
SEL = 3.3V
V
= 1.5V p-p
IN
Figure 23. Eye Pattern; 1.5 Gbps, V
20dB
ATTENUATION
TA = 25°C
= 3.3 V; PRBS 31
CC
04309-022
Rev. A | Page 9 of 16
ADG3242
www.BDTIC.com/ADI
TERMINOLOGY
VCC
Positive power supply voltage.
C
IN
Control input capacitance. This consists of
BE
and
SEL
.
GND
Ground (0 V) reference.
V
INH
Minimum input voltage for Logic 1.
V
INL
Maximum input voltage for Logic 0.
I
I
Input leakage current at the control inputs.
I
OZ
Off state leakage current. It is the maximum leakage current at
he switch pin in the off state.
t
I
OL
On state leakage current. It is the maximum leakage current at
he switch pin in the on state.
t
V
P
Maximum pass voltage. The maximum pass voltage relates to
he clamped output voltage of an NMOS device when the switch
t
input voltage is equal to the supply voltage.
R
ON
Ohmic resistance offered by a switch in the on state. It is measured
t a given voltage by forcing a specified amount of current through
a
the switch.
ΔR
ON
On resistance match between any two channels, that is, R
to R
min.
ON
OFF
C
X
ON
max
Off switch capacitance.
C
ON
X
On switch capacitance.
I
CC
Quiescent power supply current. This current represents the
akage current between the V
le
and ground pins. It is measured
CC
when all control inputs are at logic high or low level and the
switches are off.
ΔI
CC
EN
Extra power supply current component for the
control input
when the input is not driven at the supplies.
t
, t
PLH
PHL
Data propagation delay through the switch in the on state. Propaga-
n delay is related to the RC time constant R
tio
× CL, where CL
ON
is the load capacitance.
, t
PZH
PHZ
PZL
in
T
BE
.
, t
PLZ
t
Bus enable times. These are the times taken to cross the V
response to the control signal,
t
Bus disable times. These are the times taken to place the switch
he high impedance off state in response to the control signal.
in t
They are measured as the time taken for the output voltage to
change by V
from the original quiescent level, with reference
Δ
to the logic level transition at the control input. (See Figure 27
fo
r enable and disable times.)
Max Data Rate
Maximum rate at which data can be passed through the switch.
Channel Jitter
Peak-to-peak value of the sum of the deterministic and random
tter of the switch channel.
ji
Rev. A | Page 10 of 16
ADG3242
V
C
V
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TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that
is used is V
V
= VA and V
IN
PULSE
GENERATOR
and V
IN
where:
OUT
= VB, or VIN = VB and V
OUT
CC
V
IN
DUT
R
T
= VA
OUT
2 × V
SW1
R
V
OUT
C
L
L
R
L
GND
ENABLE
CONTRO L INPUT BE
t
PZL
V
CC
IN
IN
= 0V
= V
SW1 @ 2V
CC
V
OUT
V
OUT
SW1 @ GND
CC
CC
V
T
t
PZH
V
T
0V
Figure 27. Enable and Dis
DISABLE
t
PLZ
t
PHZ
able Times
V
INH
V
T
0V
V
CC
VL + V
V
L
V
H
VH–V
0V
Δ
Δ
04309-026
NOTES
1. PULSE GENERATOR FOR ALL PULSES:
FREQUENCY ≤ 10MHz .
INCLUDES BOARD, S TRAY, AND LOAD CAPACITANCES.
2. C
L
IS THE TERM INATION RESISTOR, SHOULD BE EQUAL TO Z
3. R
T
OF THE PULSE GENERATOR.
t
≤ 2.5ns,
R
Figure 25. Load Circuit
t
≤ 2.5ns,
F
OUT
04309-024
Table 6. Switch Position
Test S1
t
, t
2 × VCC
PLZ
PZL
t
, t
GND
PHZ
PZH
ONTROL
INPUT BE
V
OUT
t
PLH
t
PLH
Figure 26. Propagation Delay
IH
V
T
0V
V
H
V
T
V
L
4309-025
Table 7. Test Conditions
Symbol
VCC = 3.3 V ± 0.3 V (
= VCC) VCC = 2.5 V ± 0.2 V (
SEL
= VCC) VCC = 3.3 V ± 0.3 V (
SEL
SEL
= 0 V)
Unit
RL 500 500 500 Ω
VΔ 300 150 150 mV
C
50 30 30 pF
L
V
1.5 0.9 0.9 V
T
Rev. A | Page 11 of 16
ADG3242
V
V
V
V
V
V
V
V
V
V
V
V
V
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BUS SWITCH APPLICATIONS
MIXED VOLTAGE OPERATION, LEVEL TRANSLATION
Bus switches provide an ideal solution for interfacing between
mixed voltage systems. The ADG3242 is suitable for applications
where voltage translation from 3.3 V technology to a lower voltage
technology is needed. This device translates from 3.3 V to 1.8 V,
from 2.5 V to 1.8 V, or from a bidirectional 3.3 V directly to 2.5 V.
Figure 28 shows a block diagram of a typical application in which a
user needs to interface between a 3.3 V ADC and a 2.5 V microprocessor. The microprocessor does not have 3.3 V tolerant inputs,
therefore, placing the ADG3242 between the two devices allows
the devices to communicate easily. The bus switch directly connects
the two blocks, therefore introducing minimal propagation delay,
timing skew, or noise.
3.3
3.3
2.5
2.5 V TO 1.8 V TRANSLATION
When VCC is 2.5 V (
0 V to V
, the maximum output signal is also clamped within
CC
a voltage threshold below the V
is limited to approximately 1.8 V, as shown in Figure 32.
2.5V
Figure 31. 2.5 V to 1.8 V Voltage Translation,
SEL
= 2.5 V) and the input signal range is
supply. In this case, the output
CC
2.5
ADG3242
OUT
1.8
2.5V SUPPLY
SEL = 2.5V
1.8V
SEL
= 2.5 VCC
04309-030
3.3V ADC
ADG3242
2.5V
MICROPROCESSOR
04309-027
Figure 28. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor
3.3 V TO 2.5 V TRANSLATION
When VCC is 3.3 V (
0 V to V
, the maximum output signal is clamped to within a
CC
voltage threshold below the V
is limited to 2.5 V, as shown in Figure 30. This device can be used
for translation from 2.5 V to 3.3 V devices and also between two
3.3 V devices.
3.3
2.5V
Figure 29. 3.3 V to 2.5 V Voltage Translation,
SEL
= 3.3 V) and the input signal range is
supply. In this case, the output
CC
3.3
ADG3242
OUT
2.5
3.3V SUPPLY
SEL = 3.3V
SEL
2.5V
2.5V
= VCC
04309-028
SWITCH
OUTPUT
V
SWITCH
0V
INPUT
Figure 32. 2.5 V to 1.8 V Voltage Translation,
2.5V
IN
04309-031
SEL
= VCC
3.3 V TO 1.8 V TRANSLATION
The ADG3242 offers the option of interfacing between a 3.3 V
SEL
device and a 1.8 V device. This is possible through use of the
pin. The
SEL
pin is an active low control pin.
SEL
activates internal circuitry in the ADG3242 that allows voltage translation
between 3.3 V devices and 1.8 V devices.
When V
is 3.3 V and the input signal range is 0 V to VCC, the
CC
maximum output signal is clamped to 1.8 V, as shown in Figure 34.
To d o th i s, t he
SEL
pin must be tied to Logic 0. If
it can be tied directly to V
3.3V
.
CC
3.3
ADG3242
SEL
1.8V
is unused,
SWITCH
OUTPUT
V
SWITCH
0V
INPUT
Figure 30. 3.3 V to 2.5 V Voltage Translation,
3.3V
IN
04309-029
SEL
= VCC
Rev. A | Page 12 of 16
Figure 33. 3.3 V to 1.8 V Voltage Translation,
1.8
OUT
SWITCH
OUTPUT
0V
SWITCH
INPUT
3.3V SUPPLY
SEL = 0V
3.3V
V
IN
Figure 34. 3.3 V to 1.8 V Voltage Translation,
SEL
04309-033
SEL
= 0 V
= 0 V
04309-032
ADG3242
www.BDTIC.com/ADI
BUS ISOLATION
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the specifications. Because the ADG3242 is designed specifically for
applications that do not need drive, yet require simple logic functions, it solves this requirement. The device isolates access to
the bus, thus minimizing capacitance loading.
LOAD A
BUS SWITCH
LOCATIO N
Figure 35. Location of Bus Switched in a Bus Isolation Application
LOAD B
LOAD C
LOAD D
BUS/
BACKPLANE
04309-034
HOT PLUG AND HOT SWAP ISOLATION
The ADG3242 is suitable for hot swap and hot plug applications.
The output signal of the ADG3242 is limited to a voltage that
is below the V
Figure 34. Thus, the switch acts like a buffer to take the impact
rom the hot insertion, protecting vital and expensive chipsets
f
from damage.
In hot plug applications, the system cannot be shut down when
n
ew hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 36 shows a typical example of this type of application.
supply, as shown in Figure 30, Figure 32, and
CC
CPU
RAM
ADG3242 ADG3242
BUS
Figure 36. ADG3242 in a Hot Plug Application
There are many systems, such as docking stations, PCI boards for
servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be isolated
prior to insertion or removal, there is more control over the hot
swap event. This isolation can be achieved using bus switches. The
bus switches are positioned on the hot swap card between the connector and the devices. During hot swap, the ground pin of the
hot swap card must connect to the ground pin of the backplane
before connecting to any other signal or power pins.
ANALOG SWITCHING
Bus switches are used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller on and off channel capacitance, and better
frequency performance than their analog counterparts. The
bus switch channel itself, consisting solely of an NMOS switch,
limits the operating voltage (see
i
n many cases, this does not present an issue.
HIGH IMPEDANCE DURING POWER-UP/POWERDOWN
To ensure the high impedance state during power-up or power-
BE
down,
minimum value of the resistor is determined by the current sinking capability of the driver.
must be tied to VCC through a pull-up resistor. The
PLUG-IN
CARD (1)
PLUG-IN
CARD (2)
CARD I/O
CARD I/O
Figure 4 for a typical plot), but
04309-035
Rev. A | Page 13 of 16
ADG3242
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OUTLINE DIMENSIONS
2.90 BSC
2
1.95
BSC
56
0.65 BSC
2.80 BSC
1.45 MAX
SEATING
PLANE
0.22
0.08
8°
4°
0°
0.60
0.45
0.30
1.60 BSC
PIN 1
INDICATOR
1.30
1.15
0.90
0.15 MAX
847
13
0.38
0.22
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 37. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADG3242BRJ-R2 −40°C to +85°C 8-Lead Small Outline Transistor [SOT-23] RJ-8 SCA
ADG3242BRJ-REEL −40°C to +85°C 8-Lead Small Outline Transistor [SOT-23] RJ-8 SCA
ADG3242BRJ-REEL7 −40°C to +85°C 8-Lead Small Outline Transistor [SOT-23] RJ-8 SCA
ADG3242BRJZ-REEL71 −40°C to +85°C 8-Lead Small Outline Transistor [SOT-23] RJ-8 SOU
ADG3242BCZ-SF31 −40°C to +85°C Die Chip
1
Z = Pb-free part.
Rev. A | Page 14 of 16
ADG3242
www.BDTIC.com/ADI
NOTES
Rev. A | Page 15 of 16
ADG3242
www.BDTIC.com/ADI
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04309-0-9/06(A)
Rev. A | Page 16 of 16
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