ANALOG DEVICES ADG3242 Service Manual

2.5 V/3.3 V, 2-Bit Common Control

A

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FEATURES

225 ps propagation delay through the switch

4.5 Ω switch connection between ports
Data rate 1.5 Gbps

2.5 V/3.3 V supply operation
Selectable level shifting/translation
Level translation

3.3 V to 2.5 V

3.3 V to 1.8 V

2.5 V to 1.8 V
Small signal bandwidth 710 MHz
8-lead SOT-23 package

APPLICATIONS

3.3 V to 2.5 V voltage translation

3.3 V to 1.8 V voltage translation

2.5 V to 1.8 V voltage translation
Bus switching
Bus isolation
Hot swap
Hot plug
Analog switch applications

Level Translator Bus Switch

ADG3242

FUNCTIONAL BLOCK DIAGRAM

0

A1

BE

Figure 1.

B0

B1

4309-001

GENERAL DESCRIPTION

The ADG3242 is a 2.5 V or 3.3 V, 2-bit, 2-port, common control
digital switch. It is designed on a low voltage CMOS process, and
provides low power dissipation, yet gives high switching speed
and very low on resistance. This allows the inputs to be connected
to the outputs without additional propagation delay or generating
additional ground bounce noise.

These switches are enabled by means of a common bus enable

BE

) input signal. This digital switch allows a bidirectional signal

(
to be switched when on. In the off condition, signal levels up
to the supplies are blocked.

This device is ideal for applications requiring level translation.

hen operated from a 3.3 V supply, level translation from 3.3 V

W
inputs to 2.5 V outputs is allowed. Similarly, if the device is oper­ated from a 2.5 V supply and 2.5 V inputs are applied, the device
translates the outputs to 1.8 V. In addition, a level translating
select pin (

SEL

) is included. When

SEL

is low, VCC is reduced

internally, allowing for level translation between 3.3 V inputs
and 1.8 V outputs. This makes the device suitable for applications
requiring level translation between different supplies, such as
converter to DSP/microcontroller interfacing.

PRODUCT HIGHLIGHTS

1. 3.3 V or 2.5 V supply operation.

xtremely low propagation delay through switch.

2. E

3. 4.5 Ω swi

4. L

5. T

tches connect inputs to outputs.

evel/voltage translation.

iny SOT-23 package.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADG3242

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TABLE OF CONTENTS

Features.............................................................................................. 1

Timing Measurement Information.............................................. 11

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configurations and Function Descriptions ........................... 5

Typical Performance Characteristics ............................................. 6

Terminology .................................................................................... 10

REVISION HISTORY

9/06—Rev. 0 to Rev. A

Bus Switch Applications ................................................................ 12

Mixed Voltage Operation, Level Translation.......................... 12

3.3 V to 2.5 V Translation ......................................................... 12

2.5 V to 1.8 V Translation ......................................................... 12

3.3 V to 1.8 V Translation ......................................................... 12

Bus Isolation................................................................................ 13

Hot Plug and Hot Swap Isolation............................................. 13

Analog Switching ....................................................................... 13

High Impedance during Power-Up/Power-Down................. 13

Outline Dimensions....................................................................... 14

Ordering Guide............................................................................... 14

Updated Format..................................................................Universal

Added Table 4.................................................................................... 5

Changes to the Ordering Guide.................................................... 14

8/03—Revision 0: Initial Version

Rev. A | Page 2 of 16

ADG3242

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SPECIFICATIONS

VCC = 2.3 V to 3.6 V, GND = 0 V; all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 1.

B Version
Parameter Symbol Conditions Min Typ2 Max Unit

DC ELECTRICAL CHARACTERISTICS

Input High Voltage V
V
Input Low Voltage V
V

VCC = 2.7 V to 3.6 V 2.0 V

INH

= 2.3 V to 2.7 V 1.7 V

CC

VCC = 2.7 V to 3.6 V 0.8 V

INL

= 2.3 V to 2.7 V 0.7 V

CC

Input Leakage Current II ±0.01 ±1 μA
Off State Leakage Current IOZ 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
On State Leakage Current 0 ≤ A, B ≤ VCC ±0.01 ±1 μA
Maximum Pass Voltage VP

V
V
V

A/VB

A/VB

A/VB

SEL

= VCC =
= VCC =

= 3.3 V, IO = −5 μA

SEL

= 2.5 V, IO = −5 μA

= VCC = 3.3 V,

SEL

= 0 V, IO = −5 μA

2.0 2.5 2.9 V

1.5 1.8 2.1 V

1.5 1.8 2.1 V

CAPACITANCE3

A Port Off Capacitance CA OFF f = 1 MHz 3.5 pF
B Port Off Capacitance CB OFF f = 1 MHz 3.5 pF
A, B Port On Capacitance CA, CB ON f = 1 MHz 7 pF
Control Input Capacitance CIN f = 1 MHz 4 pF

SWITCHING CHARACTERISTICS3

Propagation Delay A to B or B to A, t

4

t

PD

PHL

, t

PLH

C

= 50 pF, VCC =

L

SEL

= 3 V

0.225 ns

Propagation Delay Matching5 5 ps

, t

Bus Enable Time BE to A or B6

t

PZH

PZL

, t

Bus Disable Time BE to A or B6

t

PHZ

PLZ

Maximum Data Rate
Channel Jitter

V

= 3.0 V to 3.6 V;

CC

V

= 3.0 V to 3.6 V;

CC

V

= 2.3 V to 2.7 V;

CC

V

= 3.0 V to 3.6 V;

CC

V

= 3.0 V to 3.6 V;

CC

V

= 2.3 V to 2.7 V;

CC

SEL

V

=

= 3.3 V; VA/VB = 2 V

CC

SEL

V

=

= 3.3 V; VA/VB = 2 V

CC

SEL
SEL
SEL
SEL
SEL
SEL

= VCC
= 0 V
= VCC
= VCC
= 0 V
= VCC

1 3.2 4.6 ns
1 3 4 ns
1 3 4 ns
1 3 4 ns
1 2.5 3.8 ns
1 2.5 3.4 ns

1.5 Gbps
45 ps p-p

DIGITAL SWITCH

On Resistance RON

On Resistance Matching ∆RON

V
V
V
V
V
V
V
V

= 3 V,

CC

= 3 V,

CC

= 2.3 V,

CC

= 2.3 V,

CC

= 3 V,

CC

= 3 V,

CC

= 3 V,

CC

= 3 V,

CC

SEL

= VCC, VA = 0 V, IBA = 8 mA

SEL

= VCC, VA = 1.7 V, IBA = 8 mA

SEL

= VCC, VA = 0 V, IBA = 8 mA

SEL

= VCC, VA = 1 V, IBA = 8 mA

SEL

= 0 V, VA = 0 V, IBA = 8 mA

SEL

= 0 V, VA = 1 V, IBA = 8 mA

SEL

= VCC, VA = 0 V, IA = 8 mA

SEL

= 0 V, VA = 0 V, IA = 8 mA

4.5 8 Ω
12 28 Ω
5 9 Ω
9 18 Ω
5 8 Ω
12 Ω

0.1 0.5 Ω

0.1 0.5 Ω

POWER REQUIREMENTS

VCC 2.3 3.6 V
Quiescent Power Supply Current ICC

Increase in ICC per Input7 ∆ICC

1

Temperature range is as follows: B version: −40°C to +85°C.

2

Typical values are at 25°C, unless otherwise stated.

3

Guaranteed by design, not subject to production test.

4

The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage

source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.

5

Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.

6

See Timing Measurement Information section.

7

This current applies to the Control Pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.

Digital inputs = 0 V or V
Digital inputs = 0 V or V
V

= 3.6 V, BE = 3.0 V;

CC

SEL

;

CC

;

CC

= VCC

SEL

SEL

= VCC

= 0 V

0.01 1 μA

0.1 0.2 mA

0.15 8 μA

1

Rev. A | Page 3 of 16

ADG3242

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

VCC to GND −0.5 V to +4.6 V
Digital Inputs to GND −0.5 V to +4.6 V
DC Input Voltage −0.5 V to +4.6 V
DC Output Current 25 mA per channel
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C

θJA Thermal Impedance 206°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C

Stresses above those listed under Absolute Maximum Ratings
ma

y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any

time.

one

ESD CAUTION

Rev. A | Page 4 of 16

ADG3242

V

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SEL

BE

CC

ADI DIE MARK

BE

1

A0

2

ADG3242

TOP VIEW

3

A1

(Not to Scale)

GND

4

Figure 2. Pin Configuration Figure 3. Die Pad Configuration (Die size: 550 μm × 820 μm)

8

V

CC

7

SEL

B0

6

B1

5

04309-002

B0

B1

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1

BE

Bus Enable (Active Low).

2 A0 Port A0, Input or Output.
3 A1 Port A1, Input or Output.
4 GND Ground (0 V) Reference.
5 B1 Port B1, Input or Output.
6 B0 Port B0, Input or Output.
7

SEL

Level Translation Select.

8 VCC Positive Power Supply Voltage.

ADG3242

TOP VIEW

(Not to S cale)

A0

A1

GND

04309-100

Table 4. Die Pad Coordinates (Measured fro

m the Center of the Die)

Mnemonic X(μm) Y(μm)

BE

+93 +303

A0 +102 +150
A1 +168 −139
GND +126 −266
B1 −88 −247
B0 −168 +121
SEL

−111 +279

VCC −7 +303

Table 5. Truth Table

BE

1

Function

SEL

L L A0 = B0, A1 = B1, 3.3 V to 1.8 V Level Shifting.
L H A0 = B0, A1 = B1, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting.
H X Disconnect.

1

SEL

= 0 V only when VDD = 3.3 V ± 10%.

Rev. A | Page 5 of 16