ANALOG DEVICES ADG3233 Service Manual

Low Voltage 1.65 V to 3.6 V, Bidirectional

V

Logic Level Translation, Bypass Switch

FEATURES

Operates from 1.65 V to 3.6 V supply rails
Bidirectional level translation, unidirectional signal path
8-lead SOT-23 and MSOP packages
Bypass or normal operation
Short circuit protection

APPLICATIONS

JTAG chain bypassing
Daisy-chain bypassing
Digital switching

GENERAL DESCRIPTION

The ADG32331 is a bypass switch designed on a submicron
process that operates from supplies as low as 1.65 V. The device
is guaranteed for operation over the supply range 1.65 V to 3.6 V. It
operates from two supply voltages, allowing bidirectional level
translation, that is, it translates low voltages to higher voltages
and vice versa. The signal path is unidirectional, meaning data
may only flow from A → Y.

This type of device may be used in applications that require a
bypassing function. It is ideally suited to bypassing devices in
a JTAG chain or in a daisy-chain loop. One switch could be
used for each device or a number of devices, thus allowing
easy bypassing of one or more devices in a chain. This may
be particularly useful in reducing the time overhead in testing
devices in the JTAG chain or in daisy-chain applications where
the user does not wish to change the settings of a particular device.

The bypass switch is packaged in two of the smallest footprints
available for its required pin count. The 8-lead SOT-23 package
requires only 2.9 mm × 2.8 mm board space, while the MSOP
package occupies approximately 3 mm × 4.9 mm board area.

1

U.S. Patent Number: 7,369,385 B2.

ADG3233

FUNCTIONAL BLOCK DIAGRAM

CC1VCC2

V

CC1

A1 Y1

V

CC1

A2

EN

PRODUCT HIGHLIGHTS

1. Bidirectional level translation matches any voltage level

from 1.65 V to 3.6 V.

2. The bypass switch offers high performance and is fully

guaranteed across the supply range.

3. Short circuit protection.

4. Tiny 8-lead SOT-23 package and 8-lead MSOP.

Table 1. Truth Table

EN

Signal Path Function

L

A1 → Y2, Y1 → V

H

A1 → Y2, A2 → Y2

CC1

V

V

CC1

0

1

GND

Figure 1.

Enable bypass mode
Enable normal mode

CC2VCC2

ADG3233

Y2

03297-001

Rev. A

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Fax: [phone] ©2003–2011 Analog Devices, Inc. All rights reserved.

ADG3233

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Test Waveforms ............................................................................. 5

Absolute Maximum Ratings ............................................................ 6

REVISION HISTORY

7/11—Rev. 0 to Rev. A

Changes to Patent Number, General Description Section, and

Product Highlights Section ............................................................. 1

Changes to V

→ Y1, Table 2 ............................................................................. 4

EN

Changes to Table 3 ............................................................................ 6

Updated Outline Dimensions ....................................................... 15

Changes to Ordering Guide .......................................................... 16

5/03—Revision 0: Initial Version

CC

= V

CC1

= V

= 2.5 V ± 0.2 V, ENABLE Time

CC2

ESD Caution...................................................................................6

Pin Configuration and Function Descriptions ..............................7

Typical Performance Characteristics ..............................................8

Theory of Operation ...................................................................... 13

A1 and EN Input ........................................................................ 13

Normal Operation ...................................................................... 13

Bypass Operation ....................................................................... 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 16

Rev. A | Page 2 of 16

ADG3233

SPECIFICATIONS

V

= V

CC1

= 1.65 V to 3.6 V, GND = 0 V, all specifications T

CC2

Table 2.

Parameter1 Symbol Test Conditions/Comments Min Typ2 Max Unit

LOGIC INPUTS/OUTPUTS3 V

Input High Voltage4 V

V

IH

V
V
Input Low Voltage4 VIL V
V
V

Output High Voltage (Y1) VOH I
I
I
I
I
I

Output Low Voltage (Y1) VOL I
I
I
I
I
I
LOGIC OUTPUTS3 V

Output High Voltage (Y2) VOH I

I

I

I

I

I

Output Low Voltage (Y2) VOL I
I
I
I
I
I
SWITCHING CHARACTERISTICS

VCC = V

CC1

= V

= 3.3 V ± 0.3 V

CC2

4, 5

CC2

CC1

CC1

CC1

CC1

CC1

CC1

= −100 μA, V

OH

= −100 μA, V

OH

= −100 μA, V

OH

= −4 mA, V

OH

= −4 mA, V

OH

= −8 mA, V

OH

= 100 μA, V

OL

= 100 μA, V

OL

= 100 μA, V

OL

= 4 mA, V

OL

= 4 mA, V

OL

= 8 mA, V

OL

CC1

= −100 μA, V

OH

= −100 μA, V

OH

= −100 μA, V

OH

= −4 mA, V

OH

= −4 mA,V

OH

= −8 mA, V

OH

= 100 μA, V

OL

= 100 μA, V

OL

= 100 μA, V

OL

= 4 mA, V

OL

= 4 mA, V

OL

= 8 mA, V

OL

Propagation Delay, tPD

t

, t

CL = 30 pF, VT = VCC/2 3.5 5.4 ns

PHL

A1 → Y1 Normal Mode
A2 →Y2 Normal Mode
A1 → Y2 Bypass Mode
ENABLE Time EN → Y1

DISABLE Time EN → Y1

ENABLE Time EN → Y2

DISABLE Time EN → Y2

PLH

t

, t

CL = 30 pF, VT = VCC/2 3.5 5.4 ns

PHL

PLH

, t

CL = 30 pF, VT = VCC/2 4 6.5 ns

t

PHL

PLH

C

t

EN

t

C

DIS

t

C

EN

t

C

DIS

= 30 pF, VT = VCC/2 4 6 ns

L

= 30 pF, VT = VCC/2 2.8 4 ns

L

= 30 pF, VT = VCC/2 4.5 6.5 ns

L

= 30 pF, VT = VCC/2 4 6.5 ns

L

MIN

to T

, unless otherwise noted.

MAX

= 1.65 V to 3.6 V, GND = 0 V
= 3.0 V to 3.6 V 1.35 V
= 2.3 V to 2.7 V 1.35 V
= 1.65 V to 1.95 V 0.65 × VCC V
= 3.0 V to 3.6 V 0.8 V
= 2.3 V to 2.7 V 0.7 V
= 1.65 V to 1.95 V 0.35 × VCC V

= 3.0 V to 3.6 V 2.4 V

CC1

= 2.3 V to 2.7 V 2.0 V

CC1

= 1.65 V to 1.95 V VCC − 0.45 V

CC1

= 2.3 V to 2.7 V 2.0 V

CC1

= 1.65 V to 1.95 V VCC – 0.45 V

CC1

= 3.0 V to 3.6 V 2.4 V

CC1

= 3.0 V to 3.6 V 0.40 V

CC1

= 2.3 V to 2.7 V 0.40 V

CC1

= 1.65 V to 1.95 V 0.45 V

CC1

= 2.3 V to 2.7 V 0.40 V

CC1

= 1.65 V to 1.95 V 0.45 V

CC1

= 3.0 V to 3.6 V 0.40 V

CC1

= 1.65 V to 3.6 V, GND = 0 V

= 3.0 V to 3.6 V 2.4 V

CC2

= 2.3 V to 2.7 V 2.0 V

CC2

= 1.65 V to 1.95 V VCC − 0.45 V

CC2

= 2.3 V to 2.7 V 2.0 V

CC2

= 1.65 V to 1.95 V VCC – 0.45 V

CC2

= 3.0 V to 3.6 V 2.4 V

CC2

= 3.0 V to 3.6 V 0.40 V

CC2

= 2.3 V to 2.7 V 0.40 V

CC2

= 1.65 V to 1.95 V 0.45 V

CC2

= 2.3 V to 2.7 V 0.40 V

CC2

= 1.65 V to 1.95 V 0.45 V

CC2

= 3.0 V to 3.6 V 0.40 V

CC2

Rev. A | Page 3 of 16

ADG3233

Parameter1 Symbol Test Conditions/Comments Min Typ2 Max Unit

VCC = V

VCC = V

Input Leakage Current II 0 ≤ VIN ≤ 3.6 V ±1 μA
Output Leakage Current IO 0 ≤ VIN ≤ 3.6 V ±1 μA

POWER REQUIREMENTS

Power Supply Voltages V
V
Quiescent Power Supply Current I
I
Increase in ICC per Input ΔI

1

Temperature range is as follows: B Version: −40°C to +85°C.

2

All typical values are at VCC = V

3

VIL and VIH levels are specified with respect to V

V

CC2

4

Guaranteed by design, not subject to production test.

5

See the Test Waveforms section.

= V

CC1

= 2.5 V ± 0.2 V

CC2

Propagation Delay, tPD

t

, t

CL = 30 pF, VT = VCC/2 4.5 6.2 ns

PHL

A1 → Y1 Normal Mode

A2 → Y2 Normal Mode

A1 → Y2 Bypass Mode

ENABLE Time EN → Y1

DISABLE Time EN → Y1

ENABLE Time EN → Y2

DISABLE Time EN → Y2

= V

CC1

= 1.8 V ± 0.15 V

CC2

PLH

t

, t

CL = 30 pF, VT = VCC/2 4.5 6.2 ns

PHL

PLH

t

, t

CL = 30 pF, VT = VCC/2 4.5 6.5 ns

PHL

PLH

tEN C

t

C

DIS

tEN C

t

C

DIS

= 30 pF, VT = VCC/2 5 7.2 ns

L

= 30 pF, VT = VCC/2 3.2 4.7 ns

L

= 30 pF, VT = VCC/2 5 7.7 ns

L

= 30 pF, VT = VCC/2 4.8 7.2 ns

L

Propagation Delay, tPD

t

, t

CL = 30 pF, VT = VCC/2 6.7 10 ns

PHL

A1 → Y1 Normal Mode

A2 → Y2 Normal Mode

A1 → Y2 Bypass Mode

ENABLE Time EN → Y1

DISABLE Time EN → Y1

ENABLE Time EN → Y2

DISABLE Time EN → Y2

.

= V

, TA = 25°C, unless otherwise stated.

CC1

CC2

PLH

t

, t

CL = 30 pF, VT = VCC/2 6.5 10 ns

PHL

PLH

, t

CL = 30 pF, VT = VCC/2 6.5 10.25 ns

t

PHL

PLH

tEN C

t

C

DIS

tEN C

t

C

DIS

1.65 3.6 V

CC1

1.65 3.6 V

CC2

Digital inputs = 0 V or VCC 2 μA

CC1

Digital inputs = 0 V or VCC 2 μA

CC2

CC1

, VOH, and VOL levels for Y1 are specified with respect to V

CC1

= 30 pF, VT = VCC/2 7 10.5 ns

L

= 30 pF, VT = VCC/2 4.4 6.5 ns

L

= 30 pF, VT = VCC/2 7 12 ns

L

= 30 pF, VT = VCC/2 6.5 10.5 ns

L

= 3.6 V, one input at 3.0 V; others at

V

CC

or GND

V

CC

, and VOH, and VOL levels are specified for Y2 with respect to

CC1

0.75 μA

Rev. A | Page 4 of 16

ADG3233

V

V

V

TEST WAVEFORMS

DIS

CC1

V

T

0V

V

OH

V

T

V

OL

03297-032

CC1

V

T

0V

V

OH

V

T

V

OL

03297-033

CC1

V

T

0V

V

CC1

0V

V

CC1

0V

V

OLH

V

T

V

OL

03297-034

INPUT

t

PHL

OUTPUT

t

PLH

Figure 2. Propagation Delay

EN

t

EN

t

DIS

Y1

(A1 AT GND)

V

T

Figure 3. Y1 Enable and Disable Times

EN

t

EN

t

A1

A2

V

Y2

Figure 4. Y2 Enable and Disable Times

T

Rev. A | Page 5 of 16