ANALOG DEVICES ADG3123 Service Manual

8-Channel CMOS Logic to High Voltage

V

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FEATURES

2.3 V to 5.5 V input voltage range
Output voltage levels (V

DDA

and V
Low output voltage levels: down to −24.4 V
High output voltage levels: up to +35 V

Rise/fall time: 12 ns/19.5 ns typical
Propagation delay: 80 ns typical
Operating frequency: 100 kHz typical
Ultralow quiescent current: 65 μA typical
20-lead, Pb-free, TSSOP package

APPLICATIONS

Low voltage to high voltage translation
TFT-LCD panels
Piezoelectric motor drivers

GENERAL DESCRIPTION

to VSS ≤ 35 V)

DDB

Level Translator

ADG3123

FUNCTIONAL BLOCK DIAGRAM

DDA

GND

A1
A2
A3
A4
A5
A6

A7

A8

CHANNELS

CHANNELS

6

2

V

DDB

Figure 1.

ADG3123

Y1
Y2
Y3
Y4
Y5
Y6

V

SS

Y7

Y8

05655-001

The ADG3123 is an 8-channel, noninverting CMOS to high

2

voltage level translator. Fabricated on an enhanced LC

MOS
process, the device is capable of operating at high supply
voltages while maintaining ultralow power consumption.

The internal architecture of the device ensures compatibility
w

ith logic circuits running from supply voltages within the 2.3 V to

5.5 V range. The voltages applied to Pin V

set the logic levels available at the outputs on the Y side

Pin V

SS

of the device. Pin V

and Pin V

DDA

set the high output level

DDB

DDA

, Pin V

DDB,

and

for Pin Y1 to Pin Y6 and for Pin Y7 to Pin Y8, respectively. The
V

pin sets the low output level for all channels. The ADG3123

SS

can provide output voltages levels down to −10 V for a low
input level and up to +30 V for a high input logic level. For
proper operation, V
V

and the voltage between the Pin V

DDA

must always be greater than or equal to

DDB

and Pin VSS should

DDB

not exceed 35 V.

The low output impedance of the channels guarantees fast rise

nd fall times even for significant capacitive loads. This feature,

a
combined with low propagation delay and low power consump­tion, makes the ADG3123 an ideal driver for TFT-LCD panel
applications.

The ADG3123 is guaranteed to operate over the −40°C to

emperature range and is available in a compact, 20-lead

+85°C t
TSSOP, Pb-free package.

PRODUCT HIGHLIGHTS

1. Compatible with a wide range of CMOS logic levels.

igh output voltage levels.

2. H

3. F

ast rise and fall times coupled with low propagation delay.

4. Ult

5. C

ralow power consumption.

ompact, 20-lead TSSOP, Pb-free package.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADG3123

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TABLE OF CONTENTS

Features.............................................................................................. 1

Typical Performance Characteristics..............................................6

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

REVISION HISTORY

5/06—Rev. 0 to Rev. A

Changes to Features, General Description, and
P

roduct Highlights ........................................................................... 1

Changes to Specifications................................................................ 3

Changes to Figure 4 through Figure 9 ........................................... 6

Changes to Figure 14 and Figure 15............................................... 7

Changes to Theory of Operations section and

ower Supplies section................................................................... 10

P

9/05—Revision 0: Initial Version

Terminology.......................................................................................9

Theory of Operation ...................................................................... 10

Input Driving Requirements..................................................... 10

Output Load Requirements ...................................................... 10

Power Supplies............................................................................ 10

Applications..................................................................................... 11

Outline Dimensions....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. A | Page 2 of 12

ADG3123

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SPECIFICATIONS

V

= V

DDA

= 27 V, VSS = −7 V, GND = 0 V, unless otherwise noted.

DDB

Table 1.

Parameter Symbol Min Typ2Max Unit Conditions

DIGITAL INPUTS (Pin A1 to Pin A8) VAX = 0 V to 5.5 V

Input High Voltage VIH 1.7 V
Input Low Voltage VIL 0.8 V
Leakage Current IIL ±0.03 ±1 µA
Capacitance

ANALOG INPUTS (Pin V

Input Voltage Range V

3

)

DDA

CI 1 pF

0 V

DDA

DIGITAL OUTPUTS (Pin Y1 to Pin Y8) V

Output High Voltage (Pin Y1 to Pin Y6) VOH V
Output High Voltage (Pin Y7 to Pin Y8) VOH V

DDA

DDB

Output Low Voltage VOL V
Output Impedance R0 30 Ω V

SWITCHING CHARACTERISTICS

3

See Figure 2

Propagation Delay

Low to High Transition t
High to Low Transition t

76 125 ns

PLH

80 125 ns

PHL

Rise Time tR 12 20 ns
Fall Time tF 19.5 32 ns
Maximum Operating Frequency F

0

50 100 kHz 100 pF load, all channels, see Figure 2

POWER REQUIREMENTS

Quiescent Power Supply Current I

Power Supply Voltages

V

to VSS

DDB

V

to GND

DDB

VSS to GND

1

Temperature range for B version is −40°C to +85°C.

2

Typical values are specified at 25°C.

3

Guaranteed by design; not subject to production testing.

0.03 1 A VAX = 0 V or 5.5 V, no load, V

DDA

I

65 150 A

DDB

ISS

V
VSS

DDB

10.8

10.8

−24.2

1

V

DDB

= V

DDA

V

DDA

= 25 V to 30 V, V

DDB

and V

DDB

− 1 V IOH = −10 mA

− 1 V IOH = −10 mA
+ 1 V IOL = +10 mA

SS

= V

= +27 V, VSS = −7 V

DDB

to VSS ≤ 35 V
to VSS ≤ 35 V

0.03 1 A

35 V
35 V
0 V

V
V

DDA

DDB

DDB

to VSS ≤ 35V

= −5 V to −7 V,

SS

≤ V

DDB

DDA

DDA

++

10µF 10µF0.1µF 0.1µF

V

DDAVDDB

SIGNAL

SOURCE

R

50Ω

Z0 = 50Ω

S

V

SS

10µF 0.1µF

50Ω

V

R

ADG3123

IN

A

X

T

V

SS

+

GND

V

OUT

Y

X

100pF

Figure 2. Switching Characteristics Test Circuit

Rev. A | Page 3 of 12

DDB

50%

90%
50%
10%

V

IN

t

V

OUT

PHL

t

F

t

PLH

t

R

05655-002

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

V
V
V
VSS to GND +0.3 V to −32 V
Digital Inputs

Load Current Per Device

Operating Temperature Range

Storage Temperature Range −65°C to +125°C
Junction Temperature 150°C
Thermal Impedance, θJA 78°C/W3
Reflow Soldering (Pb-Free)

1

Overvoltage at Pin A1 to Pin A8 is clamped by internal diodes. Limit the

current to the maximum ratings given.

2

Pulsed at 100 kHz; 10% duty cycle maximum with the load shown in

Figure 2.

3

Guaranteed when the device is soldered on a 4-layer board.

to VSS 44 V

DDA/VDDB

to GND −0.3 V to +32 V

DDB

to GND −0.3 V to V

DDA

1

Average 15 mA at 25°C
8 mA at 85°C
Peak Current2 150 mA at 25°C
80 mA at 85°C

Industrial (B Version) −40°C to +85°C

Peak Temperature 260 (+0/−5)°C
Time at Peak Temperature 10 seconds to 40 seconds

VSS − 0.3 V to V
20 mA, whichever occurs first

DDB

+ 0.3 V or

DDB

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating can be applied at any

time.

one

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 4 of 12