8-Channel CMOS Logic to High Voltage
V
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FEATURES
2.3 V to 5.5 V input voltage range
Output voltage levels (V
DDA
and V
Low output voltage levels: down to −24.4 V
High output voltage levels: up to +35 V
Rise/fall time: 12 ns/19.5 ns typical
Propagation delay: 80 ns typical
Operating frequency: 100 kHz typical
Ultralow quiescent current: 65 μA typical
20-lead, Pb-free, TSSOP package
APPLICATIONS
Low voltage to high voltage translation
TFT-LCD panels
Piezoelectric motor drivers
GENERAL DESCRIPTION
to VSS ≤ 35 V)
DDB
Level Translator
ADG3123
FUNCTIONAL BLOCK DIAGRAM
DDA
GND
A1
A2
A3
A4
A5
A6
A7
A8
CHANNELS
CHANNELS
6
2
V
DDB
Figure 1.
ADG3123
Y1
Y2
Y3
Y4
Y5
Y6
V
SS
Y7
Y8
05655-001
The ADG3123 is an 8-channel, noninverting CMOS to high
2
voltage level translator. Fabricated on an enhanced LC
MOS
process, the device is capable of operating at high supply
voltages while maintaining ultralow power consumption.
The internal architecture of the device ensures compatibility
w
ith logic circuits running from supply voltages within the 2.3 V to
5.5 V range. The voltages applied to Pin V
set the logic levels available at the outputs on the Y side
Pin V
SS
of the device. Pin V
and Pin V
DDA
set the high output level
DDB
DDA
, Pin V
DDB,
and
for Pin Y1 to Pin Y6 and for Pin Y7 to Pin Y8, respectively. The
V
pin sets the low output level for all channels. The ADG3123
SS
can provide output voltages levels down to −10 V for a low
input level and up to +30 V for a high input logic level. For
proper operation, V
V
and the voltage between the Pin V
DDA
must always be greater than or equal to
DDB
and Pin VSS should
DDB
not exceed 35 V.
The low output impedance of the channels guarantees fast rise
nd fall times even for significant capacitive loads. This feature,
a
combined with low propagation delay and low power consumption, makes the ADG3123 an ideal driver for TFT-LCD panel
applications.
The ADG3123 is guaranteed to operate over the −40°C to
emperature range and is available in a compact, 20-lead
+85°C t
TSSOP, Pb-free package.
PRODUCT HIGHLIGHTS
1. Compatible with a wide range of CMOS logic levels.
igh output voltage levels.
2. H
3. F
ast rise and fall times coupled with low propagation delay.
4. Ult
5. C
ralow power consumption.
ompact, 20-lead TSSOP, Pb-free package.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
ADG3123
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TABLE OF CONTENTS
Features.............................................................................................. 1
Typical Performance Characteristics..............................................6
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
REVISION HISTORY
5/06—Rev. 0 to Rev. A
Changes to Features, General Description, and
P
roduct Highlights ........................................................................... 1
Changes to Specifications................................................................ 3
Changes to Figure 4 through Figure 9 ........................................... 6
Changes to Figure 14 and Figure 15............................................... 7
Changes to Theory of Operations section and
ower Supplies section................................................................... 10
P
9/05—Revision 0: Initial Version
Terminology.......................................................................................9
Theory of Operation ...................................................................... 10
Input Driving Requirements..................................................... 10
Output Load Requirements ...................................................... 10
Power Supplies............................................................................ 10
Applications..................................................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. A | Page 2 of 12
ADG3123
V
V
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SPECIFICATIONS
V
= V
DDA
= 27 V, VSS = −7 V, GND = 0 V, unless otherwise noted.
DDB
Table 1.
Parameter Symbol Min Typ2Max Unit Conditions
DIGITAL INPUTS (Pin A1 to Pin A8) VAX = 0 V to 5.5 V
Input High Voltage VIH 1.7 V
Input Low Voltage VIL 0.8 V
Leakage Current IIL ±0.03 ±1 µA
Capacitance
ANALOG INPUTS (Pin V
Input Voltage Range V
3
)
DDA
CI 1 pF
0 V
DDA
DIGITAL OUTPUTS (Pin Y1 to Pin Y8) V
Output High Voltage (Pin Y1 to Pin Y6) VOH V
Output High Voltage (Pin Y7 to Pin Y8) VOH V
DDA
DDB
Output Low Voltage VOL V
Output Impedance R0 30 Ω V
SWITCHING CHARACTERISTICS
3
See Figure 2
Propagation Delay
Low to High Transition t
High to Low Transition t
76 125 ns
PLH
80 125 ns
PHL
Rise Time tR 12 20 ns
Fall Time tF 19.5 32 ns
Maximum Operating Frequency F
0
50 100 kHz 100 pF load, all channels, see Figure 2
POWER REQUIREMENTS
Quiescent Power Supply Current I
Power Supply Voltages
V
to VSS
DDB
V
to GND
DDB
VSS to GND
1
Temperature range for B version is −40°C to +85°C.
2
Typical values are specified at 25°C.
3
Guaranteed by design; not subject to production testing.
0.03 1 A VAX = 0 V or 5.5 V, no load, V
DDA
I
65 150 A
DDB
ISS
V
VSS
DDB
10.8
10.8
−24.2
1
V
DDB
= V
DDA
V
DDA
= 25 V to 30 V, V
DDB
and V
DDB
− 1 V IOH = −10 mA
− 1 V IOH = −10 mA
+ 1 V IOL = +10 mA
SS
= V
= +27 V, VSS = −7 V
DDB
to VSS ≤ 35 V
to VSS ≤ 35 V
0.03 1 A
35 V
35 V
0 V
V
V
DDA
DDB
DDB
to VSS ≤ 35V
= −5 V to −7 V,
SS
≤ V
DDB
DDA
DDA
++
10µF 10µF0.1µF 0.1µF
V
DDAVDDB
SIGNAL
SOURCE
R
50Ω
Z0 = 50Ω
S
V
SS
10µF 0.1µF
50Ω
V
R
ADG3123
IN
A
X
T
V
SS
+
GND
V
OUT
Y
X
100pF
Figure 2. Switching Characteristics Test Circuit
Rev. A | Page 3 of 12
DDB
50%
90%
50%
10%
V
IN
t
V
OUT
PHL
t
F
t
PLH
t
R
05655-002
ADG3123
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
V
V
V
VSS to GND +0.3 V to −32 V
Digital Inputs
Load Current Per Device
Operating Temperature Range
Storage Temperature Range −65°C to +125°C
Junction Temperature 150°C
Thermal Impedance, θJA 78°C/W3
Reflow Soldering (Pb-Free)
1
Overvoltage at Pin A1 to Pin A8 is clamped by internal diodes. Limit the
current to the maximum ratings given.
2
Pulsed at 100 kHz; 10% duty cycle maximum with the load shown in
Figure 2.
3
Guaranteed when the device is soldered on a 4-layer board.
to VSS 44 V
DDA/VDDB
to GND −0.3 V to +32 V
DDB
to GND −0.3 V to V
DDA
1
Average 15 mA at 25°C
8 mA at 85°C
Peak Current2 150 mA at 25°C
80 mA at 85°C
Industrial (B Version) −40°C to +85°C
Peak Temperature 260 (+0/−5)°C
Time at Peak Temperature 10 seconds to 40 seconds
VSS − 0.3 V to V
20 mA, whichever occurs first
DDB
+ 0.3 V or
DDB
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
time.
one
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 4 of 12
ADG3123
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
A1
A2
A3
A4
A5
A6
A7
A8
V
SS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 GND Ground Reference (0 V).
2 to 9 A1 to A8 Level Translator CMOS Inputs.
10 V
11 V
12 to 19 Y8 to Y1
20 V
Most Negative Power Supply. Use the VSS pin to generate the output low level for Output Y1 to Output Y8.
SS
Positive Power Supply. Use the V
DDB
Level Translator High Voltage Outputs.
Analog Input. Use the V
DDA
pin to generate the output high level for Output Y1 to Output Y6 (V
DDA
1
2
3
4
ADG3123
5
TOP VIEW
(Not to Scale)
6
7
8
9
10
pin to generate the output high level for Output Y7 and Output Y8.
DDB
20
V
DDA
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
V
DDB
05655-003
DDA
≤ V
DDB
).
Rev. A | Page 5 of 12
ADG3123
–
–
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TYPICAL PERFORMANCE CHARACTERISTICS
4.1
TA = 25°C
= –7V
V
SS
3.9
R
= 5kΩ
L
C
= 100pF
L
DUTY CYCLE = 50%
3.7
1 CHANNEL
V
= V
3.5
DDA
DDB
= 27V
6.5
TA = 25°C
= –7V
V
SS
6.0
R
= 5kΩ
L
FREQUENCY = 20kHz
DUTY CYCLE = 50%
5.5
1 CHANNEL
5.0
(mA)
3.3
DDB
I
3.1
2.9
2.7
2.5
10
3.9
TA = 25°C
V
R
3.7
C
DUTY CYCLE = 50%
3.5
1 CHANNEL
3.3
(mA)
DDA
3.1
I
2.9
2.7
2.5
10
V
= V
DDA
20 30 40 50 60 70 80 90
FREQUENCY ( kHz)
Figure 4. Supply Current (I
= –7V
SS
= 5kΩ
L
= 100pF
L
V
DDA
V
DDA
20 30 40 50 60 70 80 90
FREQUENCY ( kHz)
Figure 5. Supply Current (I
= 25V
DDB
) vs. Frequency
DDB
= V
= 27V
DDB
= V
= 25V
DDB
) vs. Frequency
DDA
100
100
(mA)
4.5
DDB
I
4.0
3.5
3.0
2.5
0.1
05655-004
V
= V
DDA
DDB
CAPACITIVE LOAD ( nF)
Figure 7. Supply Current (I
4.1
TA = 25°C
= –7V
V
SS
3.9
R
= 5kΩ
L
FREQUENCY = 20kHz
DUTY CYCLE = 50%
3.7
1 CHANNEL
3.5
(mA)
3.3
DDA
I
3.1
2.9
2.7
2.5
0.1
05655-005
V
= V
DDA
DDB
CAPACITIVE LOAD ( nF)
Figure 8. Supply Current (I
V
= V
DDA
= 25V
) vs. Capacitive Load
DDB
V
= V
DDA
= 25V
) vs. Capacitive Load
DDA
DDB
DDB
= 27V
= 27V
4.64.13.63.12.62.11.61.10.6
05655-007
4.64.13.63.12.62. 11.61.10.6
05655-008
0.5
VSS = –5V
–0.7
–0.9
–1.1
(mA)
SS
I
–1.3
–1.5
–1.7
10
VSS = –7V
20 30 40 50 60 70 80 90
FREQUENCY ( kHz)
Figure 6. Supply Current (I
TA = 25°C
V
DDA
R
= 5kΩ
L
= 100pF
C
L
DUTY CYCLE = 50%
1 CHANNEL
) vs. Frequency
SS
= V
DDB
= 27V
100
05655-006
0.5
–1.5
–2.5
–3.5
(mA)
SS
I
–4.5
–5.5
–6.5
0.1
Figure 9. Supply Current (I
TA = 25°C
V
DDA
R
L
FREQUENCY = 20kHz
DUTY CYCL E = 50%
1 CHANNEL
CAPACITIVE LOAD ( nF)
) vs. Capacitive Load
SS
= V
= 5kΩ
= 27V
DDB
VSS = –5V
VSS = –7V
4.64.13.63.12.62. 11.61.10.6
05655-009
Rev. A | Page 6 of 12
ADG3123
www.BDTIC.com/ADI
300
TA = 25°C
V
= V
DDA
V
= –7V
SS
250
R
= 5kΩ
L
FREQUENCY = 20kHz
DUTY CYCLE = 50%
200
1 CHANNEL
DDB
= 27V
TA = 25°C
V
= V
DDA
270
V
= –7V
SS
R
= 5kΩ
L
FREQUENCY = 20kHz
DUTY CYCLE = 50%
1 CHANNEL
220
DDB
= 27V
150
RISE TIM E (ns)
100
50
0
0.10
500
TA = 25°C
V
DDA
450
V
SS
R
= 5kΩ
L
400
FREQUENCY = 20kHz
DUTY CYCLE = 50%
350
1 CHANNEL
300
250
200
FALL TIME (ns)
150
100
50
0
0.10
TA = 25°C
180
V
DDA
V
SS
R
= 5kΩ
L
160
FREQUENCY = 20kHz
DUTY CYCLE = 50%
1 CHANNEL
140
(ns)
120
PLH
t
100
0.60 1.10 1.60 2.10 2.60 3.10 3.60 4.10
CAPACITIVE LOAD ( nF)
Figure 10. Rise Time vs. Capacitive Load
= V
= 27V
DDB
= –7V
0.60 1.10 1.60 2.10 2.60 3.10 3.60 4.10
CAPACITIVE LOAD ( nF)
Figure 11. Fall Time vs. Ca
= V
= 27V
DDB
= –7V
pacitive Load
(ns)
PLH
170
t
120
70
0.10
0.60 1.10 1.60 2.10 2.60 3.10 3.60 4.10
05655-010
Figure 13. Propagation Delay (t
10
1
FREQUENCY (MHz)
0.1
0.01 0.1 1 10
05655-011
Figure 14. Maximum Operating Fre
CAPACITIVE LOAD ( nF)
) vs. Capacitive Load
PHL
CAPACITIVE L OAD (nF)
quency vs. Capacitive Load
V
= V
DDA
DDB
V
= –7V
SS
T
= 250°C
A
1 CHANNEL
= 27V
05655-013
05655-014
(One Channel)
1000
100
10
FREQUENCY (kHz)
V
= V
DDA
DDB
V
= –7V
SS
T
= 25°C
A
8 CHANNELS
= 27V
80
60
0.10
0.60 1.10 1.60 2.10 2.60 3.10 3.60 4.10
CAPACITIVE LOAD ( nF)
Figure 12. Propagation Delay (t
) vs. Capacitive Load
PLH
05655-012
Rev. A | Page 7 of 12
1
0.01 0.1 1 10
Figure 15. Maximum Operating Fre
CAPACITIVE LOAD (nF)
quency vs. Capacitive Load
(Eight Channels)
05655-015
ADG3123
www.BDTIC.com/ADI
–6.4
T
A
V
DDA
V
SS
1 CHANNEL
V
AX
–6.6
= 25°C
= V
= –7V
= 0V
DDB
= 27V
27.0
26.9
TA = 25°C
V
= V
DDA
DDB
V
= –7V
SS
1 CHANNEL
V
= 5.5V
AX
= 27V
(V)
OL
V
–6.8
–7.0
0
Figure 16. Output Voltage (V
510
LOAD CURRENT (mA)
) vs. Load Current
OL
15
05655-014
(V)
26.8
OH
V
26.7
26.6
–15 0
Figure 17. Output Voltage (V
–10 –5
LOAD CURRENT (mA)
) vs. Load Current
OH
05655-015
Rev. A | Page 8 of 12
ADG3123
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TERMINOLOGY
V
IH
Logic input high voltage at Pin A1 to Pin A8.
V
IL
Logic input low voltage at Pin A1 to Pin A8.
I
IL
Leakage current at Pin A1 to Pin A8.
C
I
Capacitance measured at Pin A1 to Pin A8.
V
OH
Logic output high voltage at Pin Y1 to Pin Y8.
V
OL
Logic output low voltage at Pin Y1 to Pin Y8.
Ro
Output impedance.
t
PLH
Propagation delay through the part measured between the input
nal applied to any one channel and its corresponding output
sig
for a low-to-high transition (see
t
PHL
Figure 2).
Propagation delay through the part measured between the input
signal applied to any one channel and its corresponding output
for a high-to-low transition (see
Figure 2).
t
F
Fall time of the output signal at the Pin Y1 to Pin Y8
(see Figure 2).
F
O
Frequency of the signal applied to the A1 to A8 input pins.
V
DDA
Input voltage used to generate the high logic levels for Y1 to Y6
s.
output
V
DDB
Positive power supply voltage. Also used to generate the high
ic levels for Y7 to Y8 outputs.
log
V
SS
Negative power supply voltage. It is used to generate the low
ic level for Y1 to Y8 outputs.
log
GND
Ground (0 V) reference.
I
DDA
Supply current at the V
I
DDB
Supply current at the V
I
SS
Supply current at the V
DDA
DDB
pin.
SS
pin.
pin.
t
R
Rise time of the output signal at Pin Y1 to Pin Y8 (see Figure 2).
Rev. A | Page 9 of 12
ADG3123
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THEORY OF OPERATION
The ADG3123 is an 8-channel, noninverting CMOS to high
voltage level translator. Fabricated on an enhanced LC
process, the device is capable of operating at high supply
voltages while maintaining ultralow power consumption.
2
MOS
Capacitive Loads
where:
OCHANNEL
DDXL
SS
|)| ( )(
VV CFAI +××=
The device requires a dual-supply voltage, V
and VSS, which
DDB
sets the low logic levels for all outputs and the high logic levels
for the Y7 and Y8 outputs. The V
The voltage applied to the V
DDA
pin acts as an analog input.
DDA
pin sets the output high logic
level for the Y1 to Y6 outputs.
The device translates the CMOS logic levels applied to the A1 to
8 inputs into high voltage bipolar levels available on the Y side
A
of the device at Pin Y1 to Pin Y8.
To ensure proper operation, V
or equal to V
Pin V
should not exceed 35 V.
SS
and the voltage between the Pin V
DDA
must always be greater than
DDB
and
DDB
INPUT DRIVING REQUIREMENTS
The ADG3123 design ensures low input capacitance and
leakage current thereby reducing the loading of the circuit that
drives the input pins (Pin A1 to Pin A8) to a minimum. Its
input threshold levels are compliant with JEDEC standards for
drivers operated from supply voltages between 2.3 V and 5.5 V.
It is recommended that the inputs of any unused channel be
tied to a stable logic level (low or high).
OUTPUT LOAD REQUIREMENTS
The low output impedance of the ADG3123 allows each
channel to drive both resistive and capacitive loads. The
maximum load current is limited by the current carrying
capability of any given channel. If more channels are used, the
maximum load current per channel is reduced accordingly.
Note that the sum of the load currents on all channels should
never exceed the absolute maximum ratings specifications.
The average load current on each channel, I
determined using the formulas shown in the Capacitive Loads
an
d the Resistive Loads sections.
CHANNEL
, can be
F
is the frequency of the signal applied to the channel in Hz.
O
C
is the load capacitance in farads.
L
VSS is the voltage applied to the V
V
is V
DDX
for Y1 to Y6 outputs, and V
DDA
SS
pin.
for Y7 to Y8
DDB
outputs.
Resistive Loads
VDVD
×−+×
CHANNEL
AI
)(
DDX
=
)1(
SS
R
L
where:
D is the duty cycle of the input signal. D is defined as the ratio
between the high state duration of the signal and its period.
R
is the load resistor in Ω.
L
V
is the voltage applied to the VSS pin.
SS
V
is V
DDX
for Y1 to Y6 outputs, and V
DDA
for Y7 to Y8
DDB
outputs.
POWER SUPPLIES
The ADG3123 operates from a dual-supply voltage. As good
design practice for all CMOS devices dictates, power up the
ADG3123 first (V
inputs (A1 to A8 and V
ADG3123, the voltage applied to the V
greater than or equal to V
Pin V
and Pin VSS should not exceed 35 V.
DDB
To ensure optimum performance, use
all power supply pins. Furthermore, good engineering and
layout practice suggests placing these capacitors as close as
possible to the package supply pins.
and VSS) before applying the signals to its
DDB
). To ensure correct operation of the
DDA
pin must always be
DDB
and the voltage between the
DDA
decoupling capacitors on
Rev. A | Page 10 of 12
ADG3123
V
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APPLICATIONS
The high voltage operation coupled with high current driving
capability and the wide range of CMOS levels accepted by the
ADG3123, make the device ideal for LCD-TFT panel applications. In this type of application, the controllers that generate
the timing signals required to control the pixel scanning process
inside the panel are usually low voltage CMOS devices.
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
V
DD
CONTROLL ER
= +2.3V TO +5.5V
DD
TIMING
Most LCD-TFT panels operate at high supply voltages; therefore,
the timing signals generated by the controller require level
translation to drive the panel. Figure 18 shows a typical applica-
on circuit where the ADG3123 translates eight timing signals
ti
provided by the timing controller into high voltage logic levels
required to drive the panel.
+
10µF
0.1µF
ADG3123
1
GND
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
V
SS
10µF 10µF
20
V
DDA
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
V
DDB
LCD-TFT
PANE L
++
DC TO DC
CONVERTER
–5V TO –10V
+25V TO +30V
+25V TO +30V
0.1µF 0.1µF
NOTE: |V
| + |VSS| ≤ 35V and V
DDB
DDA
≤ V
DDB
5655-016
Figure 18. Typical Application Circuit
Rev. A | Page 11 of 12
ADG3123
Y
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OUTLINE DIMENSIONS
6.60
6.50
6.40
20
1
PIN 1
0.65
BSC
0.15
0.05
COPLANARIT
0.30
0.19
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 19. 20-Lead Thin Shrink S
1.20 MAX
11
4.50
4.40
4.30
10
SEATING
PLANE
6.40 BSC
0.20
0.09
mall Outline Package [TSSOP]
8°
0°
0.75
0.60
0.45
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG3123BRUZ
ADG3123BRUZ-REEL
ADG3123BRUZ-REEL7
1
Z = Pb-free part.
1
1
−40°C to +85°C 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20
−40°C to +85°C 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20
1
−40°C to +85°C 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20
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D05655-0-5/06(A)
Rev. A | Page 12 of 12
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