0.2 Ω on resistance flatness
±3.3 V to ±8 V dual-supply operation
3.3 V to 16 V single-supply operation
No V
supply required
L
3 V logic-compatible inputs
Rail-to-rail operation
Continuous current per channel
LFCSP package: 280 mA
TSSOP package: 175 mA
16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Communication systems
Medical systems
Audio signal routing
Video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
GENERAL DESCRIPTION
The ADG1611/ADG1612/ADG1613 contain four independent
single-pole/single-throw (SPST) switches. The ADG1611 and
ADG1612 differ only in that the digital control logic is inverted.
The ADG1611 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1612 switches. The ADG1613 has two switches with
digital control logic similar to that of the ADG1611; the logic is
inverted on the other two switches. Each switch conducts equally
well in both directions when on and has an input signal range that
extends to the supplies. In the off condition, signal levels up to
the supplies are blocked.
The ADG1613 exhibits break-before-make switching action for use
in multiplexer applications. Inherent in the design is the low charge
injection for minimum transients when switching the digital inputs.
The ultralow on resistance of these switches make them ideal
solutions for data acquisition and gain switching applications
where low on resistance and distortion is critical. The on resistance
profile is very flat over the full analog input range, ensuring
excellent linearity and low distortion when switching audio signals.
The CMOS construction ensures ultralow power dissipation, making
them ideally suited for portable and battery-powered instruments.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
−40°C to
Parameter 25°C
+85°C
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 1 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 24
1.2 1.4 1.6 Ω max VDD = ±4.5 V, VSS = ±4.5 V
On Resistance Match Between Channels (∆RON) 0.04 Ω typ VS = ±4.5 V, IS = −10 mA
0.08 0.09 0.1 Ω max
On Resistance Flatness (R
) 0.2 Ω typ VS = ±4.5 V, IS = −10 mA
FLAT(ON)
0.25 0.29 0.34 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.1 nA typ
±0.3 ±1 ±6 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ
±0.3 ±1 ±6 nA max
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = ±4.5 V; see Figure 26
±0.4 ±1.5 ±10 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
+0.005 ±0.1 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
tON 165 ns typ RL = 300 Ω, CL = 35 pF
212 253 285 ns max VS = 2.5 V; see Figure 31
t
105 ns typ RL = 300 Ω, CL = 35 pF
OFF
137 150 159 ns max VS = 2.5 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 25 ns typ RL = 300 Ω, CL = 35 pF
20 ns min VS1 = VS2 = 2.5 V; see Figure 32
Charge Injection 140 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation 70 dB typ
Channel-to-Channel Crosstalk 110 dB typ
Total Harmonic Distortion + Noise (THD + N) 0.007 % typ
−3 dB Bandwidth 42 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29
CS (Off) 63 pF typ VS = 0 V, f = 1 MHz
CD (Off) 63 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 154 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 μA max
VDD/VSS ±3.3/±8 V min/max
1
Guaranteed by design, not subject to production test.
Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.95 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 24
1.1 1.25 1.45 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between Channels (∆RON) 0.03 Ω typ VS = 0 V to 10 V, IS = −10 mA
0.06 0.7 0.08 Ω max
On Resistance Flatness (R
) 0.2 Ω typ VS = 0 V to 10 V, IS = −10 mA
FLAT(ON)
0.23 0.27 0.32 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V, see Figure 25
±0.3 ±1 ±6 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V see Figure 25
±0.3 ±1 ±6 nA max
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 10 V; see Figure 26
±0.4 ±1.5 ±10 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.001 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
tON 125 ns typ RL = 300 Ω, CL = 35 pF
156 190 215 ns max VS = 8 V; see Figure 31
t
75 ns typ RL = 300 Ω, CL = 35 pF
OFF
87 93 99 ns max VS = 8 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 Ω, CL = 35 pF
30 ns min VS1 = VS2 = 8 V; see Figure 32
Charge Injection 170 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise 0.012 % typ
−3 dB Bandwidth 38 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29
CS (Off) 60 pF typ VS = 6 V, f = 1 MHz
CD (Off) 60 pF typ VS = 6 V, f = 1 MHz
CD, CS (On) 154 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 12 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
IDD 320 μA typ Digital inputs = 5 V
480 μA max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.
Analog Signal Range 0 V to VDD V
On Resistance (RON) 1.7 Ω typ VS = 0 V to 4.5 V, IS = −10 mA; see Figure 24
2.15 2.4 2.7 Ω max VDD = 4.5 V, VSS = 0 V
On Resistance Match Between Channels (∆RON) 0.05 Ω typ VS = 0 V to 4.5 V, IS = −10 mA
0.09 0.12 0.15 Ω max
On Resistance Flatness (R
) 0.4 Ω typ VS = 0 V to 4.5 V, IS = −10 mA
FLAT(ON)
0.53 0.55 0.6 Ω max
LEAKAGE CURRENTS VDD = 5.5 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25
±0.3 ±1 ±6 nA max
Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25
±0.3 ±1 ±6 nA max
Channel On Leakage, ID, IS (On) ±0.15 nA typ VS = VD = 1 V or 4.5 V; see Figure 26
±0.4 ±1.5 ±10 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.001 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
tON 215 ns typ RL = 300 Ω, CL = 35 pF
279 334 376 ns max VS = 2.5 V; see Figure 31
t
115 ns typ RL = 300 Ω, CL = 35 pF
OFF
150 169 180 ns max VS = 2.5 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 Ω, CL = 35 pF
25 ns min VS1 = VS2 = 2.5 V; see Figure 32
Charge Injection 80 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation 70 dB typ
Channel-to-Channel Crosstalk 110 dB typ
Total Harmonic Distortion + Noise 0.093 % typ
−3 dB Bandwidth 42 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29
CS (Off) 72 pF typ VS = 2.5 V, f = 1 MHz
CD (Off) 72 pF typ VS = 2.5 V, f = 1 MHz
CD, CS (On) 160 pF typ VS = 2.5 V, f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.
−40°C to
125°C Unit Test Conditions/Comments
or VDD
GND
= 50 Ω, CL = 5 pF, f = 100 kHz;
R
L
see Figure 27
= 50 Ω, CL = 5 pF, f = 100 kHz;
R
L
see Figure 28
= 110 Ω, f = 20 Hz to 20 kHz,
R
L
V
= 3.5 V p-p; see Figure 30
S
Rev. A | Page 5 of 16
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