Datasheet ADG1611 Datasheet (ANALOG DEVICES)

1 Ω Typical On Resistance, ±5 V, +12 V,

+5 V, and +3.3 V Quad SPST Switches

FEATURES

1 Ω typical on resistance

0.2 Ω on resistance flatness ±3.3 V to ±8 V dual-supply operation

3.3 V to 16 V single-supply operation No V

supply required

L

3 V logic-compatible inputs Rail-to-rail operation Continuous current per channel

LFCSP package: 280 mA TSSOP package: 175 mA

16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP

APPLICATIONS

Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements

GENERAL DESCRIPTION

The ADG1611/ADG1612/ADG1613 contain four independent single-pole/single-throw (SPST) switches. The ADG1611 and ADG1612 differ only in that the digital control logic is inverted. The ADG1611 switches are turned on with Logic 0 on the appropriate control input, while Logic 1 is required for the ADG1612 switches. The ADG1613 has two switches with digital control logic similar to that of the ADG1611; the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.

The ADG1613 exhibits break-before-make switching action for use in multiplexer applications. Inherent in the design is the low charge injection for minimum transients when switching the digital inputs.

The ultralow on resistance of these switches make them ideal solutions for data acquisition and gain switching applications where low on resistance and distortion is critical. The on resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals.

The CMOS construction ensures ultralow power dissipation, making them ideally suited for portable and battery-powered instruments.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADG1611/ADG1612/ADG1613

FUNCTIONAL BLOCK DIAGRAMS

IN1

IN2

ADG1611

IN3

IN4

NOTES

1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.

NOTES

1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.

NOTES

1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.

Figure 1.

IN1

IN2

ADG1612

IN3

IN4

Figure 2.

IN1

IN2

ADG1613

IN3

IN4

Figure 3.

PRODUCT HIGHLIGHTS

1. 1.6 Ω maximum on resistance over temperature.

2. Minimum distortion: THD + N = 0.007%.

3. 3 V logic-compatible digital inputs: V

4. No V

5. Ultralow power dissipation: <16 nW.

6. 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP.

logic power supply required.

L

S1

D1

S2

D2

S3

D3

S4

D4

S1

D1

S2

D2

S3

D3

S4

D4

S1

D1

S2

D2

S3

D3

S4

D4

INH

07981-001

07981-033

07981-034

= 2.0 V, V

= 0.8 V.

INL

ADG1611/ADG1612/ADG1613

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to On Resistance (R Between Channels (ΔR (R

Changes to Figure 7 Caption ......................................................... 10

1/09—Revision 0: Initial Version

) Parameter, Table 4 ............................................................ 6

FLATON

ON

) Parameter, On Resistance Match

ON

) Parameter, and On Resistance Flatness

3.3 V Single Supply ........................................................................6

Continuous Current per Channel, S or D ..................................7

Absolute Maximum Ratings ............................................................8

ESD Caution...................................................................................8

Pin Configurations and Function Descriptions ............................9

Typical Performance Characteristics ........................................... 10

Test Circuits ..................................................................................... 13

Terminolog y .................................................................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

Rev. A | Page 2 of 16

ADG1611/ADG1612/ADG1613

SPECIFICATIONS

±5 V DUAL SUPPLY

VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range VDD to VSS V On Resistance (RON) 1 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 24

1.2 1.4 1.6 Ω max VDD = ±4.5 V, VSS = ±4.5 V On Resistance Match Between Channels (∆RON) 0.04 Ω typ VS = ±4.5 V, IS = −10 mA

0.08 0.09 0.1 Ω max

On Resistance Flatness (R

) 0.2 Ω typ VS = ±4.5 V, IS = −10 mA

FLAT(ON)

0.25 0.29 0.34 Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V

Source Off Leakage, IS (Off) ±0.1 nA typ

±0.3 ±1 ±6 nA max Drain Off Leakage, ID (Off) ±0.1 nA typ

±0.3 ±1 ±6 nA max

Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = ±4.5 V; see Figure 26 ±0.4 ±1.5 ±10 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

+0.005 ±0.1 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 5 pF typ DYNAMIC CHARACTERISTICS1

tON 165 ns typ RL = 300 Ω, CL = 35 pF

212 253 285 ns max VS = 2.5 V; see Figure 31

t

105 ns typ RL = 300 Ω, CL = 35 pF

OFF

137 150 159 ns max VS = 2.5 V; see Figure 31

Break-Before-Make Time Delay, tD (ADG1613 Only) 25 ns typ RL = 300 Ω, CL = 35 pF

20 ns min VS1 = VS2 = 2.5 V; see Figure 32 Charge Injection 140 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation 70 dB typ

Channel-to-Channel Crosstalk 110 dB typ

Total Harmonic Distortion + Noise (THD + N) 0.007 % typ

−3 dB Bandwidth 42 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (Off) 63 pF typ VS = 0 V, f = 1 MHz CD (Off) 63 pF typ VS = 0 V, f = 1 MHz CD, CS (On) 154 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max VDD/VSS ±3.3/±8 V min/max

1

Guaranteed by design, not subject to production test.

−40°C to +125°C Unit Test Conditions/Comments

V

= ±4.5 V, VD = ∓4.5 V; see Figure 25

S

V

= ±4.5 V, VD = ∓4.5 V; see Figure 25

S

or VDD

GND

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 27

= 50 Ω, CL = 5 pF, f = 1 MHz;

R

L

see Figure 28

= 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;

R

L

see Figure 30

Rev. A | Page 3 of 16

ADG1611/ADG1612/ADG1613

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance (RON) 0.95 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 24

1.1 1.25 1.45 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between Channels (∆RON) 0.03 Ω typ VS = 0 V to 10 V, IS = −10 mA

0.06 0.7 0.08 Ω max

On Resistance Flatness (R

) 0.2 Ω typ VS = 0 V to 10 V, IS = −10 mA

FLAT(ON)

0.23 0.27 0.32 Ω max

LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V, see Figure 25 ±0.3 ±1 ±6 nA max Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V see Figure 25 ±0.3 ±1 ±6 nA max

Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 10 V; see Figure 26 ±0.4 ±1.5 ±10 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 5 pF typ DYNAMIC CHARACTERISTICS1

tON 125 ns typ RL = 300 Ω, CL = 35 pF

156 190 215 ns max VS = 8 V; see Figure 31

t

75 ns typ RL = 300 Ω, CL = 35 pF

OFF

87 93 99 ns max VS = 8 V; see Figure 31

Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 Ω, CL = 35 pF

30 ns min VS1 = VS2 = 8 V; see Figure 32 Charge Injection 170 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27 Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 Total Harmonic Distortion + Noise 0.012 % typ

−3 dB Bandwidth 38 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (Off) 60 pF typ VS = 6 V, f = 1 MHz CD (Off) 60 pF typ VS = 6 V, f = 1 MHz CD, CS (On) 154 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 12 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 320 μA typ Digital inputs = 5 V 480 μA max VDD 3.3/16 V min/max

1

Guaranteed by design, not subject to production test.

−40°C to +125°C Unit Test Conditions/Comments

or VDD

GND

= 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;

R

L

see Figure 30

Rev. A | Page 4 of 16

ADG1611/ADG1612/ADG1613

5 V SINGLE SUPPLY

VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance (RON) 1.7 Ω typ VS = 0 V to 4.5 V, IS = −10 mA; see Figure 24

2.15 2.4 2.7 Ω max VDD = 4.5 V, VSS = 0 V On Resistance Match Between Channels (∆RON) 0.05 Ω typ VS = 0 V to 4.5 V, IS = −10 mA

0.09 0.12 0.15 Ω max

On Resistance Flatness (R

) 0.4 Ω typ VS = 0 V to 4.5 V, IS = −10 mA

FLAT(ON)

0.53 0.55 0.6 Ω max

LEAKAGE CURRENTS VDD = 5.5 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25 ±0.3 ±1 ±6 nA max Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25 ±0.3 ±1 ±6 nA max

Channel On Leakage, ID, IS (On) ±0.15 nA typ VS = VD = 1 V or 4.5 V; see Figure 26 ±0.4 ±1.5 ±10 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 5 pF typ DYNAMIC CHARACTERISTICS1

tON 215 ns typ RL = 300 Ω, CL = 35 pF

279 334 376 ns max VS = 2.5 V; see Figure 31

t

115 ns typ RL = 300 Ω, CL = 35 pF

OFF

150 169 180 ns max VS = 2.5 V; see Figure 31

Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 Ω, CL = 35 pF

25 ns min VS1 = VS2 = 2.5 V; see Figure 32 Charge Injection 80 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation 70 dB typ

Channel-to-Channel Crosstalk 110 dB typ

Total Harmonic Distortion + Noise 0.093 % typ

−3 dB Bandwidth 42 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (Off) 72 pF typ VS = 2.5 V, f = 1 MHz CD (Off) 72 pF typ VS = 2.5 V, f = 1 MHz CD, CS (On) 160 pF typ VS = 2.5 V, f = 1 MHz

POWER REQUIREMENTS VDD = 5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max VDD 3.3/16 V min/max

1

Guaranteed by design, not subject to production test.

−40°C to 125°C Unit Test Conditions/Comments

or VDD

GND

= 50 Ω, CL = 5 pF, f = 100 kHz;

R

L

see Figure 27

= 50 Ω, CL = 5 pF, f = 100 kHz;

R

L

see Figure 28

= 110 Ω, f = 20 Hz to 20 kHz,

R

L

V

= 3.5 V p-p; see Figure 30

S

Rev. A | Page 5 of 16

ADG1611/ADG1612/ADG1613

3.3 V SINGLE SUPPLY

VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 4.

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance (RON) 3.2 3.4 3.6 Ω typ

On Resistance Match Between Channels (∆RON) 0.06 0.07 0.08 Ω typ VS = 0 V to VDD, IS = −10 mA On Resistance Flatness (R

) 1.2 1.3 1.4 Ω typ VS = 0 V to VDD, IS = −10 mA

FLAT(ON)

LEAKAGE CURRENTS VDD = 3.6 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 25 ±0.3 ±1 ±6 nA max Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 25

±0.3 ±1 ±6 nA max

Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 0.6 V or 3 V; see Figure 26 ±0.4 ±1.5 ±10 nA max DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INH

±0.1 μA max

Digital Input Capacitance, CIN 3 pF typ DYNAMIC CHARACTERISTICS1

tON 350 ns typ RL = 300 Ω, CL = 35 pF

493 556 603 ns max VS = 1.5 V; see Figure 31

t

190 ns typ RL = 300 Ω, CL = 35 pF

OFF

263 286 300 ns max VS = 1.5 V; see Figure 31

Break-Before-Make Time Delay, tD (ADG1613 Only) 25 ns typ RL = 300 Ω, CL = 35 pF

18 ns min VS1 = VS2 = 1.5 V; see Figure 32 Charge Injection 50 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation 70 dB typ

Channel-to-Channel Crosstalk 110 dB typ

Total Harmonic Distortion + Noise 0.18 % typ

−3 dB Bandwidth 52 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29 CS (Off) 76 pF typ VS = 1.5 V, f = 1 MHz CD (Off) 76 pF typ VS = 1.5 V, f = 1 MHz CD, CS (On) 160 pF typ VS = 1.5 V, f = 1 MHz

POWER REQUIREMENTS VDD = 3.6 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 1.0 μA max VDD 3.3/16 V min/max

1

Guaranteed by design, not subject to production test.

−40°C to +125°C Unit Test Conditions/Comments

= 0 V to VDD, IS = −10 mA, VDD = 3.3 V,

V

S

= 0 V; see Figure 24

V

SS

or VDD

GND

= 50 Ω, CL = 5 pF, f = 100 kHz;

R

L

see Figure 27

= 50 Ω, CL = 5 pF, f = 100 kHz;

R

L

see Figure 28

= 110 Ω, f = 20 Hz to 20 kHz,

R

L

= 2 V p-p; see Figure 30

V

S

Rev. A | Page 6 of 16

ADG1611/ADG1612/ADG1613

CONTINUOUS CURRENT PER CHANNEL, S OR D

Table 5.

Parameter

CONTINUOUS CURRENT, S OR D

VDD = +5 V, VSS = −5 V

TSSOP (θJA = 150.4°C/W) 175 119 70 mA maximum LFCSP (θJA = 48.7°C/W) 280 175 95 mA maximum

VDD = 12 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) 206 135 84 mA maximum LFCSP (θJA = 48.7°C/W) 336 203 108 mA maximum

VDD = 5 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) 140 91 63 mA maximum LFCSP (θJA = 48.7°C/W) 220 140 84 mA maximum

VDD = 3.3 V, VSS = 0 V

TSSOP (θJA = 150.4°C/W) 140 98 70 mA maximum LFCSP (θJA = 48.7°C/W) 228 150 91 mA maximum

25°C 85°C 125°C

Unit

Rev. A | Page 7 of 16

ADG1611/ADG1612/ADG1613

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to VSS 18 V VDD to GND −0.3 V to +18 V VSS to GND +0.3 V to −18 V Analog Inputs1

Digital Inputs1

Peak Current, S or D

Continuous Current, S or D2 Data + 15% Operating Temperature Range

Industrial (Y Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP, θJA Thermal

Impedance (2-Layer Board)

16-Lead LFCSP, θJA Thermal

Impedance (4-Layer Board)

Reflow Soldering Peak

Temperature, Pb free

1

Overvoltages at IN, S, or D are clamped by internal diodes. Current should be

limited to the maximum ratings given.

2

See Table 5.

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first GND − 0.3 V to V

30 mA, whichever occurs first 630 mA (pulsed at 1 ms,

10% duty-cycle maximum)

150.4°C/W

48.7°C/W

260°C

+ 0.3 V or

DD

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 16

ADG1611/ADG1612/ADG1613

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

IN1

D1

IN2

D2

14

13

15

1S1

2V

3GND

4S4

16

PIN 1 INDICATOR

ADG1611/

ADG1612/

ADG1613

TOP VIEW

(Not to Scale)

7

5

6

D4

IN4

IN3

12 S2

11 V

DD

10 NC

9S3

8

D3

.

SS

07981-003

1

IN1

2

D1

3

S1

ADG1611/

ADG1612/

4

V

SS

ADG1613

5

S4

D4

TOP VIEW

(Not to Scale)

6

7

8

GND

IN4

NC = NO CONNECT

Figure 4. 16-Lead TSSOP Pin Configuration

16

IN2

15

D2

14

S2

13

V

DD

12

NC

11

S3

10

D3

9

IN3

07981-002

SS

NOTES

1. NC = NO CONNECT .

2. EXPOSED P AD TIED TO SUBSTRATE, V

Figure 5. 16-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

16-Lead TSSOP 16-Lead LFCSP

Mnemonic Description

1 15 IN1 Logic Control Input.

2 16 D1 Drain Terminal. This pin can be an input or output.

3 1 S1 Source Terminal. This pin can be an input or output.

4 2 VSS Most Negative Power Supply Potential.

5 3 GND Ground (0 V) Reference.

6 4 S4 Source Terminal. This pin can be an input or output.

7 5 D4 Drain Terminal. This pin can be an input or output.

8 6 IN4 Logic Control Input.

9 7 IN3 Logic Control Input.

10 8 D3 Drain Terminal. This pin can be an input or output.

11 9 S3 Source Terminal. This pin can be an input or output.

12 10 NC No Connection.

13 11 VDD Most Positive Power Supply Potential.

14 12 S2 Source Terminal. This pin can be an input or output.

15 13 D2 Drain Terminal. This pin can be an input or output.

16 14 IN2 Logic Control Input.

N/A 17 (EPAD) EP (EPAD) Exposed Pad. Tied to substrate, VSS.

Table 8. ADG1611/ADG1612 Truth Table

ADG1611 INx ADG1612 INx Switch Condition

0 1 On

1 0 Off

Table 9. ADG1613 Truth Table

Logic (INx) Switch 1, Switch 4 Switch 2, Switch 3

0 Off On

1 On Off

Rev. A | Page 9 of 16

ADG1611/ADG1612/ADG1613

TYPICAL PERFORMANCE CHARACTERISTICS

1.4

TA = 25°C

= +3.3V

V

DD

V

= –3.3V

1.2

1.0

0.8

ON RESISTANCE ()

0.6

SS

= +5V

V

DD

V

= –5V

SS

VDD = +8V V

= –8V

SS

1.4

1.2

1.0

0.8

ON RESISTANCE ()

0.6

TA = +125°C T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

VDD = 12V V

= 0V

SS

0.4

–8 –6 –4 –2 0 2 4 6 8

OR VD VOLTAGE (V)

V

S

Figure 6. On Resistance as a Function of VD (VS) for Dual Supply

3.5

TA = 25°C

3.0

2.5

2.0

1.5

ON RESISTANCE ()

1.0

0.5

0 2 4 6 8 10 12 14 16

Figure 7. On Resistance as a Function of V

VDD = 3.3V V

= 0V

SS

VDD = 5V V

= 0V

SS

V

OR VD VOLTAGE (V)

S

V

= 12V

DD

V

= 0V

SS

D

VDD = 16V V

(VS) for Single Supply

= 0V

SS

1.4

1.2

0.4

024681012

07981-013

Figure 9. On Resistance as a Function of V

VS OR VD VOLTAGE (V)

(VS) for Different Temperatures,

D

07981-010

12 V Single Supply

2.5

TA = +125°C

= +125°C

T

A

T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

2.0

1.5

ON RESISTANCE ()

1.0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

07981-014

VS OR VD VOLTAGE (V)

VDD = 5V V

= 0V

SS

07981-012

Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,

5 V Single Supply

4.0 VDD = 3.3V V

= 0V

SS

3.5

1.0

0.8

ON RESISTANCE ()

0.6

VDD = +5V V

= –5V

SS

0.4

–6–4–20246

V

OR VD VOLTAGE (V)

S

Figure 8. On Resistance as a Function of V

(VS) for Different Temperatures,

D

T

TA = +125°C

= +125°C

A

T

= +85°C

A

T

= +25°C

A

T

= –40°C

A

±5 V Dual Supply

07981-011

Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,

Rev. A | Page 10 of 16

3.0

T

= +125°C

2.5

ON RESISTANCE ()

2.0

1.5

0 0.5 1. 0 1. 5 2. 0 2. 5 3. 0 3. 5

A

T

= +85°C

A

T

= +25°C

A

TA = –40°C

VS OR VD VOLTAGE (V)

3.3 V Single Supply

07981-006

ADG1611/ADG1612/ADG1613

(

20

15

10

5

0

–5

LEAKAGE CURRENT (n A)

–10

–15

0 20406080100120

TEMPERATURE (°C)

ID, IS (ON) +, +

ID (OFF) –, +

IS (OFF) +, –

ID, IS (ON) –, – IS (OFF) –, +

ID (OFF) +, –

07981-03

Figure 12. Leakage Currents as a Function of Temperature, ±5 V Dual Supply

25

20

15

10

5

0

–5

LEAKAGE CURRENT (n A)

–10

–15

–20

0 20406080100120

TEMPERATURE (°C)

ID, IS (ON) +, +

ID (OFF) –, +

IS (OFF) +, –

ID, IS (ON) –, – IS (OFF) –, +

(OFF) +, –

I

D

7981-031

Figure 13. Leakage Currents as a Function of Temperature,

12 V Single Supply

20

15

ID, IS (OFF) +, +

10

ID, IS (OFF) –, –

5

LEAKAGE CURRENT (n A)

0

–5

0 20406080100120

TEMPERATURE (°C)

ID (OFF) –, +

IS (OFF) +, – IS (OFF) –, + ID (OFF) +, –

07981-019

Figure 14. Leakage Currents as a Function of Temperature,

5 V Single Supply

18

16

14

12

10

8

6

4

2

LEAKAGE CURRENT (n A)

0

–2

–4

0 20 40 60 80 100 120

TEMPERATURE (°C)

ID, IS (OFF) +, +

ID, IS (OFF) –, –

ID (OFF) –, +

IS (OFF) +, –

IS (OFF) –, +

(OFF) +, –

I

D

Figure 15. Leakage Currents as a Function of Temperature,

3.3 V Single Supply

600

500

400

300

µA)

200

DD

I

100

0

–100

024681012

IDD = +12V I

= 0V

SS

I

= +5V

DD

I

= –5V

SS

IDD = +3.3V I

= 0V

SS

Figure 16. I

I

= +5V

DD

I

= 0V

SS

LOGIC (V)

vs. Logic Level

DD

IDD PER CHANNEL T

= 25°C

A

300

VDD = +5V V

= –5V

SS

= 0V

VS (V)

SS

VDD = +5V V

= 0V

SS

V V

DD SS

= +12V

= 0V

250

200

150

100

CHARGE INJECTI ON (pC)

50

VDD = +3.3V

0

–6 –4 –2 0 2 4 6 8 10 12 14

V

Figure 17. Charge Injection vs. Source Voltage (V

07981-030

07981-005

07981-009

)

S

Rev. A | Page 11 of 216

ADG1611/ADG1612/ADG1613

–

A

500

450

400

350

300

250

TIME (ns)

200

150

100

50

t

(+5V)

OFF

t

(±5V)

OFF

t

(+5V)

ON

t

(+12V)

0

–60 –40 –20 0 20 40 60 80 100 120 140

OFF

Figure 18. t

TEMPERATURE (°C)

Times vs. Temperature

ON/tOFF

t

OFF

t

ON

(+3.3V)

t

(±5V)

OFF

t

(+12V)

ON

1-018 0798

0

–1

–2

–3

–4

INSERTION LOSS (dB)

–5

–6

100k 1M 10M 100M 1G10k1k

FREQUENCY (Hz)

TA = 25°C

= +5V

V

DD

= –5V

V

SS

07981-004

Figure 21. On Response vs. Frequency

TION (dB)

OFF ISOL

CROSSTALK (dB)

–100

–120

–140

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

–75

–80

–85

–20

–40

–60

–80

5

TA = 25°C V V

0

TA = 25°C V V

= +5V

DD

= –5V

SS

100k 1M 10M 100M 1G10k1k

FREQUENCY ( Hz)

Figure 19. Off Isolation vs. Frequency

= +5V

DD

= –5V

SS

100k 1M 10M 100M 1G10k1k

FREQUENCY ( Hz)

Figure 20. Crosstalk vs. Frequency

0

TA = 25°C

= +5V

V

DD

= –5V

V

SS

–20

–40

–60

ACPSRR (dB)

–80

–100

007

07981-

–120

FREQUENCY (Hz)

NO DECOUPLI NG CAPACITORS

DECOUPLING CAPACITORS

100k 1M 10M10k1k

07981-008

Figure 22. ACPSRR vs. Frequency

0.20

0.18

RL = 110

0.16

T

= 25°C

A

0.14

0.12

0.10

0.08

THD + N (%)

0.06

0.04

0.02

07981-017

VDD = +12V

= 5V p-p

V

S

0

VDD = +3.3V

= 2V

V

S

VDD = +5V

= 3.5V

V

S

15k 20k10k5k 25k

FREQUENCY ( Hz)

VDD = +5V

V

= –5V

SS

= 5V p-p

V

S

1-016 0798

Figure 23. THD + N vs. Frequency

Rev. A | Page 12 of 16

ADG1611/ADG1612/ADG1613

V

TEST CIRCUITS

DD

SS

0.1µF

V

SS

Sx

Dx

Figure 27. Off Isolation

L

50

OFF ISOLATION = 20 log

DD

0.1µF

V

DD

S1

S2

NETWO RK

ANALYZER

50

V

OUT

R

L

50

SS

0.1µF

V

SS

Dx

V

S

V

OUT

V

S

07981-026

R

L

50

Sx Dx

V

S

RON = V1/I

Figure 24. On Resistance

0.1µF

V

DD

I

S

V1

S

07981-020

INx

V

IN

GND

NETWORK

ANALYZER

V

OUT

R 50

IS (OFF) ID (OFF)

V

S

Sx Dx

A A

Figure 25. Off Leakage

Sx Dx

NC

NC = NO CONNECT

Figure 26. On Leakage

ID (ON)

A

V

D

S

V

D

7981-021

CHANNEL-TO-CHANNEL CROSSTAL K = 20 log

Figure 28. Channel-to-Channel Crosstalk

DD

SS

0.1µF

V

DD

INx

V

IN

07981-022

GND

0.1µF

V

SS

Sx

Dx

INSERTIO N LOSS = 20 log

Figure 29. Bandwidth

GND

V

OUT

V

S

NETWORK ANALYZER

50

R

L

50

V

WITH SWITCH

OUT

WITHOUT SWITCH

V

OUT

07981-027

V

S

V

OUT

7981-028

V

Rev. A | Page 13 of 16

ADG1611/ADG1612/ADG1613

V

0.1µF

INx

IN

V

DD

SS

0.1µF

R

L

110

AUDIO PRECISI ON

R

S

V

S

V p-p

V

OUT

07981-029

V

DD

SS

Sx

Dx

GND

Figure 30. THD + Noise

V

DD

SS

0.1µF

V

DD

Sx

S

INx

GND

0.1µF

ADG1612

V

OUT

IN

ADG1611

V

SS

V

C

L

35pF

OUT

Dx

R

L

300

50% 50%

90% 90%

t

ON

t

OFF

07981-023

Figure 31. Switching Times

V

DD

0.1µF

SS

0.1µF

V

IN

0V

50% 50%

V

DD

IN1, IN2

S1 D1

S2 D2

ADG1613

V

S1

V

S2

GND

SS

R

L

R

L

300

C

L

35pF

V

OUT2

300

C

L

35pF

V

OUT1

V

OUT1

OUT2

0V

90%

0V

90%

t

D

t

90%

D

90%

07981-024

Figure 32. Break-Before-Make Time Delay

DD

SS

V

DD

SS

C 1nF

V

OUT

L

R

S

V

S

INx

Sx

Dx

GND

V

IN

V

IN

V

OUT

ADG1612

ADG1611

Q

INJ

ON

= CL × V

OUT

V

OFF

OUT

07981-025

Figure 33. Charge Injection

Rev. A | Page 14 of 16

ADG1611/ADG1612/ADG1613

TERMINOLOGY

IDD

The positive supply current.

I

SS

The negative supply current.

V

(VS)

D

The analog voltage on Terminal D and Terminal S.

R

ON

The ohmic resistance between Terminal D and Terminal S.

R

FLAT(ON)

Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range.

I

(Off)

S

The source leakage current with the switch off.

I

(Off)

D

The drain leakage current with the switch off.

I

, IS (On)

D

The channel leakage current with the switch on.

V

INL

The maximum input voltage for Logic 0.

V

INH

The minimum input voltage for Logic 1.

I

(I

)

INL

INH

The input current of the digital input.

C

(Off)

S

The off switch source capacitance, which is measured with reference to ground.

C

(Off)

D

The off switch drain capacitance, which is measured with reference to ground.

C

, CS (On)

D

The on switch capacitance, which is measured with reference to ground.

C

IN

The digital input capacitance.

t

ON

The delay between applying the digital control input and the output switching on. See Figure 31.

t

OFF

The delay between applying the digital control input and the output switching off. See Figure 31.

Charge Injection

A measure of the glitch impulse transferred from the digital input to the analog output during switching. See Figure 33.

Off Isolation

A measure of unwanted signal coupling through an off switch. See Figure 27.

Crosstalk

A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. See Figure 28.

Bandwidth

The frequency at which the output is attenuated by 3 dB. See Figure 29.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

Total Harmonic Distortion + Noise (THD + N)

The ratio of the harmonic amplitude plus noise of the signal to the fundamental. See Figure 30.

AC Power Supply Rejection Ratio (ACPSRR)

The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.

Rev. A | Page 15 of 16

ADG1611/ADG1612/ADG1613

C

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65 BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]

4.00

BSC SQ

PIN 1

ATO R

INDI

TOP VIEW

12° MAX

1.00

0.85

0.80

SEATING

PLANE

0.30

0.23

0.18

COMPLIANTTOJEDEC STANDARDS MO-220-VGGC.

Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad (CP-16-13)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1611BRUZ1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1611BRUZ-REEL1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1611BRUZ-REEL71 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1611BCPZ-REEL1 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13 ADG1611BCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13 ADG1612BRUZ1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1612BRUZ-REEL1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1612BRUZ-REEL71 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1612BCPZ- REEL1 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13 ADG1612BCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13 ADG1613BRUZ1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1613BRUZ-REEL1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1613BRUZ-REEL71 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1613BCPZ-REEL1 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13 ADG1613BCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13

1

Z = RoHS Compliant Part.

9

6.40 BSC

81

1.20 MAX

0.30

0.19

0.10

SEATING PLANE

0.20

0.09

(RU-16)

Dimensions shown in millimeters

0.60 MAX

12

13

3.75

BSC SQ

0.80 MAX

0.65 TYP

0.20 REF

0.05 MAX

0.02 NOM

0.65 BSC

1.95 BCS

COPLANARIT Y

9

BOTTOM VIEW

0.08

EXPOSED

8

Dimensions shown in millimeters

8° 0°

0.50

0.40

0.30

16

PA D

4

5

FOR PROPER CO NNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DESCRI PTIONS SECTION O F THIS DATA SHEET.

P

N

I

D

N

I

1

2.65

2.50 SQ

2.35

0.25 MIN

0.75

0.60

0.45

1

R

O

C

I

A

T

031006-A

Rev. A | Page 16 of 16

Datasheet ADG1611 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

±5 V DUAL SUPPLY

12 V SINGLE SUPPLY

5 V SINGLE SUPPLY

3.3 V SINGLE SUPPLY

CONTINUOUS CURRENT PER CHANNEL, S OR D

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

TERMINOLOGY

OUTLINE DIMENSIONS

ORDERING GUIDE