0.2 Ω on resistance flatness
±3.3 V to ±8 V dual-supply operation
3.3 V to 16 V single-supply operation
No V
supply required
L
3 V logic-compatible inputs
Rail-to-rail operation
Continuous current per channel
LFCSP package: 504 mA
TSSOP package: 315 mA
14-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Communication systems
Medical systems
Audio signal routing
Video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
+12 V, +5 V, and +3.3 V, 4:1 Multiplexer
ADG1604
FUNCTIONAL BLOCK DIAGRAM
S1
S2
S3
S4
ADG1604
1 OF 4
DECODER
Figure 1.
D
ENA1A0
07982-001
GENERAL DESCRIPTION
The ADG1604 is a complementary metal-oxide semiconductor
(CMOS) analog multiplexer and switches one of four inputs to
a common output, D, as determined by the 3-bit binary address
lines, A0, A1, and EN. Logic 0 on the EN pin disables the device.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In
the off condition, signal levels up to the supplies are blocked.
All switches exhibit break-before-make switching action.
Inherent in the design is low charge injection for minimum
transients when switching the digital inputs.
The ultralow on resistance of these switches make them ideal
solutions for data acquisition and gain switching applications where
low on resistance and distortion is critical. The on resistance profile
is very flat over the full analog input range, ensuring excellent
linearity and low distortion when switching audio signals.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The CMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and batterypowered instruments.
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
−40°C to
Parameter 25°C
+85°C
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 1 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 22
1.2 1.4 1.6 Ω max VDD = ±4.5 V, VSS = ±4.5 V
On Resistance Match Between Channels (∆RON) 0.04 Ω typ VS = ±4.5 V, IS = −10 mA
0.08 0.09 0.1 Ω max
On Resistance Flatness (R
) 0.2 Ω typ VS = ±4.5 V, IS = −10 mA
FLAT(ON)
0.25 0.29 0.34 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.1 nA typ
±0.2 ±1 ±8 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ
±0.2 ±2 ±16 nA max
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = ±4.5 V; see Figure 24
±0.4 ±2 ±16 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.005 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 8 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
150 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
278 336 376 ns max VS = 2.5 V; see Figure 29
tON (EN) 116 ns typ RL = 300 Ω, CL = 35 pF
146 166 177 ns max VS = 2.5 V; see Figure 31
t
(EN) 186 ns typ RL = 300 Ω, CL = 35 pF
OFF
234 277 310 ns max VS = 2.5 V; see Figure 31
Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF
28.5 ns min VS1 = VS2 = 2.5 V; see Figure 30
Charge Injection 140 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation 70 dB typ
Channel-to-Channel Crosstalk 70 dB typ
Total Harmonic Distortion + Noise (THD + N) 0.007 % typ
−3 dB Bandwidth 15 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
CS (Off) 63 pF typ VS = 0 V, f = 1 MHz
CD (Off) 270 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 360 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 μA max
VDD/VSS ±3.3/±8 V min/max
1
Guaranteed by design, not subject to production test.
Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.95 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 22
1.1 1.25 1.45 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between Channels (∆RON) 0.03 Ω typ VS = 10 V, IS = −10 mA
0.06 0.07 0.08 Ω max
On Resistance Flatness (R
) 0.2 Ω typ VS = 0 V to 10 V, IS = −10 mA
FLAT(ON)
0.23 0.27 0.32 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23
±0.2 ±1 ±8 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23
±0.2 ±2 ±16 nA max
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 10 V; see Figure 24
±0.4 ±2 ±16 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.001 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 8 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
100 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
161 192 220 ns max VS = 8 V; see Figure 29
tON (EN) 80 ns typ RL = 300 Ω, CL = 35 pF
95 104 111 ns max VS = 8 V; see Figure 31
t
(EN) 144 ns typ RL = 300 Ω, CL = 35 pF
OFF
173 205 234 ns max VS = 8 V; see Figure 31
Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF
18 ns min VS1 = VS2 = 8 V; see Figure 30
Charge Injection 125 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation 70 dB typ
Channel-to-Channel Crosstalk 70 dB typ
Total Harmonic Distortion + Noise 0.013 % typ
−3 dB Bandwidth 19 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
CS (Off) 60 pF typ VS = 6 V, f = 1 MHz
CD (Off) 270 pF typ VS = 6 V, f = 1 MHz
CD, CS (On) 350 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 12 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
IDD 230 μA typ Digital inputs = 5 V
360 μA max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.
Analog Signal Range 0 V to VDD V
On Resistance (RON) 1.7 Ω typ VS = 0 V to 4.5 V, IS = −10 mA; see Figure 22
2.15 2.4 2.7 Ω max VDD = 4.5 V, VSS = 0 V
On Resistance Match Between Channels (∆RON) 0.05 Ω typ VS = 0 V to 4.5 V, IS = −10 mA
0.09 0.12 0.15 Ω max
On Resistance Flatness (R
) 0.4 Ω typ VS = 0 V to 4.5 V, IS = −10 mA
FLAT(ON)
0.53 0.55 0.6 Ω max
LEAKAGE CURRENTS VDD = 5.5 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 23
±0.2 ±1 ±8 nA max
Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 23
±0.2 ±2 ±16 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 1 V or 4.5 V; see Figure 24
±0.4 ±2 ±16 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.001 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 8 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
175 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
283 337 380 ns max VS = 2.5 V; see Figure 29
tON (EN) 135 ns typ RL = 300 Ω, CL = 35 pF
174 194 212 ns max VS = 2.5 V; see Figure 31
t
(EN) 228 ns typ RL = 300 Ω, CL = 35 pF
OFF
288 342 385 ns max VS = 2.5 V; see Figure 31
Break-Before-Make Time Delay, tD 30 ns typ RL = 300 Ω, CL = 35 pF
21 ns min VS1 = VS2 = 2.5 V; see Figure 30
Charge Injection 70 pC typ VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation 70 dB typ
Channel-to-Channel Crosstalk 70 dB typ
Total Harmonic Distortion + Noise 0.09 % typ
−3 dB Bandwidth 16 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
CS (Off) 70 pF typ VS = 2.5 V, f = 1 MHz
CD (Off) 300 pF typ VS = 2.5 V, f = 1 MHz
CD, CS (On) 400 pF typ VS = 2.5 V, f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1 μA max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.
Analog Signal Range 0 V to VDD V
On Resistance (RON) 3.2 3.4 3.6 Ω typ
On Resistance Match Between Channels (∆RON) 0.06 0.07 0.08 Ω typ VS = 0 V to VDD, IS = −10 mA
On Resistance Flatness (R
) 1.2 1.3 1.4 Ω typ VS = 0 V to VDD, IS = −10 mA
FLAT(ON)
LEAKAGE CURRENTS VDD = 3.6 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 23
±0.25 ±1 ±8 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 23
±0.25 ±2 ±16 nA max
Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = 0.6 V or 3 V; see Figure 24
±0.6 ±2 ±16 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
INL
2.0 V min
INH
0.8 V max
INL
or I
0.001 μA typ VIN = V
INH
±0.1 μA max
Digital Input Capacitance, CIN 8 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, t
280 ns typ RL = 300 Ω, CL = 35 pF
TRANSITION
460 526 575 ns max VS = 1.5 V; see Figure 29
tON (EN) 227 ns typ RL = 300 Ω, CL = 35 pF
308 332 346 ns max VS = 1.5 V; see Figure 31
t
(EN) 357 ns typ RL = 300 Ω, CL = 35 pF
OFF
480 549 601 ns max VS = 1.5 V; see Figure 31
Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF
20 ns min VS1 = VS2 = 1.5 V; see Figure 30
Charge Injection 60 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32
Off Isolation 70 dB typ
Channel-to-Channel Crosstalk 70 dB typ
Total Harmonic Distortion + Noise 0.15 % typ
−3 dB Bandwidth 15 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
CS (Off) 76 pF typ VS = 1.5 V, f = 1 MHz
CD (Off) 316 pF typ VS = 1.5 V, f = 1 MHz
CD, CS (On) 420 pF typ VS = 1.5 V, f = 1 MHz
POWER REQUIREMENTS VDD = 3.6 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 1.0 μA max
VDD 3.3/16 V min/max
1
Guaranteed by design, not subject to production test.
−40°C to
+125°C Unit Test Conditions/Comments
= 0 V to VDD, IS = −10 mA, VDD = 3.3 V,
V
S
= 0 V; see Figure 22
V
SS
or VDD
GND
= 50 Ω, CL = 5 pF, f = 100 kHz;
R
L
see Figure 25
= 50 Ω, CL = 5 pF, f = 100 kHz;
R
L
see Figure 27
= 110 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p;
R
L
see Figure 28
Rev. A | Page 6 of 20
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