Analog Devices ADG 1436 Service Manual

www.DataSheet4U.com

2

Ω

±15 V/12 V/±5 V iCMOS™ Dual SPDT Switch

Max On Resistance,

Preliminary Technical Data

FEATURES

2Ω Max On Resistance

0.5Ω Max On Resistance Flatness

200mA continious current
33 V supply range
Fully specified at +12 V, ±15 V, ±5 V

supply required

No V

L

3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP packages

APPLICATIONS

Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay Replacement

ADG1436

FUNCTIONAL BLOCK DIAGRAM

ADG1436

S1A

S1B

IN1

IN2

S2A

S2B

SWITCHES SHOWN FOR A LOGIC "1" INPUT

Figure 1.TSSOP package

ADG1436

S1A

D1

S1B

LOGIC

D1

D2

S2A

D2

S2B

GENERAL DESCRIPTION

The ADG1436 is a monolithic CMOS device containing two
independently selectable SPDT switches. An EN input on the
LFCSP package is used to enable or disable the device. When
disabled, all channels are switched off. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. Both switches exhibit
break-before-make switching action for use in multiplexer
applications.

It is designed on an iCMOS process. iCMOS (industrial­CMOS) is a modular manufacturing process combining high
voltage CMOS (complementary metal-oxide semiconductor)
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no previous generation of high voltage parts
has been able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high supply

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

IN1 IN2

SWITCHES SHOWN FOR A “1” INPUT LOGIC

Figure 2.LFCSP package

EN

voltages, while providing increased performance, dramatically
lower power consumption, and reduced package size.

The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. iCMOS construction ensures ultralow
power dissipation, making the part ideally suited for portable
and battery-powered instruments.

PRODUCT HIGHLIGHTS

1. 2Ω Max On Resistance over temperature.

2. Minimum distortion

3. 3 V logic-compatible digital inputs: V

4. No V

logic power supply required.

L

5. Ultralow power dissipation: <0.03 µW.

6. 16-lead TSSOP and 16-lead 4 mm × 4mm LFCSP

packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2007 Analog Devices, Inc. All rights reserved.

= 2.0 V, VIL = 0.8 V.

IH

ADG1436 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Pin Configurations and Function Descriptions............................8

Dual Supply................................................................................... 3

Single Supply................................................................................. 4

Absolute Maximum Ratings............................................................ 7

Truth Table For Switches ............................................................. 8

ESD Caution.................................................................................. 7

REVISION HISTORY

Terminology.......................................................................................9

Typical Performance Characteristics........................................... 10

Test Circuits..................................................................................... 13

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. PrC | Page 2 of 17

Preliminary Technical Data ADG1436

SPECIFICATIONS

DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

25°C -40°C to

+85°C

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance (RON) 1.5 Ω typ VS = ±10 V, IS = −10 mA; Figure 23
2 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match between

Channels (∆R

)

ON

0.1 Ω typ V

0.5 Ω max

On Resistance Flatness (R

) 0.1 Ω typ VS = −5 V/0 V/+5 V; IS = −10 mA

FLAT(ON)

0.5 Ω max
LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.01 nA typ VS = ±10 V, Vs = ±10 V; Figure 23
±0.5 ±2.5 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = ±10 V, Vs = ±10 V;; Figure 23
±0.5 ±2.5 ±5 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = ±10 V; Figure 23
±1 ±2.5 ±5 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.005 µA typ VIN = V

INH

±0.5 µA max
Digital Input Capacitance, CIN 5 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

120 ns typ RL = 300 Ω, CL = 35 pF

TRANS

150 200 ns max VS = +10 V; Figure 25

tON (EN) 85 ns typ RL = 300 Ω, CL = 35 pF

105 130 140 ns max VS = 10 V; see Figure 25

t

(EN) 105 ns typ RL = 300 Ω, CL = 35 pF

OFF

125 150 170 ns max VS = 10 V; see Figure 25

Break-before-Make Time Delay, tD 15 40 ns typ RL = 300 Ω, CL = 35 pF

1 ns min VS1 = VS2 = +10 V; Figure 27

Charge Injection 50 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 29
Off Isolation 50 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 30
Channel-to-Channel Crosstalk 60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 31
Total Harmonic Distortion + Noise 0.015 % typ RL = 110Ω, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 100 MHz typ RL = 50 Ω, CL = 5 pF; Figure 32
CS (Off) 35 pF typ f = 1 MHz; VS = 0 V
CD (Off) 35 pF typ f = 1 MHz; VS = 0 V
CD, CS (On) 70 pF typ f = 1 MHz; VS = 0 V

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 µA typ Digital Inputs = 0 V or VDD
1 µA max
IDD 150 µA typ Digital Input = 5 V
300 µA max
ISS 0.001 µA typ Digital Inputs = 0 V, 5V or VDD

1.0 µA max

-40°C to
+125°C

= ±10 V, IS = −10 mA

S

V

= +16.5 V, VSS = −16.5 V

DD

or V

INL

INH

Rev. PrC| Page 3 of 17

ADG1436 Preliminary Technical Data

25°C -40°C to

+85°C

VDD/VSS ±4.5/±16.5 V min/max Gnd = 0V

1

Guaranteed by design, not subject to production test.

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

25°C -40°C to

+85°C

ANALOG SWITCH

Analog Signal Range
On Resistance (RON) 2.5

On Resistance Match between

Channels (∆R

)

ON

0.5

On Resistance Flatness (R

) 0.1

FLAT(ON)

0.5
LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.01

Drain Off Leakage, ID (Off) ±0.01

Channel On Leakage, ID, IS (On) ±0.04

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

Input Current, I

INH

INL

or I

INL

0.001

INH

Digital Input Capacitance, CIN 5

DYNAMIC CHARACTERISTICS1

Transition Time, t

120 ns typ RL = 300 Ω, CL = 35 pF

TRANS

150 200 ns max VS = 8 V; Figure 25

tON (EN) 85 ns typ

t

(EN) 105 ns typ

OFF

125 150 170 ns max

Break-before-Make Time Delay, tD 15

Charge Injection 30
Off Isolation 50
Channel-to-Channel Crosstalk 60
Total Harmonic Distortion + Noise 0.015 % typ RL = 110Ω, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 100
CS (Off) 35 pF typ f = 1 MHz; VS = 6V
CD (Off) 35 pF typ f = 1 MHz; VS = 6V
CD, CS (On) 70 pF typ f = 1 MHz; VS = 6 V

0 V to VDD V

3 4

0.1

±0.5 ±2.5 ±5 nA max

±0.5 ±2.5 ±5 nA max

±1 ±2.5 ±5 nA max

±0.5 µA max

105 130 140 ns max

1 ns min V

-40°C to
+125°C

-40°C to
+125°C

Ω typ VS = +10 V, IS = −10 mA; Figure 23
Ω max
Ω typ V

Ω max

= +10 V, IS = −10 mA

S

Ω typ VS = +3 V/+6 V/+9 V, IS = −10 mA

VDD = 12 V

nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 24

nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 24

nA typ VS = VD = 1 V or 10 V, Figure 25

2.0 V min

0.8 V max
µA typ VIN = V

pF typ

RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 25

ns typ RL = 300 Ω, CL = 35 pF

S1

pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 29
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 30;
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 31

MHz typ RL = 50 Ω, CL = 5 pF; Figure 32

or V

INH

INL

= VS2 = 8 V; Figure 27

Rev. PrC | Page 4 of 17

Preliminary Technical Data ADG1436

25°C -40°C to

+85°C

POWER REQUIREMENTS

IDD 0.001

IDD 150

VDD 5/16.5 V

1.0 µA max

300 µA max

1

Guaranteed by design, not subject to production test.

DUAL SUPPLY

VDD = 5 V ± 10%, VSS = -5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 3.

−40°C to

25°C
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 3
4
On Resistance Match Between

Channels (∆R

)

ON

0.1

On Resistance Flatness (R

) 0.1

FLAT(ON)

LEAKAGE CURRENTS
Source Off Leakage, IS (Off) ±0.01 nA typ

±0.5 ±2.5 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ

±0.5 ±2.5 ±5 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = ±4.5V; See figure x
±1 ±5 ±5 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 µA typ VIN = V

INH

±0.5 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1

Transition Time, t

150 ns typ RL = 300 Ω, CL = 35 pF

TRANS

190 265 ns max VS = 3 V; Figure 25

tON (EN) 85 ns typ

105 130 140 ns max

t

(EN) 105 ns typ

OFF

125 150 170 ns max

Break-Before-Make Time Delay, tD 50 ns typ
10 ns min VS1 = VS2 = 3 V; See figure 25
Charge Injection 50 pC typ
Off Isolation 50 dB typ

Channel-to-Channel Crosstalk 60 dB typ

+85°C

-40°C to
+125°C

−40°C to
+125°C

VDD = 13.2 V

µA typ Digital Inputs = 0 V or VDD

µA typ Digital Inputs = 5 V

min/max

Gnd = 0V, Vss = 0V

Unit Test Conditions/Comments

Ω typ VS = ±3.3V, IS = −10 mA; See figure x
Ω max VDD = +4.5 V, VSS = −4.5 V
Ω typ V

Ω max

= ±3.3 V , IS = −10 mA

S

Ω typ VS = −3 V/0 V/+3 V; IS = −10 mA

VDD = +5.5 V, VSS = −5.5 V

VS = ±4.5 V, VD = ∓4.5 V; See figure x

VS = ±4.5 V, VD = ∓4.5 V; See figure x

or V

INH

INL

RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25

= 300 Ω, CL = 35 pF

R

L

VS = 0 V, RS = 0 Ω, CL = 1 nF; See figure x
RL = 50 Ω, CL = 5 pF, f = 1 MHz; See figure

x
R

= 50 Ω, CL = 5 pF, f = 1 MHz; See figure

L

x

Rev. PrC| Page 5 of 17

ADG1436 Preliminary Technical Data

−40°C to

25°C

Total Harmonic Distortion + Noise 0.002 % typ RL = 110Ω, 5 V pp, f = 20 Hz to 20 kHz

−3 dB Bandwidth
CS (Off) 35 pF typ Vs = 0V, f = 1 MHz
CD (Off) 35 pF typ Vs = 0V, f = 1 MHz
CD, CS (On) 150 pF typ Vs = 0V, f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V , Vss = -5.5V
IDD 0.001 µA typ Digital inputs = 0 V or VDD

1.0 µA max
ISS 0.001 µA typ Digital inputs = 0 V or VDD

1.0 µA max

VDD/VSS ±4.5/±16.5 V

200 MHz typ

+85°C

−40°C to
+125°C Unit Test Conditions/Comments

RL = 50 Ω, CL = 5 pF; See figure x

Gnd = 0V

min/max

1

Guaranteed by design, not subject to production test.

Rev. PrC | Page 6 of 17

Preliminary Technical Data ADG1436

ABSOLUTE MAXIMUM RATINGS

T

= 25°C, unless otherwise noted.

A

Table 4.

Parameter Ratings

VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs1 V
Digital Inputs1

Peak Current, S or D

Continuous Current, S or D 200 mA
Operating Temperature Range

Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP, θJA Thermal

Impedance
16-Lead LFCSP, θJA Thermal

Impedance
Reflow Soldering Peak

Temperature, Pb free

− 0.3 V to VDD + 0.3 V

SS

GND − 0.3 V to V
30 mA, whichever occurs first

300 mA (pulsed at 1 ms, 10%
duty cycle max)

150.4°C/W

72.7°C/W

260°C

+ 0.3 V or

DD

1

Over voltages at IN, S, or D are clamped by internal diodes. Current should

be limited to the maximum ratings given.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrC| Page 7 of 17

ADG1436 Preliminary Technical Data

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

S1A

IN1

NC NC

141516

ADG1436

TOP V IEW

(Not to Scale)

6

7

5

IN2

13

EN

12

Vdd

11

10

S2B

D2

9

8

S2ANC

1

IN1

S1A

2

3

D1

ADG1236

4

S1B

TOP VIEW

5

V

SS

(Not to Scale)

6

GND

7

NC

8

NC

NC = NO CONNECT

16

NC

NC

15

14

NC

13

V

DD

12

S2B

11

D2

10

S2A

9

IN2

04776-0-002

Figure 3.TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

TSSOP LFCSP

Mnemonic Function

1 15 IN1 Logic Control Input.
2 16 S1A Source Terminal. Can be an input or output.
3 1 D1 Drain Terminal. Can be an input or output.
4 2 S1B Source Terminal. Can be an input or output.
5 3 VSS Most Negative Power Supply Potential.
6 4 GND Ground (0 V) Reference.
7, 8, 14–16 5,7,13,14 NC No Connect.
9 6 IN2 Logic Control Input.
10 8 S2A Source Terminal. Can be an input or output.
11 9 D2 Drain Terminal. Can be an input or output.
12 10 S2B Source Terminal. Can be an input or output.
13 11 VDD Most Positive Power Supply Potential.

- 12 EN

Active High Digital Input. When low, the device is disabled and all switches are off. When
high, INx logic inputs determine the on switches.

D1

1

S1B

2

3

Vss

Gnd

4

NC

EXPOSED PAD TIEDTO SUBSTRATE, Vss
NC = NO CONNECT

Figure 4. LFCSP Pin Configuration

TRUTH TABLE FOR SWITCHES

Table 6. ADG1436 TSSOP Truth Table

INx Switch xA Switch xB

0 Off On
1 On Off

Table 7. ADG1436 LFCSPTruth Table

EN INx SxA SxB
0 X Off Off
1 0 Off On
1 1 On Off

Rev. PrC | Page 8 of 17

Preliminary Technical Data ADG1436

TERMINOLOGY

IDD

The positive supply current.

I

SS

The negative supply current.

(VS)

V

D

The analog voltage on Terminals D and S.

R

ON

The ohmic resistance between D and S.

R

FLAT(ON)

Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.

I

(Off)

S

The source leakage current with the switch off.

I

(Off)

D

The drain leakage current with the switch off.

I

, IS (On)

D

The channel leakage current with the switch on.

V

INL

The maximum input voltage for Logic 0.

V

INH

The minimum input voltage for Logic 1.

(I

INL

INH

)

I

The input current of the digital input.

C

(Off)

S

The off switch source capacitance, measured with reference to
ground.

C

(Off)

D

The off switch drain capacitance, measured with reference to
ground.

, CS (On)

C

D

The on switch capacitance, measured with reference to ground.

C

IN

The digital input capacitance.

t

TRANS

The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

Rev. PrC| Page 9 of 17

ADG1436 Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. On Resistance as a Function of V

Figure 6, On Resistance as a Function of V

(VS) for Dual Supply

D

(VS) for Single l Supply

D

Figure 8. On Resistance as a Function of V

(VS) for Different Temperatures,

D

Single Supply

Figure 9. Leakage Current as a Function of V

D

(VS)

Figure 7. On Resistance as a Function of V

Dual Supply

(VS) for Different Temperatures,

D

Rev. PrC | Page 10 of 17

Figure 10. Leakage Currents as a Function of V

D

(VS)

Preliminary Technical Data ADG1436

Figure 11. Leakage Current as a Function of V

(VS)

D

Figure 12. Leakage Currents as a Function of Temperature

Figure 13. I

vs. Log ic Level

DD

Figure 15. Charge Injection vs. Source Voltage

Figure 16. t

Times vs. Temperature

TRANSITION

Figure 14. Logic Threshold Voltage vs Supply Voltage

Rev. PrC| Page 11 of 17

Figure 17. Off Isolation vs. Frequency

ADG1436 Preliminary Technical Data

Figure 18. Cross talk vs. Frequen cy

Figure 19. On Response vs. Frequency

Figure 20. THD + N vs. Frequency

Figure 211. Capacitance vs. Source Voltage for Dual Supply

Figure 222. Capacitance vs. Source Voltage for Single Supply

Rev. PrC | Page 12 of 17

Preliminary Technical Data ADG1436

V

VDDV

TEST CIRCUITS

V

SD

I

V

S

DS

04776-0-020

IS (OFF) ID (OFF)

SD

A A

S

V

D

04776-0-021

SD

NC

NC = NO CONNECT

Figure 23. On Resistance Figure 24. Off Resistance Figure 25. On Leakage

V

V

DD

SS

0.1µF0.1µF

V

DDVSS

SB

V

S

SA

IN

V

IN

GND

D

R

L

50Ω

C

L

35pF

V

OUT

Figure 26. Switching Times

V

IN

V

IN

V

OUT

t

50%

50%

90%

ON

50%

50%

90%

t

OFF

04776-0-023

ID (ON)

A

V

D

04776-0-022

V

V

DD

SS

0.1µF0.1µF

V

IN

80%

V

OUT

GND

t

BBM

04776-0-024

SS

SA

SB

D

OUTPUT

100Ω

V

S

35pF

t

BBM

V

DDVSS

INx

EN

V

IN

50Ω

3V

ENABLE
DRIVE (V

0V

OUTPUT

V

V

DD

SS

SB

V

S

SA

IN

V

IN

GND

D

R

L

50Ω

C

L

35pF

V

OUT

Figure 27. Break-before-Make Time Delay

)

IN

t

(EN)

ON

50% 50%

0.9V

O

0.9V

t

(EN)

OFF

O

04861-025

Figure 28. . Enable Delay, t

ON

(EN), t

OFF

(EN)

Rev. PrC| Page 13 of 17

ADG1436 Preliminary Technical Data

V

V

V

V

DD

SS

0.1µF0.1µF

VIN(NORMALLY

NC

V

OUT

CLOSED SWITCH)

VIN(NORMALLY
OPEN SWITCH)

V

OUT

∆V

OUT

Q

INJ

ON

= CL×∆V

OUT

OFF

04776-0-025

V

V

DD

SS

GND

SB

SA

C
1nF

L

D

V

S

IN

IN

Figure 29. Charge Injection

V

0.1µF

IN

IN

V

DD

V

SS

0.1µF

NETWORK

V

DD

SS

NC

SA

SB

50Ω

D

GND

ANALYZER

50Ω

V

OUT

R

L

50Ω

V

S

NETWORK

ANALYZER

V

OUT

R

L

50Ω



V

S

V

0.1µF

SA

SB

IN

CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG

OFF ISOLATION = 20 LOG

Figure 30. Off Isolation

V

OUT

V

S

04776-0-026

Figure 32. Bandwidth

V

DD

V

SS

0.1µF

V

DD

SS

D

R
50Ω

GND

V

OUT

V

S

04776-0-028

V

0.1µF

IN

V

IN

INSERTION LOSS = 20 LOG

V

DD

SS

0.1µF

V

V

DD

SS

NC

SB

SA

50Ω

D

GND

WITH SWITCH

V

OUT

V

WITHOUT SWITCH

OUT

Figure 31. Channel-to-Channel Crosstalk

NETWORK

ANALYZER

50Ω

V

OUT

R

L

50Ω

V

0.1µF

V

S

04776-0-027

IN

V

IN

V

DD

V

SS

0.1µF

V

DD

SS

AUDIO PRECISION

R

S

S

V

S

V p-p

V

OUT

04776-0-029

GND

D

R

L

600Ω

Figure 33. THD + Noise

Rev. PrC | Page 14 of 17

Preliminary Technical Data ADG1436

R

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in inches and (millimeters

PIN 1

INDICATO

1.00

0.85

0.80

4.00

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

Figure 35. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

0.60 MAX

13

12

EXPOSED

(BOTTOM VIEW)

9

8

PAD

16

1

4

5

1.95 BSC

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1436YRUZ −40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADG1436YRUZ-

REEL
ADG1436YRUZ-

REEL7
ADG1436YCPZ-

500RL7
ADG1436YCPZ-

REEL7

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

−40°C to +125°C Lead Frame Chip Scale Package (LFCSP) CP-16-4

−40°C to +125°C Lead Frame Chip Scale Package (LFCSP) CP-16-4

Rev. PrC| Page 15 of 17

ADG1436 Preliminary Technical Data

NOTES

Rev. PrC | Page 16 of 17

Preliminary Technical Data ADG1436

NOTES

© 2007Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

PR06817-0-5/07(PrC)

Rev. PrC| Page 17 of 17