Analog Devices ADG 1436 Service Manual

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2

Ω

±15 V/12 V/±5 V iCMOS™ Dual SPDT Switch

Max On Resistance,

Preliminary Technical Data

FEATURES

2Ω Max On Resistance

0.5Ω Max On Resistance Flatness

200mA continious current
33 V supply range
Fully specified at +12 V, ±15 V, ±5 V

supply required

No V

L

3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP packages

APPLICATIONS

Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay Replacement

ADG1436

FUNCTIONAL BLOCK DIAGRAM

ADG1436

S1A

S1B

IN1

IN2

S2A

S2B

SWITCHES SHOWN FOR A LOGIC "1" INPUT

Figure 1.TSSOP package

ADG1436

S1A

D1

S1B

LOGIC

D1

D2

S2A

D2

S2B

GENERAL DESCRIPTION

The ADG1436 is a monolithic CMOS device containing two
independently selectable SPDT switches. An EN input on the
LFCSP package is used to enable or disable the device. When
disabled, all channels are switched off. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. Both switches exhibit
break-before-make switching action for use in multiplexer
applications.

It is designed on an iCMOS process. iCMOS (industrial­CMOS) is a modular manufacturing process combining high
voltage CMOS (complementary metal-oxide semiconductor)
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no previous generation of high voltage parts
has been able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high supply

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

IN1 IN2

SWITCHES SHOWN FOR A “1” INPUT LOGIC

Figure 2.LFCSP package

EN

voltages, while providing increased performance, dramatically
lower power consumption, and reduced package size.

The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. iCMOS construction ensures ultralow
power dissipation, making the part ideally suited for portable
and battery-powered instruments.

PRODUCT HIGHLIGHTS

1. 2Ω Max On Resistance over temperature.

2. Minimum distortion

3. 3 V logic-compatible digital inputs: V

4. No V

logic power supply required.

L

5. Ultralow power dissipation: <0.03 µW.

6. 16-lead TSSOP and 16-lead 4 mm × 4mm LFCSP

packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2007 Analog Devices, Inc. All rights reserved.

= 2.0 V, VIL = 0.8 V.

IH

ADG1436 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Pin Configurations and Function Descriptions............................8

Dual Supply................................................................................... 3

Single Supply................................................................................. 4

Absolute Maximum Ratings............................................................ 7

Truth Table For Switches ............................................................. 8

ESD Caution.................................................................................. 7

REVISION HISTORY

Terminology.......................................................................................9

Typical Performance Characteristics........................................... 10

Test Circuits..................................................................................... 13

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. PrC | Page 2 of 17

Preliminary Technical Data ADG1436

SPECIFICATIONS

DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

25°C -40°C to

+85°C

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance (RON) 1.5 Ω typ VS = ±10 V, IS = −10 mA; Figure 23
2 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match between

Channels (∆R

)

ON

0.1 Ω typ V

0.5 Ω max

On Resistance Flatness (R

) 0.1 Ω typ VS = −5 V/0 V/+5 V; IS = −10 mA

FLAT(ON)

0.5 Ω max
LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.01 nA typ VS = ±10 V, Vs = ±10 V; Figure 23
±0.5 ±2.5 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = ±10 V, Vs = ±10 V;; Figure 23
±0.5 ±2.5 ±5 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = ±10 V; Figure 23
±1 ±2.5 ±5 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.005 µA typ VIN = V

INH

±0.5 µA max
Digital Input Capacitance, CIN 5 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

120 ns typ RL = 300 Ω, CL = 35 pF

TRANS

150 200 ns max VS = +10 V; Figure 25

tON (EN) 85 ns typ RL = 300 Ω, CL = 35 pF

105 130 140 ns max VS = 10 V; see Figure 25

t

(EN) 105 ns typ RL = 300 Ω, CL = 35 pF

OFF

125 150 170 ns max VS = 10 V; see Figure 25

Break-before-Make Time Delay, tD 15 40 ns typ RL = 300 Ω, CL = 35 pF

1 ns min VS1 = VS2 = +10 V; Figure 27

Charge Injection 50 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 29
Off Isolation 50 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 30
Channel-to-Channel Crosstalk 60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 31
Total Harmonic Distortion + Noise 0.015 % typ RL = 110Ω, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 100 MHz typ RL = 50 Ω, CL = 5 pF; Figure 32
CS (Off) 35 pF typ f = 1 MHz; VS = 0 V
CD (Off) 35 pF typ f = 1 MHz; VS = 0 V
CD, CS (On) 70 pF typ f = 1 MHz; VS = 0 V

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 µA typ Digital Inputs = 0 V or VDD
1 µA max
IDD 150 µA typ Digital Input = 5 V
300 µA max
ISS 0.001 µA typ Digital Inputs = 0 V, 5V or VDD

1.0 µA max

-40°C to
+125°C

= ±10 V, IS = −10 mA

S

V

= +16.5 V, VSS = −16.5 V

DD

or V

INL

INH

Rev. PrC| Page 3 of 17

ADG1436 Preliminary Technical Data

25°C -40°C to

+85°C

VDD/VSS ±4.5/±16.5 V min/max Gnd = 0V

1

Guaranteed by design, not subject to production test.

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

25°C -40°C to

+85°C

ANALOG SWITCH

Analog Signal Range
On Resistance (RON) 2.5

On Resistance Match between

Channels (∆R

)

ON

0.5

On Resistance Flatness (R

) 0.1

FLAT(ON)

0.5
LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.01

Drain Off Leakage, ID (Off) ±0.01

Channel On Leakage, ID, IS (On) ±0.04

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

Input Current, I

INH

INL

or I

INL

0.001

INH

Digital Input Capacitance, CIN 5

DYNAMIC CHARACTERISTICS1

Transition Time, t

120 ns typ RL = 300 Ω, CL = 35 pF

TRANS

150 200 ns max VS = 8 V; Figure 25

tON (EN) 85 ns typ

t

(EN) 105 ns typ

OFF

125 150 170 ns max

Break-before-Make Time Delay, tD 15

Charge Injection 30
Off Isolation 50
Channel-to-Channel Crosstalk 60
Total Harmonic Distortion + Noise 0.015 % typ RL = 110Ω, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 100
CS (Off) 35 pF typ f = 1 MHz; VS = 6V
CD (Off) 35 pF typ f = 1 MHz; VS = 6V
CD, CS (On) 70 pF typ f = 1 MHz; VS = 6 V

0 V to VDD V

3 4

0.1

±0.5 ±2.5 ±5 nA max

±0.5 ±2.5 ±5 nA max

±1 ±2.5 ±5 nA max

±0.5 µA max

105 130 140 ns max

1 ns min V

-40°C to
+125°C

-40°C to
+125°C

Ω typ VS = +10 V, IS = −10 mA; Figure 23
Ω max
Ω typ V

Ω max

= +10 V, IS = −10 mA

S

Ω typ VS = +3 V/+6 V/+9 V, IS = −10 mA

VDD = 12 V

nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 24

nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 24

nA typ VS = VD = 1 V or 10 V, Figure 25

2.0 V min

0.8 V max
µA typ VIN = V

pF typ

RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 25

ns typ RL = 300 Ω, CL = 35 pF

S1

pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 29
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 30;
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 31

MHz typ RL = 50 Ω, CL = 5 pF; Figure 32

or V

INH

INL

= VS2 = 8 V; Figure 27

Rev. PrC | Page 4 of 17

Preliminary Technical Data ADG1436

25°C -40°C to

+85°C

POWER REQUIREMENTS

IDD 0.001

IDD 150

VDD 5/16.5 V

1.0 µA max

300 µA max

1

Guaranteed by design, not subject to production test.

DUAL SUPPLY

VDD = 5 V ± 10%, VSS = -5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 3.

−40°C to

25°C
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 3
4
On Resistance Match Between

Channels (∆R

)

ON

0.1

On Resistance Flatness (R

) 0.1

FLAT(ON)

LEAKAGE CURRENTS
Source Off Leakage, IS (Off) ±0.01 nA typ

±0.5 ±2.5 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ

±0.5 ±2.5 ±5 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = ±4.5V; See figure x
±1 ±5 ±5 nA max
DIGITAL INPUTS
Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 µA typ VIN = V

INH

±0.5 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1

Transition Time, t

150 ns typ RL = 300 Ω, CL = 35 pF

TRANS

190 265 ns max VS = 3 V; Figure 25

tON (EN) 85 ns typ

105 130 140 ns max

t

(EN) 105 ns typ

OFF

125 150 170 ns max

Break-Before-Make Time Delay, tD 50 ns typ
10 ns min VS1 = VS2 = 3 V; See figure 25
Charge Injection 50 pC typ
Off Isolation 50 dB typ

Channel-to-Channel Crosstalk 60 dB typ

+85°C

-40°C to
+125°C

−40°C to
+125°C

VDD = 13.2 V

µA typ Digital Inputs = 0 V or VDD

µA typ Digital Inputs = 5 V

min/max

Gnd = 0V, Vss = 0V

Unit Test Conditions/Comments

Ω typ VS = ±3.3V, IS = −10 mA; See figure x
Ω max VDD = +4.5 V, VSS = −4.5 V
Ω typ V

Ω max

= ±3.3 V , IS = −10 mA

S

Ω typ VS = −3 V/0 V/+3 V; IS = −10 mA

VDD = +5.5 V, VSS = −5.5 V

VS = ±4.5 V, VD = ∓4.5 V; See figure x

VS = ±4.5 V, VD = ∓4.5 V; See figure x

or V

INH

INL

RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 25

= 300 Ω, CL = 35 pF

R

L

VS = 0 V, RS = 0 Ω, CL = 1 nF; See figure x
RL = 50 Ω, CL = 5 pF, f = 1 MHz; See figure

x
R

= 50 Ω, CL = 5 pF, f = 1 MHz; See figure

L

x

Rev. PrC| Page 5 of 17

ADG1436 Preliminary Technical Data

−40°C to

25°C

Total Harmonic Distortion + Noise 0.002 % typ RL = 110Ω, 5 V pp, f = 20 Hz to 20 kHz

−3 dB Bandwidth
CS (Off) 35 pF typ Vs = 0V, f = 1 MHz
CD (Off) 35 pF typ Vs = 0V, f = 1 MHz
CD, CS (On) 150 pF typ Vs = 0V, f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V , Vss = -5.5V
IDD 0.001 µA typ Digital inputs = 0 V or VDD

1.0 µA max
ISS 0.001 µA typ Digital inputs = 0 V or VDD

1.0 µA max

VDD/VSS ±4.5/±16.5 V

200 MHz typ

+85°C

−40°C to
+125°C Unit Test Conditions/Comments

RL = 50 Ω, CL = 5 pF; See figure x

Gnd = 0V

min/max

1

Guaranteed by design, not subject to production test.

Rev. PrC | Page 6 of 17