Datasheet ADG1433 Datasheet (ANALOG DEVICES)

4 Ω RON, Triple/Quad SPDT

A

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FEATURES

4.7 Ω maximum on resistance @ 25°C

0.5 Ω on resistance flatness Fully specified at ±15 V/+12 V/±5 V 3 V logic-compatible inputs Up to 115 mA continuous current per channel Rail-to-rail operation Break-before-make switching action 16-/20-lead TSSOP and 4 mm × 4 mm LFCSP_VQ packages

APPLICATIONS

Relay replacement Audio and video routing Automatic test equipment Data acquisition systems Temperature measurement systems Avio nics Battery-powered systems Communication systems Medical equipment

±15 V/+12 V/±5 V iCMOS Switches

ADG1433/ADG1434

FUNCTIONAL BLOCK DIAGRAMS

D1

D2

D1

IN1

ADG1433

LOGIC

IN1 IN2 IN3 EN

ADG1434

S3B

D3

S3A

S4A

D4

S4B

IN4

06181-001

S1A

S1B

S2B

S2A

SWITCHES SHOWN FOR A 1 INPUT LO GIC.

Figure 1. ADG1433 TSSOP and LFCSP_VQ

S1

S1B

GENERAL DESCRIPTION

The ADG1433 and ADG1434 are monolithic industrial CMOS (iCMOS®) analog switches comprising three independently selectable single-pole, double-throw (SPDT) switches and four independently selectable SPDT switches, respectively.

All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An input on the ADG1433 (LFCSP and TSSOP packages) and ADG1434 (LFCSP package only) is used to enable or disable the device. When disabled, all channels are switched off.

The iCMOS modular manufacturing process combines high voltage, complementary metal-oxide semiconductor (CMOS), and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using a conventional CMOS process, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.

The ultralow on resistance and on resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.

EN

IN2

S2B

D2

S2

SWITCHES S HOWN FOR

1 INPUT LOGIC.

Figure 2. ADG1434 TSSOP

S1A

S1B

S2B

S2A

SWITCHES SHOWN F OR A 1 INPUT LO GIC.

ADG1434

D1

D2

LOGIC

IN1

IN2 IN3 IN4 EN

Figure 3. ADG1434 LFCSP_VQ

IN3

S3B

D3

S3A

S4A

D4

S4B

S3B

D3

S3A

06181-002

06181-101

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

6/08—Rev. 0 to Rev. A

Added Continuous Current per Channel Parameter (Table 1) .. 4 Added Continuous Current per Channel Parameter (Table 2) .. 5 Added Continuous Current per Channel Parameter (Table 3) .. 6

Changes to Table 4 ............................................................................ 7

Changes to Figure 30 ...................................................................... 13

Updated Outline Dimensions ....................................................... 16

Changes to Ordering Guide .......................................................... 17

10/06—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................7

Thermal Resistance .......................................................................7

ESD Caution...................................................................................7

Pin Configurations and Function Descriptions ............................8

Typical Performance Characteristics ........................................... 10

Test Circuits ..................................................................................... 13

Terminology .................................................................................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 17

Rev. A | Page 2 of 20

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SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

−40°C to

Parameter +25°C

ANALOG SWITCH

Analog Signal Range VSS to VDD V On-Resistance, RON 4 Ω typ VS = ±10 V, IS = −10 mA; see Figure 25

4.7 5.7 6.7 Ω max VDD = +13.5 V, VSS = −13.5 V On-Resistance Match Between 0.5 Ω typ VS = ±10 V, IS = −10 mA

Channels, ΔRON 0.78 0.85 1.1 Ω max

On Resistance Flatness, R

0.72 0.77 0.92 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.04 nA typ VD = ±10 V, VS = ±10 V; see Figure 26 ±0.3 ±0.6 ±3 nA max Drain Off Leakage, ID (Off) ±0.04 nA typ VD = ±10 V, VS = ±10 V; see Figure 26 ±0.3 ±0.6 ±3 nA max Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = ±10 V; see Figure 27 ±0.4 ±0.8 ±8 nA max

DIGITAL INPUTS

Input High Voltage, VIH 2.0 V min Input Low Voltage, VIL 0.8 V max Input Current, IIL or IIH ±0.005 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t 170 200 230 ns max VS = 10 V, see Figure 28 Break-Before-Make Time Delay, tD 40 ns typ RL = 100 Ω, CL = 35 pF 30 ns min VS1 = VS2 = 10 V, see Figure 29 tON (EN) 170 200 230 ns max VS = 10 V, see Figure 30 t

(EN)

OFF

75 85 90 ns max VS = 10 V, see Figure 30 Charge Injection −50 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 31 Off Isolation −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32 Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34 Total Harmonic Distortion, THD + N 0.025 % typ

−3 dB Bandwidth Insertion Loss 0.24 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33 CS (Off) 12 pF typ f = 1 MHz CD (Off) 22 pF typ f = 1 MHz CD, CS (On) 72 pF typ f = 1 MHz

140 ns typ RL = 100 Ω, CL = 35 pF

TRANS

0.5 Ω typ VS = ±10 V, IS = −10 mA

FLAT(ON)

140 ns typ R

60 ns typ R

200 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 33

+85°C

−40°C to +125°C1 Unit Test Conditions/Comments

or VDD

GND

= 100 Ω, CL = 35 pF

L

= 100 Ω, CL = 35 pF

L

= 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz, see

R

L

Figure 35

Rev. A | Page 3 of 20

ADG1433/ADG1434

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−40°C to

Parameter +25°C

POWER REQUIREMENTS

IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 260 μA typ Digital inputs = 5 V 440 μA max ISS 0.001 μA typ Digital inputs = 0 V, 5 V, or VDD 1 μA max VDD/VSS ±4.5/±16.5 V min/max GND = 0 V Continuous Current per Channel

ADG1433 115 75 40 mA max ADG1434 100 65 40 mA max

1

Temperature range for Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

2

V

+85°C

−40°C to +125°C

1

Unit Test Conditions/Comments

VDD = +16.5 V, VSS = −16.5 V

= +13.5 V, VSS = −13.5 V

DD

Rev. A | Page 4 of 20

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12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 to VDD V

−40°C to

On-Resistance, RON

6 Ω typ 8 9.5 11.2 Ω max VDD = 10.8 V, VSS = 0 V On-Resistance Match Between 0.55 Ω typ VS = 0 V to 10 V, IS = −10 mA

Channels, ΔRON 0.82 0.85 1.1 Ω max

On Resistance Flatness, R

1.5 Ω typ VS = 0 V to 10 V, IS = −10 mA

FLAT(ON)

2.5 2.5 2.8 Ω max

LEAKAGE CURRENTS VDD = 13.2 V

Source Off Leakage, IS (Off) ±0.04 nA typ ±0.3 ±0.6 ±3 nA max Drain Off Leakage, ID (Off) ±0.04 nA typ

±0.3 ±0.6 ±3 nA max

Channel On Leakage, ID, IS (On) ±0.06 nA typ

±0.4 ±0.8 ±8 nA max

DIGITAL INPUTS

Input High Voltage, VIH 2.0 V min Input Low Voltage, VIL 0.8 V max Input Current, IIL or IIH ±0.005 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

200 ns typ RL = 100 Ω, CL = 35 pF

TRANS

255 310 350 ns max Break-Before-Make Time Delay, tD 80 ns typ RL = 100 Ω, CL = 35 pF 55 ns min tON (EN)

210 ns typ 270 320 360 ns max t

OFF

(EN)

70 ns typ

86 95 105 ns max

Charge Injection

−10 pC typ Off Isolation –70 dB typ Channel-to-Channel Crosstalk –70 dB typ

−3 dB Bandwidth

135

Insertion Loss 0.5 dB typ CS (Off) 25 pF typ f = 1 MHz CD (Off) 45 pF typ f = 1 MHz CD, CS (On) 80 pF typ f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 260 μA typ Digital inputs = 5 V

440 μA max

VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V Continuous Current per Channel2

V ADG1433 100 65 40 mA max ADG1434 85 60 35 mA max

1

Temperature range for Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

−40°C to +125°C

1

Unit Test Conditions/Comments

V

= 0 V to 10 V, IS = −10 mA, see Figure 25

S

V

= 1 V/10 V, VD = 10 V/1 V, see Figure 26

S

V

= 1 V/10 V, VD = 10 V/1 V, see Figure 26

S

V

= VD = 1 V or 10 V, see Figure 27

S

or VDD

GND

V

= 8 V, see Figure 28

S

V

= VS2 = 8 V, see Figure 29

S1

= 100 Ω, CL = 35 pF

R

L

V

= 8 V, see Figure 30

S

= 100 Ω, CL = 35 pF

R

L

V

= 8 V, see Figure 30

S

V

= 6 V, RS = 0 Ω, CL = 1 nF, see Figure 31

S

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32

L

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34

L

R

MHz typ

= 50 Ω, CL = 5 pF, see Figure 33

L

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33

L

= +10.8 V, VSS = 0 V

DD

Rev. A | Page 5 of 20

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±5 V DUAL SUPPLY

VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 3.

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range VSS to VDD V On Resistance (RON) 7 Ω typ 9 10.5 12 Ω max VDD = +4.5 V, VSS = −4.5 V On-Resistance Match Between 0.55 Ω typ VS = ±4.5 V, IS = −10 mA

Channels (ΔRON) 0.78 0.91 1.1 Ω max

−40°C to

On-Resistance Flatness, R

1.5 Ω typ VS = ±4.5 V, IS = −10 mA

FLAT(ON)

2.5 2.5 3 Ω max

LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V

Source Off Leakage, IS (Off) ±0.02 nA typ ±0.3 ±0.6 ±3 nA max Drain Off Leakage, ID (Off) ±0.02 nA typ

±0.3 ±0.6 ±3 nA max

Channel On Leakage, ID, IS (On) ±0.04 nA typ

±0.4 ±0.8 ±8 nA max

DIGITAL INPUTS

Input High Voltage, VIH 2.0 V min Input Low Voltage, VIL 0.8 V max Input Current, IIL or IIH ±0.005 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

315 ns typ RL = 100 Ω, CL = 35 pF

TRANS

430 480 550 ns max Break-Before-Make Time Delay, tD 90 ns typ RL = 100 Ω, CL = 35 pF 55 ns min tON (EN)

325 ns typ R 425 490 545 ns max t

(EN)

OFF

150 ns typ R 200 225 240 ns max Charge Injection −10 pC typ Off Isolation −70 dB typ Channel-to-Channel Crosstalk −70 dB typ Total Harmonic Distortion, THD + N 0.06 % typ

−3 dB Bandwidth

145 MHz typ

Insertion Loss 0.5 dB typ CS (Off) 18 pF typ f = 1 MHz CD (Off) 32 pF typ f = 1 MHz CD, CS (On) 80 pF typ f = 1 MHz

POWER REQUIREMENTS

IDD 0.002 μA typ Digital inputs = 0 V, 5 V, or VDD 1 μA max ISS 0.001 μA typ Digital inputs = 0 V, 5 V, or VDD 1 μA max VDD/VSS ±4.5/±16.5 V min/max GND = 0 V Continuous Current per Channel2

ADG1433 95 60 35 mA max ADG1434 85 55 35 mA max

1

Temperature range for Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

−40°C to

1

+125°C

Rev. A | Page 6 of 20

Unit Test Conditions/Comments

V

= ±4.5 V, IS = −10 mA, see Figure 25

S

V

= ±4.5 V, VS = ±4.5 V, see Figure 26

D

V

= ±4.5 V, VS = ±4.5 V, see Figure 26

D

V

= VD = ±4.5 V, see Figure 27

S

or VDD

GND

V

= 5 V, see Figure 28

S

V

= VS2 = 5 V, see Figure 29

S1

= 100 Ω, CL = 35 pF

L

V

= 5 V, see Figure 30

S

= 100 Ω, CL = 35 pF

L

V

= 5 V, see Figure 30

S

V

= 0 V, RS = 0 Ω, CL = 1 nF, see Figure 31

S

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 32

L

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34

L

R

= 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz, see Figure 35

L

R

= 50 Ω, CL = 5 pF, see Figure 33

L

R

= 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33

L

V

= +5.5 V, VSS = −5.5 V

DD

V

= +4.5 V, VSS = −4.5 V

DD

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND −25 V to +0.3 V Analog Inputs, Digital Inputs1

Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum)

Continuous Current, S or D2 Data + 15% Operating Temperature Range

Industrial (Y Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Reflow Soldering Peak

Temperature (Pb-Free)

1

Overvoltages at A, EN, S, or D pins are clamped by internal diodes. Current

should be limited to the maximum ratings given.

2

See data given in the Specifications section (see Table 1 to Table 3).

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating may be applied at any one time.

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs first 250 mA

260 (+ 0 to −5)°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 5.

Package Type θJA θ

TSSOP 150.4 50 °C/W LFCSP_VQ 30.4 N/A °C/W

Unit

JC

ESD CAUTION

Rev. A | Page 7 of 20

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD

14 GND

13 IN1

16 S1A

1

V

DD

2

S1A

3

D1

ADG1433

4

D2

TOP VIEW

(Not to Scale)

5

6

7

8

S1B

S2B

S2A

IN2 IN3

16

GND

15

IN1

14

EN

13

V

SS

12

S3B

11

D3

10

S3A

9

06181-003

Figure 4. ADG1433 TSSOP Pin Configuration

Table 6. ADG1433 Pin Function Descriptions

Pin No.

Mnemonic Description TSSOP LFCSP_VQ

1 15 VDD Most Positive Power Supply Potential. 2 16 S1A Source Terminal 1A. Can be an input or an output. 3 1 D1 4 2 S1B 5 3 S2B 6 4 D2 7 5 S2A 8 6 IN2 9 7 IN3 10 8 S3A 11 9 D3 12 10 S3B 13 11 V 14 12

SS

EN Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx

Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.

Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input 2. Logic Control Input 3. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output.

logic inputs determine the on switches.

15 13 IN1

Logic Control Input 1.

16 14 GND Ground (0 V) Reference.

1D1

2S1B

3S2B

4D2

NOTES

1. EXPOSED PAD IS TIED TO SUBSTRATE, V

Figure 5. ADG1433 LFCSP_VQ Pin Configuration

15 V

PIN 1 INDICATO R

ADG1433

TOP VIEW

(Not to Scale)

7

5

6 2

IN

IN3

S2A

12 EN

11 V

SS

10 S3B

9D3

8

S3A

.

SS

06181-005

Table 7. ADG1433 Truth Table

EN

INx SxA SxB

1 X Off Off 0 0 Off On 0 1 On Off

Rev. A | Page 8 of 20

ADG1433/ADG1434

V

A

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1

IN1

2

S1A

3

D1

4

S1B

GND

S2B

S2A

ADG1434

5

V

SS

TOP VIEW

(Not to Scale)

6

7

8

D2 D3

9

10

IN2

NC = NO CONNECT

Figure 6. ADG1434 TSSOP Pin Configuration

20

IN4

19

S4A

18

D4

17

S4B

16

V

DD

15

NC

14

S3B

13

12

S3A

11

IN3

06181-004

1D1 2S1B 3V

SS

4GND 5S2B

NOTES

1. EXPOSED P AD IS TIED TO SUBSTRAT E,

4 IN

EN

IN1

S1

17

18

19

20

PIN 1 INDICAT OR

ADG1434

TOP VIEW

(Not to Scale)

9

8

6

7

D2

IN2

IN3

S2A

S4

16

15 D4 14 S4B 13 V

DD

12 S3B 11 D3

10

S3A

.

SS

06181-006

Figure 7. ADG1434 LFCSP_VQ Pin Configuration

Table 8. ADG1434 Pin Function Descriptions

Pin No.

TSSOP Mnemonic Description LFCSP_VQ

1 19 IN1 Logic Control Input 1. 2 20 S1A Source Terminal 1A. Can be an input or an output. 3 1 D1 Drain Terminal 1. Can be an input or an output. 4 2 S1B Source Terminal 1B. Can be an input or an output. 5 3 VSS Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground. 6 4 GND Ground (0 V) Reference. 7 5 S2B Source Terminal 2B. Can be an input or an output. 8 6 D2 Drain Terminal 2. Can be an input or an output. 9 7 S2A Source Terminal 2A. Can be an input or an output. 10 8 IN2 Logic Control Input 2. 11 9 IN3 Logic Control Input 3. 12 10 S3A Source Terminal 3A. Can be an input or an output. 13 11 D3 Drain Terminal 3. Can be an input or an output. 14 12 S3B Source Terminal 3B. Can be an input or an output. 15 N/A NC No Connect. 16 13 VDD Most Positive Power Supply Potential. 17 14 S4B Source Terminal 4B. Can be an input or an output. 18 15 D4 Drain Terminal 4. Can be an input or an output. 19 16 S4A Source Terminal 4A. Can be an input or an output. 20 17 IN4 Logic Control Input 4. N/A 18

EN

Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches.

Table 9. ADG1434 TSSOP Truth Table

INx SxA SxB

0 Off On 1 On Off

Table 10. ADG1434 LFCSP_VQ Truth Table

EN

INx SxA

1 X Off Off 0 0 Off On 0 1 On Off

Rev. A | Page 9 of 20

SxB

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TYPICAL PERFORMANCE CHARACTERISTICS

6

TA = 25°C

5

4

3

2

ON RESISTANCE (Ω)

VDD = +15V, VSS = –15V V

= +13.5V, VSS = –13.5V

DD

1

V

= +12V, VSS = –12V

DD

V

= +10V, VSS = –10V

DD

V

= +16.5V, VSS = –16.5V

DD

0

–16.5 15.5

–12.5 –8.5 –4.5 –0.5 3.5 7. 5 11.5

SOURCE OR DRAIN VO LTAGE (V)

Figure 8. On Resistance as a Function of V

9

TA = 25°C

8

7

6

5

4

3

ON RESISTANCE (Ω)

2

VDD = +7V, VSS = –7V V

= +5.5V, VSS = –5.5V

DD

1

V

= +5V, VSS = –5V

DD

V

= +4.5V, VSS = –4.5V

DD

0

–7 –4–5–6 7

–3 –2 –1 0 54312 6

SOURCE OR DRAIN VO LTAGE (V)

(VS), Dual Supply

D

Figure 9. On Resistance as a Function of VD (VS), Dual Supply

13

12

11

10

9

8

7

6

5

4

ON RESISTANCE (Ω)

3

VDD = 12V

= 13.2V

V

DD

2

= 10.8V

V

DD

= 8V

V

1

DD

= 5V

V

DD

0

1 2 3 4 5 6 7 8 9 10 11 12 13

SOURCE OR DRAIN VO LTAGE (V)

TA = 25°C

= 0V

V

SS

Figure 10. On Resistance as a Function of VD (VS), Single Supply

06181-007

06181-008

06181-009

7

6

5

4

3

ON RESISTANCE (Ω)

2

TA = +25°C

1

= +85°C

T

A

T

= –40°C

A

= +125°C

T

A

0

–15

–10 –5 0 5 10

SOURCE OR DRAIN VO LTAGE (V)

Figure 11. On Resistance as a Function of V

VDD = +15V V

= –15V

SS

15

(VS) for Different Temperatures,

D

06181-010

±15 V Dual Supply

12

10

8

6

4

ON RESISTANCE (Ω)

TA = +25°C

2

= +85°C

T

A

= –40°C

T

A

T

= +125°C

A

0

–5

–4–3–2–101234

SOURCE OR DRAIN VO LTAGE (V)

VDD = +5V

= –5V

V

SS

5

06181-011

Figure 12. On Resistance as a Function of VD (VS) for Different Temperatures,

±5 V Dual Supply

10

9

8

7

6

5

4

ON RESISTANCE (Ω)

3

2

TA = +25°C

= +85°C

T

A

1

= –40°C

T

A

= +125°C

T

A

0

246810

SOURCE OR DRAIN VO LTAGE (V)

VDD = 12V V

= 0V

SS

12

06181-012

Figure 13. On Resistance as a Function of VD (VS) for Different Temperatures,

12 V Single Supply

Rev. A | Page 10 of 20

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1600

VDD = +15V

= –15V

V

SS

LEAKAGE CURRENTS (p A)

1400

1200

1000

800

600

400

200

–200

0

V

BIAS

= +10V/–10V

(OFF) – +

I

S

TEMPERATURE (° C)

(ON) + +

I

D,IS

IS (OFF) + –

(ON) – –

I

D,IS

120100806040200

06181-013

Figure 14. Leakage Currents as a Function of Temperature, ±15 V Dual Supply

1600

VDD = +5V

= –5V

V

SS

LEAKAGE CURRENTS (p A)

1400

1200

1000

800

600

400

200

–200

0

= +4.5V/–4.5V

V

BIAS

I

D,IS

TEMPERATURE (° C)

I

D,IS

IS (OFF) + –

(ON) – –

(ON) + +

I

(OFF) – +

S

120100806040200

06181-014

Figure 15. Leakage Currents as a Function of Temperature, ±5 V Dual Supply

70

60

50

40

(µA)

DD

I

30

20

10

0

01

VDD = +12V V

= 0V

SS

VDD = +5V V

= –5V

SS

24681012

LOGIC, INx (V)

IDD PER CHANNEL

= 25°C

T

A

VDD = +15V V

= –15V

SS

4

06181-015

Figure 17. IDD vs. Logic Level

200

TA = 25°C

150

100

50

0

–50

CHARGE INJECTI ON (pC)

–100

–150

–200

–15 151050–5–10

VDD = +15V V

= –15V

SS

= +5V

V

DD

V

= –5V

SS

V

(V)

S

V V

DD SS

= +12V = 0V

06181-016

Figure 18. Charge Injection vs. Source Voltage

2000

VDD = 12V

1800

= 0V

V

SS

V

= 1V/10V

LEAKAGE CURRENTS (p A)

1600

1400

1200

1000

800

600

400

200

–200

BIAS

IS (OFF) + –

0

TEMPERATURE (° C)

I

D,IS

I

D,IS

(ON) + +

(ON) – –

I

(OFF) – +

S

Figure 16. Leakage Currents as a Function of Temperature,

12 V Single Supply

120100806040200

06181-020

Rev. A | Page 11 of 20

350

300

V

= +5V

DD

250

V

= –5V

SS

200

150

TIME (ns)

100

50

0

TEMPERATURE (° C)

= +12V

V

DD

V

= 0V

SS

VDD = +15V V

= –15V

SS

120100806040200–20–40

06181-017

Figure 19. Transition Time vs. Temperature

ADG1433/ADG1434

www.BDTIC.com/ADI

0

VDD = +15V V

= –15V

–10

SS

T

= 25°C

A

–20

–30

–40

–50

–60

–70

OFF ISOLATION (dB)

–80

–90

–100

–110

1k 1G

10k 100k 1M 10M 100M

FREQUENCY (Hz)

06181-018

0.10

LOAD = 110Ω T

= 25°C

0.09

A

0.08

0.07

0.06

0.05

0.04

THD + N (%)

0.03

0.02

0.01

0

10 100k

VDD = +5V, VSS = –5V, VS = +5V p-p

VDD = +15V, VSS = –15V, VS = +15V p-p

100 1k 10k

FREQUENCY (Hz)

06181-032

Figure 20. Off Isolation vs. Frequency Figure 23. THD + N vs. Frequency

0

VDD = +15V V

= –15V

–10

SS

T

= 25°C

A

–20

–30

–40

–50

–60

–70

CROSSTALK (d B)

–80

–90

–100

–110

1k 1G

10k 100k 1M 10M 100M

FREQUENCY (Hz)

06181-019

0

VDD = +15V

= –15V

V

SS

= 25°C

T

A

–20

V p-p = 0. 63V

–40

NO DECOUPLING

–60

ACPSRR (dB)

–80

–100

–120

100 1k 10M

CAPACITORS

10k 100k 1M

FREQUENCY (Hz)

DECOUPLING CAPACITORS ON SUPPLIES

06181-035

Figure 21. Crosstalk vs. Frequency Figure 24. ACPSRR vs. Frequency

–0.5

–1.0

–1.5

–2.0

–2.5

ON RESPONSE (dB)

–3.0

–3.5

–4.0

0

100 1G100M10M1M100k10k1k

FREQUENCY (Hz)

VDD = +15V V

= –15V

SS

T

= 25°C

A

06181-100

Figure 22. On Response vs. Frequency

Rev. A | Page 12 of 20

ADG1433/ADG1434

V

VDDV

V

www.BDTIC.com/ADI

TEST CIRCUITS

OUT

ID(ON)

V

OUT

IS(OFF) ID (OFF)

SD

A A

S

V

D

06181-022

Figure 26. Off Leakage

A

V

D

06181-023

IN

50%

90%

t

ON

50%

90%

t

OFF

06181-024

V

SD

I

S

DS

06181-021

Figure 25. On Resistance

SD

NC

NC = NO CONNECT

Figure 27. On Leakage

SS

0.1µF0.1µF

V

DD

GND

SS

D

R

L

100Ω

C

L

35pF

V

SB

V

S

SA

IN

V

IN

Figure 28. Switching Timing

SS

0.1µF0.1µF

V

DD

GND

SS

D

R

L

100Ω

C

L

35pF

V

OUT

SB

V

S

SA

IN

V

IN

Figure 29. Break-Before-Make Delay, t

IN

80%

V

OUT

t

BBM

D

t

BBM

06181-025

V

DD

SS

0.1µF0.1µF

V

DD

SS

ADG1433

INx

EN

50Ω

V

IN

S1A

S1B

GND

V

S

V

D1

R

L

100Ω

C

L

35pF

OUT

Figure 30. Enable Delay, t

ENABLE

DRIVE (V

OUTPUT

(EN), t

ON

3V

50%

)

IN

0V

V

OUT

0V

OFF

0.9V

(EN)

50%

t

(EN)

OFF

0.9V

OUT

t

(EN)

ON

OUT

06181-026

Rev. A | Page 13 of 20

ADG1433/ADG1434

VDDV

V

www.BDTIC.com/ADI

SS

0.1µF0.1µF

VIN(NORMALLY

OUT

CLOSED SWI TCH)

VIN(NORMALLY OPEN SWITCH)

V

OUT

ΔV

OUT

Q

INJ

ON

= CL × ΔV

OUT

OFF

06181-027

V

DD

SS

D

V

S

IN

V

IN

SB

SA

GND

C 1nF

NC

V

L

Figure 31. Charge Injection

DD

0.1µF

V

DD

IN

SS

0.1µF

V

SS

SB

SA

D

GND

OFF ISOLATION = 20 log

Figure 32. Off Isolation

NC

50Ω

NETWO RK

NETWORK ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

V

OUT

V

S

6181-028

ANALYZER

V

OUT

R

L

50Ω

V

S

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

Figure 34. Channel-to-Channel Crosstalk

0.1µF

V

DD

SA

SB

IN

GND

V

OUT

V

SS

0.1µF

V

SS

D

R 50Ω

S

06181-030

DD

0.1µF

V

DD

IN

SS

0.1µF

V

SS

SA

D

GND

INSERTION LOSS = 20 log

SB

NC

50Ω

Figure 33. Bandwidth

WITH SWITCH

V

OUT

WITHOUT SWITCH

V

OUT

NETWORK ANALYZER

50Ω

V

OUT

R

L

50Ω

DD

0.1µF

V

S

IN

V

IN

06181-029

SS

0.1µF

R

L

110Ω

AUDIO PRECISI ON

R

S

V

S

V p-p

V

OUT

06181-031

V

DD

SS

S

D

GND

Figure 35. THD + Noise

Rev. A | Page 14 of 20

ADG1433/ADG1434

www.BDTIC.com/ADI

TERMINOLOGY

T

RON

Ohmic resistance between Terminal D and Terminal S.

ΔR

ON

The difference between the R

FLAT(ON)

R

of any two channels.

ON

The difference between the maximum and minimum value of on resistance as measured.

I

(Off)

S

Source leakage current when the switch is off.

I

(Off)

D

Drain leakage current when the switch is off.

I

, IS (On)

D

Channel leakage current when the switch is on.

V

(VS)

D

Analog voltage on Terminal D and Terminal S.

C

(Off)

S

Channel input capacitance for off condition.

C

(Off)

D

Channel output capacitance for off condition.

C

, CS (On)

D

On switch capacitance.

C

IN

Digital input capacitance.

(EN)

t

ON

Delay time between the 50% and 90% points of the digital input and switch on condition.

t

(EN)

OFF

Delay time between the 50% and 90% points of the digital input and switch off condition.

t

TRANS

Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another.

BBM

Off time measured between the 80% point of both switches when switching from one address state to another.

V

IL

Maximum input voltage for Logic 0.

V

IH

Minimum input voltage for Logic 1.

I

(IIH)

IL

Input current of the digital input.

I

DD

Positive supply current.

I

SS

Negative supply current.

Off Isolation

A measure of unwanted signal coupling through an off channel.

Charge Injection

A measure of the glitch impulse transferred from the digital input to the analog output during switching.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Total Harmonic Distortion + Noise (THD + N)

The ratio of the harmonic amplitude plus noise of the signal to the fundamental.

AC Power Supply Rejection Ratio (ACPSRR)

A measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.

Rev. A | Page 15 of 20

ADG1433/ADG1434

C

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

BSC

81

1.20 MAX

SEATING PLANE

6.40

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.50

0.40

INDI

SEATING

PIN 1

ATO R

1.00

0.85

0.80

PLANE

12° MAX

4.00

BSC SQ

3.75

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.05 MAX

0.30

0.23

0.18

COMPLIANTTOJEDEC STANDARDS MO-220-VGGC.

0.02 NOM

0.20 REF

0.60 MAX

12

0.65

9

BSC

1.95 BSC

COPLANARITY

0.08

13

EXPOSED

8

BOTTOM VIEW

Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm, Very Thin Quad (CP-16-13)

Dimensions shown in millimeters

PAD

0.30

1

16

4

5

P

N

I

N

I

D

2.65

2.50 SQ

2.35

0.25 MIN

1

R

O

C

I

A

T

122107-A

Rev. A | Page 16 of 20

ADG1433/ADG1434

Y

C

www.BDTIC.com/ADI

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARIT

0.10

20

1

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AC

1.20 MAX

11

10

SEATING PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 38. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

0.08

0.50

BSC

0.75

0.60

0.50

0.60 MAX

15

11

16

EXPOSED

PAD

(BOTTOM VIEW)

10

P

N

I

1

R

A

O

T

N

I

D

C

2.45

2.30 SQ

2.15

0.25 MIN

I

012508-B

20

1

5

6

INDI

ATO R

1.00

0.85

0.80

SEATING

PLANE

PIN 1

4.00

12° MAX

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT

BCS SQ

TO

0.60 MAX

3.75

0.05 MAX

0.02 NOM COPLANARITY

0.20 REF

JEDEC STANDARDS MO-220-VGGD-1

Figure 39. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad (CP-20-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Description

ADG1433YRUZ ADG1433YRUZ-REEL ADG1433YRUZ-REEL71 ADG1433YCPZ-REEL1 ADG1433YCPZ-REEL71 ADG1434YRUZ ADG1434YRUZ-REEL ADG1434YRUZ-REEL71 ADG1434YCPZ-REEL1 ADG1434YCPZ-REEL71

1

Z = RoHS Compliant Part.

1

−40°C to +125°C

1

−40°C to +125°C

1

−40°C to +125°C

1

−40°C to +125°C

16-Lead Thin Shrink Small Outline Package [TSSOP] Yes RU-16 16-Lead Thin Shrink Small Outline Package [TSSOP] Yes RU-16 16-Lead Thin Shrink Small Outline Package [TSSOP] Yes RU-16 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes CP-16-13 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes CP-16-13 20-Lead Thin Shrink Small Outline Package [TSSOP] No RU-20 20-Lead Thin Shrink Small Outline Package [TSSOP] No RU-20 20-Lead Thin Shrink Small Outline Package [TSSOP] No RU-20 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes CP-20-3 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Yes CP-20-3

Rev. A | Page 17 of 20

EN

Package Option

ADG1433/ADG1434

www.BDTIC.com/ADI

NOTES

Rev. A | Page 18 of 20

ADG1433/ADG1434

www.BDTIC.com/ADI

NOTES

Rev. A | Page 19 of 20

ADG1433/ADG1434

www.BDTIC.com/ADI

NOTES

Rev. A | Page 20 of 20

Datasheet ADG1433 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

±15 V DUAL SUPPLY

12 V SINGLE SUPPLY

±5 V DUAL SUPPLY

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

TERMINOLOGY

OUTLINE DIMENSIONS

ORDERING GUIDE