ANALOG DEVICES ADG1408, ADG1409 Service Manual

4 Ω RON, 4-/8-Channel

www.BDTIC.com/ADI

FEATURES

4.7 Ω maximum on resistance @ 25°C

0.5 Ω on resistance flatness Up to 190 mA continuous current Fully specified at ±15 V/+12 V/±5 V 3 V logic-compatible inputs Rail-to-rail operation Break-before-make switching action 16-lead TSSOP and 4 mm × 4 mm LFCSP packages

APPLICATIONS

Relay replacement Audio and video routing Automatic test equipment Data acquisition systems Temperature measurement systems Avio nics Battery-powered systems Communication systems Medical equipment

±15 V/+12 V/±5 V iCMOS Multiplexers

ADG1408/ADG1409

FUNCTIONAL BLOCK DIAGRAM

ADG1408

S1

S8

1-OF-8

DECODER

S1A

S4A

D

S1B

S4B

Figure 1.

ADG1409

1-OF-4

DECODER

A0 A1 ENA0 A1 A2 EN

DA

DB

04861-001

GENERAL DESCRIPTION

The ADG1408/ADG1409 are monolithic iCMOS® analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG1408 switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, A0, A1, and A2. The ADG1409 switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, A0 and A1. An EN input on both devices is used to enable or disable the device. When disabled, all channels are switched off.

The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.

The ultralow on resistance and on resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments.

PRODUCT HIGHLIGHTS

1. 4 Ω on resistance.

2. 0.5 Ω on resistance flatness.

3. 3 V logic compatible digital input, V

4. 16-lead TSSOP and 4 mm × 4 mm LFCSP packages.

Table 1. Related Devices

Part No. Description

ADG1208/ADG1209

Low capacitance, low charge injection, and low leakage 4-/8-channel ±15 V multiplexers

= 2.0 V, VIL = 0.8 V.

IH

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

8/08—Rev. 0 to Rev. A

Changes to Features .......................................................................... 1

Added Table 5; Renumbered Sequentially .................................... 8

Changes to Table 6 ............................................................................ 9

Added Exposed Pad Notation to Figure 3 ................................... 10

Added Exposed Pad Notation to Figure 5 ................................... 11

Added Exposed Pad Notation to Outline Dimensions ............. 19

8/06—Revision 0: Initial Version

Continuous Current per channel, S or D ...................................8

Absolute Maximum Ratings ............................................................9

Thermal Resistance .......................................................................9

ESD Caution...................................................................................9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 12

Terminolog y .................................................................................... 16

Test Circuits ..................................................................................... 17

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 20

Rev. A | Page 2 of 20

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SPECIFICATIONS

15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 2.

−40°C to

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range VSS to VDD V On Resistance (RON) 4 Ω typ VS = ±10 V, IS = −10 mA; see Figure 26

4.7 5.7 6.7 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between 0.2 Ω typ VS = ±10 V, IS = −10 mA

Channels (ΔRON) 0.78 0.85 1.1 Ω max

On Resistance Flatness (R

) 0.5 Ω typ VS = ±10 V, IS = −10 mA

FLAT(ON)

0.72 0.77 0.92 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS −16.5 V =

Source Off Leakage, IS (Off) ±0.04 nA typ ±0.2 ±0.6 ±5 nA max Drain Off Leakage, ID (Off) ±0.04 nA typ ±0.45 ±2 ±30 nA max Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 28 ±1.5 ±3 ±30 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V

2.0 V min

INH

0.8 V max

INL

Input Current ±0.005 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

140 ns typ RL = 100 Ω, CL = 35 pF

TRANSITION

170 210 240 ns max VS = 10 V, see Figure 29 Break-Before-Make Time Delay, t

50 ns typ RL = 100 Ω, CL = 35 pF

BBM

30 ns min VS1 = VS2 = 10 V; see Figure 30 tON (EN) 100 ns typ RL = 100 Ω, CL = 35 pF 120 150 165 ns max VS = 10 V; see Figure 31 t

(EN) 100 ns typ RL = 100 Ω, CL = 35 pF

OFF

120 150 170 ns max VS = 10 V; see Figure 31 Charge Injection −50 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33 Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 Total Harmonic Distortion, THD + N 0.025 % typ

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 35 ADG1408 60 MHz typ ADG1409 115 MHz typ

Insertion Loss 0.24 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 CS (Off) 14 pF typ f = 1 MHz CD (Off)

ADG1408 80 pF typ f = 1 MHz ADG1409 40 pF typ f = 1 MHz

CD, CS (On)

ADG1408 135 pF typ f = 1 MHz ADG1409 90 pF typ f = 1 MHz

−40°C to

1

+125°C

Unit Test Conditions/Comments

V

= ±10 V, VD = 10 V; see ט Figure 27

S

V

= ±10 V, VD = ט10 V; see Figure 27

S

or VDD

GND

= 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz;

R

L

see Figure 36

Rev. A | Page 3 of 20

ADG1408/ADG1409

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−40°C to

Parameter +25°C

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD 1 μA max 220 μA typ Digital inputs = 5 V 325 μA max ISS 0.002 μA typ Digital inputs = 0 V, 5 V or VDD 1 μA max VDD/VSS ±4.5/±16.5 V min/max

1

Temperature range: Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

+85°C

−40°C to +125°C

1

Unit Test Conditions/Comments

Rev. A | Page 4 of 20

ADG1408/ADG1409

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12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

−40°C to

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 to VDD V On Resistance (RON) 6 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 26 8 9.5 11.2 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match 0.2 Ω typ VS = 0 V to 10 V, IS = −10 mA

Between Channels (ΔRON) 0.82 0.85 1.1 Ω max

On Resistance Flatness (R

) 1.5 Ω typ VS = 0 V to 10 V, IS = −10 mA

FLAT(ON)

2.5 2.5 2.8 Ω max

LEAKAGE CURRENTS VDD = 13.2 V

Source Off Leakage, IS (Off) ±0.04 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27 ±0.2 ±0.6 ±5 nA max Drain Off Leakage, ID (Off) ±0.04 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 27

±0.45 ±1 ±37 nA max

Channel On Leakage, ID, IS (On) ±0.06 nA typ VS = VD = 1 V or 10 V; see Figure 28

±0.44 ±1.3 ±32 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V

2.0 V min

INH

0.8 V max

INL

Input Current ±0.005 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 5 pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANSITION

2

200 ns typ RL = 100 Ω, CL = 35 pF 260 330 380 ns max VS = 8 V; see Figure 29 Break-Before-Make Time Delay, t

90 ns typ RL = 100 Ω, CL = 35 pF

BBM

40 ns min VS1 = VS2 = 8 V; see Figure 30 tON (EN) 160 ns typ RL = 100 Ω, CL = 35 pF 210 250 285 ns max VS = 8 V; see Figure 31 t

(EN) 115 ns typ RL = 100 Ω, CL = 35 pF

OFF

145 180 200 ns max VS = 8 V; see Figure 31

Charge Injection −12 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33 Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 35

ADG1408 36 MHz typ

ADG1409 72 MHz typ Insertion Loss 0.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 CS (Off) 25 pF typ f = 1 MHz CD (Off)

ADG1408 165 pF typ f = 1 MHz

ADG1409 80 pF typ f = 1 MHz CD, CS (On)

ADG1408 200 pF typ f = 1 MHz

ADG1409 120 pF typ f = 1 MHz

−40°C to

1

+125°C

Unit Test Conditions/Comments

or VDD

GND

Rev. A | Page 5 of 20

ADG1408/ADG1409

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−40°C to

Parameter +25°C

POWER REQUIREMENTS VDD = 13.2 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD 1 μA max 220 μA typ Digital inputs = 5 V

335 μA max

VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V

1

Temperature range for Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

+85°C

−40°C to

1

+125°C

Unit Test Conditions/Comments

Rev. A | Page 6 of 20

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5 V DUAL SUPPLY

VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 4.

−40°C to

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range VSS to VDD V On Resistance (RON) 7 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 26 9 10.5 12 Ω max VDD = +4.5 V, VSS = −4.5 V On Resistance Match Between 0.3 Ω typ VS = ±4.5 V, IS = −10 mA

Channels (ΔRON) 0.78 0.91 1.1 Ω max On Resistance Flatness (R

) 1.5 Ω typ VS = ±4.5 V; IS = −10 mA

FLAT(ON)

2.5 2.5 3 Ω max

LEAKAGE CURRENTS VDD = +5.5 V, VSS −5.5 V =

Source Off Leakage, IS (Off) ±0.02 nA typ ±0.2 ±0.6 ±5 nA max Drain Off Leakage, ID (Off) ±0.02 nA typ

±0.45 ±0.8 ±20 nA max

Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = ±4.5 V; see Figure 28

±0.3 ±1.1 ±22 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V

2.0 V min

INH

0.8 V max

INL

Input Current ±0.005 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 5 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

330 ns typ RL = 100 Ω, CL = 35 pF

TRANSITION

440 530 550 ns max VS = 5 V; see Figure 29 Break-Before-Make Time Delay, t

100 ns typ RL = 100 Ω, CL = 35 pF

BBM

50 ns min VS1 = VS2 = 5 V; see Figure 30 tON (EN) 245 ns typ RL = 100 Ω, CL = 35 pF 330 400 440 ns max VS = 5 V; see Figure 31 t

(EN) 215 ns typ RL = 100 Ω, CL = 35 pF

OFF

285 335 370 ns max VS = 5 V; see Figure 31 Charge Injection –10 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation –70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 33 Channel-to-Channel Crosstalk –70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 Total Harmonic Distortion, THD + N 0.06 % typ

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 35

ADG1408 40 MHz typ

ADG1409 80 MHz typ Insertion Loss 0.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 CS (Off) 20 pF typ f = 1 MHz CD (Off)

ADG1408 130 pF typ f = 1 MHz

ADG1409 65 pF typ f = 1 MHz CD, CS (On)

ADG1408 180 pF typ f = 1 MHz

ADG1409 120 pF typ f = 1 MHz

−40°C to

1

+125°C

Unit Test Conditions/Comments

V

= ±4.5 V, VD = 4.5 V; see ט Figure 27

S

V

= ±4.5 V, VD = ט4.5 V; see Figure 27

S

or VDD

GND

= 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;

R

L

see Figure 36

Rev. A | Page 7 of 20

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−40°C to

Parameter +25°C

+85°C

POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max ISS 0.001 μA typ Digital inputs = 0 V, 5 V or VDD 1 μA max VDD/VSS ±4.5/±16.5 V min/max

1

Temperature range for Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

CONTINUOUS CURRENT PER CHANNEL, S OR D

Table 5.

Parameter 25°C 85°C 125°C Unit Test Conditions/Comments

CONTINUOUS CURRENT, S or D

15 V Dual Supply VDD = +13.5 V, VSS = −13.5 V

ADG1408 190 105 50 mA max ADG1409 140 85 45 mA max

12 V Single Supply VDD = 10.8 V, VSS = 0 V

ADG1408 160 95 50 mA max ADG1409 120 75 40 mA max

5 V Dual Supply VDD = +4.5 V, VSS = −4.5 V

ADG1408 155 90 45 mA max ADG1409 115 70 40 mA max

1

Guaranteed by design, not subject to production test.

1

−40°C to

1

+125°C

Unit Test Conditions/Comments

Rev. A | Page 8 of 20

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog Inputs, Digital Inputs

Continuous Current, S or D Tab le 5 data + 10% Peak Current, S or D (Pulsed at 1 ms,

10% Duty Cycle Maximum)

Operating Temperature Range

Industrial (Y Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Reflow Soldering Peak Temperature

(Pb-Free)

1

Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should

be limited to the maximum ratings given.

1

VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first

350 mA

260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating can be applied at any one time.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θ

16-Lead TSSOP 150.4 50 °C/W 16-Lead LFCSP 30.4 °C/W

Unit

JC

ESD CAUTION

Rev. A | Page 9 of 20

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

A0

EN

A1

A2

14

13

15

16

1

A0

2

EN

3

V

SS

ADG1408

TOP VIEW

4

S1

(Not to Scale)

5

S2

6

S3

7

S4

8

DS

Figure 2. ADG1408 Pin Configuration (TSSOP)

16

A1

15

A2

14

GND

13

V

DD

12

S5

11

S6

10

S7

9

8

4861-002

Figure 3. ADG1408 Pin Configuration (LFCSP)

Table 8. ADG1408 Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 A0 Logic Control Input. 2 16 EN

Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches.

3 1 VSS

Most Negative Power Supply Potential. In single supply applications, it can be connected

to ground. 4 2 S1 Source Terminal 1. Can be an input or an output. 5 3 S2 Source Terminal 2. Can be an input or an output. 6 4 S3 Source Terminal 3. Can be an input or an output. 7 5 S4 Source Terminal 4. Can be an input or an output. 8 6 D Drain Terminal. Can be an input or an output. 9 7 S8 Source Terminal 8. Can be an input or an output. 10 8 S7 Source Terminal 7. Can be an input or an output. 11 9 S6 Source Terminal 6. Can be an input or an output. 12 10 S5 Source Terminal 5. Can be an input or an output. 13 11 VDD Most Positive Power Supply Potential. 14 12 GND Ground (0 V) Reference. 15 13 A2 Logic Control Input. 16 14 A1 Logic Control Input. EP Exposed Pad

The exposed pad is connected internally. For increased reliability of the solder joints and

maximum thermal capability, it is recommended that the pad be soldered to the substrate, V

SS

NOTES

1. THE EXPOSED PAD IS CONNECTED INT ERNALLY. F OR INCREASED RELIABI LITY O F THE SOLDER JOI NTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, V

1V

2S1

3S2

4S3

PIN 1 INDICATOR

ADG1408

TOP VIEW

(Not to Scale)

7

5

6

D

S4

S8

12 GND

11 V

DD

10 S5

9S6

8

S7

04861-003

.

SS

.

SS

Table 9. ADG1408 Truth Table

A2 A1 A0 EN On Switch

X X X 0 None 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8

Rev. A | Page 10 of 20

ADG1408/ADG1409

V

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A0

EN

A1

GND

14

13

15

16

1

A0

2

EN

3

V

SS

ADG1409

TOP VIEW

4

S1A

S2A

S3A

S4A

(Not to Scale)

5

6

7

8

DA DB

16

A1

15

GND

14

V

DD

13

S1B

12

S2B

11

S3B

10

S4B

9

4861-004

Figure 4. ADG1409 Pin Configuration (TSSOP)

Table 10. ADG1409 Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 A0 Logic Control Input. 2 16 EN

Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches.

3 1 VSS

Most Negative Power Supply Potential. In single supply applications, it can be connected

to ground. 4 2 S1A Source Terminal 1A. Can be an input or an output. 5 3 S2A Source Terminal 2A. Can be an input or an output. 6 4 S3A Source Terminal 3A. Can be an input or an output. 7 5 S4A Source Terminal 4A. Can be an input or an output. 8 6 DA Drain Terminal A. Can be an input or an output. 9 7 DB Drain Terminal B. Can be an input or an output. 10 8 S4B Source Terminal 4B. Can be an input or an output. 11 9 S3B Source Terminal 3B. Can be an input or an output. 12 10 S2B Source Terminal 2B. Can be an input or an output. 13 11 S1B Source Terminal 1B. Can be an input or an output. 14 12 VDD Most Positive Power Supply Potential. 15 13 GND Ground (0 V) Reference. 16 14 A1 Logic Control Input. EP

Exposed Pad

The exposed pad is connected internally. For increased reliability of the solder joints and maximum

thermal capability, it is recommended that the pad be soldered to the substrate, V

SS

NOTES

1. THE EXPOSED PAD IS CONNECTED INT ERNALLY. F OR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE,

Figure 5. ADG1409 Pin Configuration (LFCSP)

1V

2S1A

3S2A

4S3A

PIN 1 INDICAT OR

ADG1409

TOP VIEW

(Not to Scale)

7

5

6

DA

DB

S4A

8

S4B

12 V

DD

11 S1B

10 S2B

9S3B

04861-005

.

SS

.

SS

Table 11. ADG1409 Truth Table

A1 A0 EN On Switch Pair

X X 0 None 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4

Rev. A | Page 11 of 20

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TYPICAL PERFORMANCE CHARACTERISTICS

6

TA = 25°C

5

4

3

2

ON RESISTANCE (Ω)

VDD = +15V, VSS = –15V V

= +13.5V, VSS = –13.5V

DD

1

V

= +12V, VSS = –12V

DD

V

= +10V, VSS = –10V

DD

V

= +16.5V, VSS = –16.5V

DD

0

–16.5 15.5

–12.5 –8.5 –4.5 –0.5 3.5 7.5 11.5

SOURCE OR DRAIN VO LTAGE (V )

Figure 6. On Resistance vs. VD, VS; Dual Supply

04861-006

7

6

5

4

3

ON RESISTANCE (Ω)

2

TA = +25°C

1

= +85°C

T

A

T

= –40°C

A

= +125°C

T

A

0

–15

–10 –5 0 5 10

SOURCE OR DRAIN VO LTAGE (V)

VDD = +15V V

= –15V

SS

Figure 9. On Resistance vs. VD, VS for Different Temperatures;

15 V Dual Supply

15

04861-008

9

TA = 25°C

8

7

6

5

4

3

ON RESISTANCE (Ω)

2

VDD = +7V, VSS = –7V V

= +5.5V, VSS = –5.5V

1

DD

V

= +5V, VSS = –5V

DD

V

= +4.5V, VSS = –4.5V

DD

0

–7 –4–5–6 7

–3 –2 –1 0 54312 6

SOURCE OR DRAIN VO LTAGE (V )

Figure 7. On Resistance vs. VD, VS; Dual Supply

13

12

11

10

9

8

7

6

5

4

ON RESISTANCE (Ω)

3

VDD = 12V

= 13.2V

V

DD

2

= 10.8V

V

DD

= 8V

V

1

DD

= 5V

V

DD

0

12345678910111213

SOURCE OR DRAIN VO LTAGE (V )

Figure 8. On Resistance vs. VD, VS; Single Supply

TA = 25°C V

= 0V

SS

12

10

8

6

4

ON RESISTANCE (Ω)

TA = +25°C

2

= +85°C

T

A

= –40°C

T

A

= +125°C

T

A

0

–5

–4 –3 –2 –1 0 1 2 3 4

04861-036

SOURCE OR DRAIN VO LTAGE (V )

VDD = +5V

= –5V

V

SS

5

04861-009

Figure 10. On Resistance vs. VD, VS for Different Temperatures;

5 V Dual Supply

10

9

8

7

6

5

4

ON RESISTANCE (Ω)

3

2

TA = +25°C

= +85°C

T

A

1

= –40°C

T

A

= +125°C

T

A

0

04861-007

246810

SOURCE OR DRAIN VO LTAGE (V)

VDD = 12V V

= 0V

SS

12

04861-010

Figure 11. On Resistance vs. VD, VS for Different Temperatures;

12 V Single Supply

Rev. A | Page 12 of 20

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1.0 IS (OFF) +–

(OFF) +–

I

D

0.8

(OFF) –+

I

S

I

(OFF) –+

D

0.6

0.4

0.2

0

–0.2

–0.4

LEAKAGE CURRENT ( nA)

–0.6

–0.8

–1.0

(ON) ++

I

D,IS

I

(ON) ––

D,IS

0

10 20 30 40 50 60 70

TEMPERATURE (°C)

VDD = +15V V

= –15V

SS

= +10V/–10V

V

BIAS

80

04861-011

Figure 12. Leakage Current vs. Temperature;

15 V Dual Supply

18

IS (OFF) +–

(OFF) +–

I

D

16

(OFF) –+

I

S

I

(OFF) –+

D

14

12

10

8

6

4

LEAKAGE CURRENT ( nA)

2

0

–2

(ON) ++

I

D,IS

I

(ON) ––

D,IS

0

20 40 60 80 100

TEMPERATURE (°C)

VDD = 12V V

= 0V

SS

= 1V/10V

V

BIAS

120

04861-013

Figure 15. Leakage Current vs. Temperature;

12 V Single Supply

14

IS (OFF) +–

(OFF) +–

I

D

12

I

(OFF) –+

S

(OFF) –+

I

D

10

8

6

4

2

LEAKAGE CURRENT ( nA)

0

–2

–4

(ON) ++

I

D,IS

I

(ON) ––

D,IS

0

20 40 60 80 100

TEMPERATURE (°C)

VDD = +15V

= –15V

V

SS

V

= +10V/–10V

BIAS

120

04861-012

Figure 13. Leakage Current vs. Temperature;

70

60

50

40

(µA)

DD

I

30

20

10

0

01

VDD = +12V V

= 0V

SS

VDD = +5V V

= –5V

SS

2 4 6 8 10 12

LOGIC, AX (V)

IDD PER CHANNEL

= 25°C

T

A

VDD = +15V V

= –15V

SS

4

04861-034

Figure 16. Positive Supply Current vs. Logic Level

15 V Dual Supply

10

IS (OFF) +–

(OFF) +–

I

9

D

(OFF) –+

I

S

(OFF) –+

I

8

D

(ON) ++

I

D,IS

7

6

5

4

3

2

LEAKAGE CURRENT ( nA)

1

0

–1

(ON) ––

I

D,IS

0

20 40 60 80 100

TEMPERATURE (°C)

VDD = +5V

= –5V

V

SS

V

= +4.5V/–4. 5V

BIAS

120

04861-015

Figure 14. Leakage Current vs. Temperature;

200

TA = 25°C

150

100

50

0

–50

CHARGE INJECTI ON (pC)

–100

–150

–200

–15 15

VDD = +5V V

= –5V

SS

VDD = +15V V

= –15V

SS

–10 –5 0 5 10

V

(V)

S

VDD = +12V V

SS

= 0V

Figure 17. Charge Injection vs. Source Voltage

04861-014

5 V Dual Supply

Rev. A | Page 13 of 20

ADG1408/ADG1409

www.BDTIC.com/ADI

450

400

350

300

250

200

TIME (ns)

150

100

50

0

–40 120

–20 0 20 40 60 80 100

VDD = +5V V

= –5V

SS

TEMPERATURE (°C)

VDD = 12V V

= 0V

SS

VDD = +15V V

= –15V

SS

Figure 18. Transition Time vs. Temperature

04861-033

0

VDD = +15V V

= –15V

–10

SS

T

= 25°C

A

–20

–30

–40

–50

–60

–70

CROSSTALK (d B)

–80

–90

–100

–110

1k 1G

10k 100k 1M 10M 100M

ADJACENT

CHANNEL

FREQUENCY (Hz)

NONADJACENT CHANNEL

Figure 21. ADG1409 Crosstalk vs. Frequency

04861-018

0

VDD = +15V V

= –15V

–10

SS

T

= 25°C

A

–20

–30

–40

–50

–60

–70

OFF ISO LATIO N (dB)

–80

–90

–100

–110

1k 1G

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 19. Off Isolation vs. Frequency

0

VDD = +15V V

= –15V

–10

SS

T

= 25°C

A

–20

–30

–40

–50

–60

–70

CROSSTALK (d B)

–80

–90

–100

–110

1k 1G

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 20. ADG1408 Crosstalk vs. Frequency

0

–0.5

–1.0

–1.5

–2.0

–2.5

BANDWIDTH (dB)

–3.0

VDD = +15V

–3.5

V

= –15V

SS

T

= 25°C

A

–4.0

100 100M

04861-016

1k 10k 100k 1M 10M

FREQUENCY (Hz)

04861-019

Figure 22. ADG1408 On Response vs. Frequency

0

–0.5

–1.0

–1.5

–2.0

–2.5

BANDWIDTH (dB)

–3.0

VDD = +15V

–3.5

V

= –15V

SS

T

= 25°C

A

–4.0

100 1G100M

1k 10k 100k 1M 10M

04861-017

FREQUENCY (Hz)

04861-031

Figure 23. ADG1409 On Response vs. Frequency

Rev. A | Page 14 of 20

ADG1408/ADG1409

www.BDTIC.com/ADI

0.10

LOAD = 110Ω T

= 25°C

0.09

A

0.08

0.07

0.06

0.05

0.04

THD + N (%)

0.03

0.02

0.01

0

10 100k

VDD = +5V, VSS = –5V, VS = +5V p-p

VDD = +15V, VSS = –15V, VS = +15V p-p

100 1k 10k

FREQUENCY (Hz)

Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency

0

VDD = +15V

–10

= –15V

V

SS

T

= 25°C

A

–20

V p-p = 0. 63V

–30

–40

–50

–60

ACPSRR (dB)

–70

–80

–90

–100

–110

100 1k 10M

04861-032

NO DECOUPLING

CAPACITORS

10k 100k 1M

FREQUENCY (Hz)

DECOUPLING CAPACITORS ON SUPPLIES

04861-035

Figure 25. AC Power Supply Rejection Ratio vs. Frequency

Rev. A | Page 15 of 20

ADG1408/ADG1409

www.BDTIC.com/ADI

TERMINOLOGY

RON

Ohmic resistance between D and S.

ΔR

ON

Difference between the R

FLAT(ON)

R

of any two channels.

ON

Flatness is defined as the difference between the maximum and minimum value of on resistance as measured.

I

(Off)

S

Source leakage current when the switch is off.

I

(Off)

D

Drain leakage current when the switch is off.

I

, IS (On)

D

Channel leakage current when the switch is on.

V

(VS)

D

Analog voltage on Terminal D and Terminal S.

C

(Off)

S

Channel input capacitance for off condition.

C

(Off)

D

Channel output capacitance for off condition.

C

, CS (On)

D

On switch capacitance.

C

IN

Digital input capacitance.

t

(EN)

ON

Delay time between the 50% and 90% points of the digital input and switch on condition.

t

(EN)

OFF

Delay time between the 50% and 90% points of the digital input and switch off condition.

t

TRANSITION

Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another.

t

BBM

Off time measured between the 80% point of both switches when switching from one address state to another.

V

INL

Maximum input voltage for Logic 0.

V

INH

Minimum input voltage for Logic 1.

I

, I

INL

INH

Input current of the digital input.

I

DD

Positive supply current.

I

SS

Negative supply current.

Off Isolation

A measure of unwanted signal coupling through an off channel.

Charge Injection

A measure of the glitch impulse transferred from the digital input to the analog output during switching.

Bandwidth

Frequency at which the output is attenuated by 3 dB.

On Response

Frequency response of the on switch.

Total Harmonic Distortion Plus Noise (THD + N)

Ratio of the harmonic amplitude plus noise of the signal to the fundamental.

AC Power Supply Rejection Ratio (ACPSRR)

A measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.

Rev. A | Page 16 of 20

ADG1408/ADG1409

V

VDDV

A

VDDV

www.BDTIC.com/ADI

TEST CIRCUITS

V

35pF

ID(ON)

A

V

D

04861-022

IS(OFF) ID(OFF)

SD

I

S

DS

04861-020

S

Figure 26. On Resistance

SD

A A

Figure 27. Off Leakage

SD

NC

V

D

04861-021

NC = NO CONNECT

Figure 28. On Leakage

SS

3V

ADDRESS DRIVE (V

0V

t

TRANSITION

OUTPUT

)

IN

50% 50%

90%

t

< 20ns

r

t

< 20ns

f

t

TRANSITI ON

90%

V

DDVSS

A0

V

IN

50Ω

A1

A2

ADG1408

2.4V EN

GND

S2 TO S7

1

S1

S8

D

OUTPUT

100Ω

V

S1

V

S8

1

DDRESS

DRIVE (V

OUTPUT

SIMILAR CONNECTIO N FOR ADG1409.

Figure 29. Address to Output Switching Times, t

3V

)

IN

0V

80% 80%

t

BBM

Figure 30. Break-Before-Make Delay, t

V

IN

50Ω

2.4V EN

1

SIMILAR CO NNECTION F OR ADG1409.

BBM

TRANSITION

A0

A1

A2

V

DDVSS

S2 TO S7

ADG1408

GND

SS

S1

S8

1

OUTPUT

D

100Ω

V

S

35pF

04861-023

04861-024

SS

3V

ENABLE DRIVE (V

0V

)

IN

50% 50%

V

DD

SS

A0

A1

A2

S1

S2 TO S8

V

S

t

0.9V

OFF

(EN)

O

OUTPUT

t

(EN)

ON

0.9V

O

Figure 31. Enable Delay, t

Rev. A | Page 17 of 20

GND

1

OUTPUT

D

100Ω

35pF

04861-025

ADG1408

EN

V

IN

ON

50Ω

1

SIMILAR CONNECTIO N FOR ADG1409.

(EN), t

(EN)

OFF

ADG1408/ADG1409

VINV

VDDV

V

www.BDTIC.com/ADI

SS

V

DD

GND

SS

1

DS

C 1nF

V

OUT

L

04861-026

OUT

3V

A0

A1

A2

ADG1408

R

S

V

S

EN

V

IN

1

SIMILAR CO NNECTION F OR ADG1409.

Q

INJ

= CL × ΔV

OUT

ΔV

OUT

Figure 32. Charge Injection

V

0.1µF

DD

V

SS

0.1µF

V

DD

S

GND

SS

50Ω

D

OFF ISOLATION = 20 log

NETWORK

ANALYZER

50Ω

V

OUT

R

L

50Ω

S

V

OUT

V

04861-027

S

0.1µF

Figure 33. Off Isolation

V

DD

SS

0.1µF

V

DD

SS

S

D

GND

INSERTION LOSS = 20 log

NETWORK

ANALYZER

50Ω

V

R

L

50Ω

WITH SWITCH

V

OUT

WITHOUT SWITCH

V

OUT

V

S

04861-029

Figure 35. Insertion Loss

DD

0.1µF

NETWO RK

ANALYZER

V

OUT

R

L

50Ω

V

S

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

V

DD

S1

S2

Figure 34. Channel-to-Channel Crosstalk

GND

SS

0.1µF

V

SS

D

R 50Ω

V

OUT

V

S

04861-028

DD

0.1µF

V

IN

SS

0.1µF

V

DD

SS

S

D

GND

AUDIO PRECISIO N

R

L

10kΩ

R

S

V

S

V p-p

V

OUT

04861-030

Figure 36. THD + Noise

Rev. A | Page 18 of 20

ADG1408/ADG1409

C

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

4.50

4.40

4.30

9

6.40

BSC

81

PIN 1

1.20

0.30

0.19

MAX

SEATING PLANE

0.20

0.09 8°

0°

0.75

0.60

0.45

0.15

0.05

0.65

BSC

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.50

0.40

0.30

1

16

PA D

4

5

FOR PROPER CO NNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DESCRI PTIONS SECTION O F THIS DATA SHEET.

N

P

I

D

N

I

2.65

2.50 SQ

2.35

0.25 MIN

1

R

O

C

I

A

T

031006-A

INDI

SEATING

PIN 1

ATO R

1.00

0.85

0.80

PLANE

12° MAX

4.00

BSC SQ

3.75

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.05 MAX

0.30

0.23

0.18

COMPLIANTTOJEDEC STANDARDS MO-220-VGGC.

0.02 NOM

0.20 REF

0.60 MAX

12

0.65

9

BSC

1.95 BCS

COPLANARIT Y

0.08

13

EXPOSED

8

BOTTOM VIEW

Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm, Very Thin Quad (CP-16-13)

Dimensions shown in millimeters

Rev. A | Page 19 of 20

ADG1408/ADG1409

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1408YRUZ ADG1408YRUZ-REEL ADG1408YRUZ-REEL71 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1408YCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13 ADG1409YRUZ1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1409YRUZ-REEL1 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1409YRUZ-REEL71 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 ADG1409YCPZ-REEL71 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-13

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

1

−40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

Rev. A | Page 20 of 20

ANALOG DEVICES ADG1408, ADG1409 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

15 V DUAL SUPPLY

12 V SINGLE SUPPLY

5 V DUAL SUPPLY

CONTINUOUS CURRENT PER CHANNEL, S OR D

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

TEST CIRCUITS

OUTLINE DIMENSIONS

ORDERING GUIDE