Datasheet ADG1406, ADG1407 Datasheet (ANALOG DEVICES)

9.5 Ω RON, 16-Channel, Differential 8-Channel,

S

±15 V/+12 V/±5 V iCMOS Multiplexers

FEATURES

9.5 Ω on resistance @ 25°C Up to 300 mA of continuous current Fully specified at ±15 V/+12 V/±5 V 3 V logic-compatible inputs Rail-to-rail operation Break-before-make switching action 28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP_VQ

APPLICATIONS

Medical equipment Audio and video routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Communication systems

GENERAL DESCRIPTION

The ADG1406 and ADG1407 are monolithic iCMOS® analog multiplexers comprising 16 single channels and eight differential channels, respectively. The ADG1406 switches one of 16 inputs to a common output, as determined by the 4-bit binary address lines (A0, A1, A2, and A3). The ADG1407 switches one of eight differential inputs to a common differential output, as determined by the 3-bit binary address lines (A0, A1, and A2). An EN input on both devices enables or disables the device. When disabled, all channels switch off. When on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies.

The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.

The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADG1406/ADG1407

FUNCTIONAL BLOCK DIAGRAMS

ADG1406

S1

D

16

1-OF-16

DECODER

A0 A1 A2 A3 EN

Figure 1.

ADG1407

S1A

S8A

S1B

S8B

1-OF-8

DECODER

A0 A1 A2 EN

Figure 2.

Table 1. Related Devices

Part No. Description

ADG1206/ADG1207

Low capacitance, low charge injection, and low leakage 8-/16-channel ±15 V multiplexers

DA

DB

07419-001

07419-002

ADG1406/ADG1407

REVISION HISTORY

3/09—Rev. 0 to Rev. A

Change to I Change to I

Changes to Figure 16 ...................................................................... 14

8/08—Revision 0: Initial Version

Parameter, Table 2 ................................................... 4

DD

Parameter, Table 3 ................................................... 5

DD

Absolute Maximum Ratings ............................................................8

Thermal Resistance .......................................................................8

ESD Caution...................................................................................8

Pin Configurations and Function Descriptions ............................9

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 17

Test Circuits ..................................................................................... 18

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

Rev. A | Page 2 of 20

ADG1406/ADG1407

SPECIFICATIONS

±15 V DUAL SUPPLY

VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted.1

Table 2.

−40°C to

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range VSS to VDD V On Resistance (RON) 9.5 Ω typ VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V,

11.5 14 16 Ω max IS = −10 mA; see Figure 27 On-Resistance Match Between 0.55 Ω typ VDD = +13.5 V, VSS = −13.5 V , VS = ±10 V, IS =

Channels (ΔRON) 1 1.5 1.7 Ω max −10 mA

On-Resistance Flatness (R

) 1.6 Ω typ VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V, IS =

FLAT(ON)

1.9 2.15 2.3 Ω max −10 mA

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.01 nA typ

±0.25 ±1 ±4 nA max Drain Off Leakage, ID (Off) ±0.01 nA typ

±0.5 ±3 ±20 nA max Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = ±10 V; see Figure 29 ±0.5 ±3 ±20 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V

2.0 V min

INH

0.8 V max

INL

Input Current ±0.002 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

105 ns typ RL = 100 Ω, CL = 35 pF

TRANSITION

160 200 225 ns max VS = 10 V, see Figure 30 Break-Before-Make Time Delay, t

40 ns typ RL = 100 Ω, CL = 35 pF

BBM

10 ns min VS1 = VS2 = 10 V; see Figure 31 tON (EN) 83 ns typ RL = 100 Ω, CL = 35 pF 110 140 155 ns max VS = 10 V; see Figure 32 t

(EN) 98 ns typ RL = 100 Ω, CL = 35 pF

OFF

120 145 165 ns max VS = 10 V; see Figure 32 Charge Injection 10 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation −73 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 Total Harmonic Distortion (THD + N) 0.07 % typ

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 36 ADG1406 60 MHz typ ADG1407 110 MHz typ

Insertion Loss 0.6 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 36 CS (Off) 8 pF typ f = 1 MHz CD (Off)

ADG1406 90 pF typ f = 1 MHz ADG1407 45 pF typ f = 1 MHz

−40°C to +125°C

1

Unit Test Conditions/Comments

VS = ±10 V, VD = ∓10 V; see Figure 28

or VDD

GND

= 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz; see

R

L

Figure 37

Rev. A | Page 3 of 20

ADG1406/ADG1407

−40°C to

Parameter +25°C

+85°C

CD, CS (On)

ADG1406 115 pF typ f = 1 MHz ADG1407 70 pF typ f = 1 MHz

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 280 μA typ Digital inputs = 5 V 475 μA max ISS 0.002 μA typ Digital inputs = 0 V, 5 V or VDD 1 μA max VDD/VSS ±4.5/±16.5 V min/max

1

Temperature range for B version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

−40°C to

Parameter +25°C

ANALOG SWITCH

Analog Signal Range 0 to VDD V On Resistance (RON) 18 Ω typ VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,

21.5 26 28.5 Ω max IS = −10 mA; see Figure 27 On-Resistance Match Between 0.55 Ω typ VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,

Channels (ΔRON) 1.2 1.6 1.8 Ω max IS = −10 mA

On-Resistance Flatness (R

) 5 Ω typ VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,

FLAT(ON)

6 6.9 7.3 Ω max IS = −10 mA

LEAKAGE CURRENTS VDD = 10.8 V

Source Off Leakage, IS (Off) ±0.01 nA typ

±0.25 ±1 ±4 nA max Drain Off Leakage, ID (Off) ±0.01 nA typ

±0.5 ±3 ±20 nA max

Channel On Leakage, ID, IS (On) ±0.01 nA typ VS = VD = 1 V or 10 V; see Figure 29

±0.5 ±3 ±20 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V

2.0 V min

INH

0.8 V max

INL

Input Current ±0.002 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 4 pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANSITION

2

170 ns typ RL = 100 Ω, CL = 35 pF 250 310 350 ns max VS = 8 V; see Figure 29 Break-Before-Make Time Delay, t

75 ns typ RL = 100 Ω, CL = 35 pF

BBM

30 ns min VS1 = VS2 = 8 V; see Figure 31

+85°C

−40°C to +125°C

1

Unit Test Conditions/Comments

1

Unit Test Conditions/Comments

= 1 V/10 V, VD = 10 V/1 V; see

V

S

Figure 28

V Figure 28

= 1 V/10 V, VD = 10 V/1 V; see

S

or VDD

GND

Rev. A | Page 4 of 20

ADG1406/ADG1407

−40°C to

Parameter +25°C

+85°C

tON (EN) 145 ns typ RL = 100 Ω, CL = 35 pF 205 250 285 ns max VS = 8 V; see Figure 31 t

(EN) 112 ns typ RL = 100 Ω, CL = 35 pF

OFF

150 175 200 ns max VS = 8 V; see Figure 31

Charge Injection

10 pC typ

Off Isolation −73 dB typ

Channel-to-Channel Crosstalk −70 dB typ

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 36 ADG1406 35 MHz typ ADG1407 70 MHz typ

Insertion Loss 0.6 dB typ

CS (Off) 12 pF typ f = 1 MHz CD (Off)

ADG1406 145 pF typ f = 1 MHz ADG1407 72 pF typ f = 1 MHz

CD, CS (On)

ADG1406 166 pF typ f = 1 MHz ADG1407 93 pF typ f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 150 μA typ Digital inputs = 5 V

475 μA max

VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V

1

Temperature range for B version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

−40°C to +125°C

1

Unit Test Conditions/Comments

= 6 V, RS = 0 Ω, CL = 1 nF; see

V

S

Figure 33 R

see Figure 34 R

see Figure 35

R see Figure 36

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

Rev. A | Page 5 of 20

ADG1406/ADG1407

±5 V DUAL SUPPLY

VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 4.

−40°C to

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range VSS to VDD V On Resistance (RON) 21 Ω typ VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V, 25 29 32 Ω max IS = −10 mA; see Figure 27 On -Resistance Match Between 0.6 Ω typ VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5V,

Channels (ΔRON) 1.3 1.7 1.9 Ω max IS = −10 mA

On -Resistance Flatness (R

) 5.2 Ω typ VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V;

FLAT(ON)

6.4 7.3 7.6 Ω max IS = −10 mA

LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V

Source Off Leakage, IS (Off) ±0.01 nA typ

±0.25 ±1 ±4 nA max Drain Off Leakage, ID (Off) ±0.01 nA typ

±0.5 ±3 ±20 nA max

Channel On Leakage, ID, IS (On) ±0.01 nA typ VS = VD = ±4.5 V; see Figure 29

±0.5 ±3 ±20 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V

2.0 V min

INH

0.8 V max

INL

Input Current ±0.002 μA typ VIN = V ±0.1 μA max Digital Input Capacitance, CIN 3.5 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

260 ns typ RL = 100 Ω, CL = 35 pF

TRANSITION

435 510 565 ns max VS = 5 V; see Figure 30 Break-Before-Make Time Delay, t

90 ns typ RL = 100 Ω, CL = 35 pF

BBM

30 ns min VS1 = VS2 = 5 V; see Figure 31 tON (EN) 230 ns typ RL = 100 Ω, CL = 35 pF 335 400 445 ns max VS = 5 V; see Figure 32 t

(EN) 205 ns typ RL = 100 Ω, CL = 35 pF

OFF

290 340 370 ns max VS = 5 V; see Figure 32 Charge Injection 10 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33 Off Isolation –73 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 Channel-to-Channel Crosstalk –70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 Total Harmonic Distortion, THD + N 0.18 % typ

−3 dB Bandwidth RL = 50 Ω, CL = 5 pF; see Figure 36 ADG1406 40 MHz typ ADG1407 80 MHz typ

Insertion Loss 1.15 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 36 CS (Off) 10 pF typ f = 1 MHz CD (Off)

ADG1406 123 pF typ f = 1 MHz ADG1407 62 pF typ f = 1 MHz

CD, CS (On)

ADG1406 148 pF typ f = 1 MHz ADG1407 88 pF typ f = 1 MHz

−40°C to +125°C

1

Unit Test Conditions/Comments

VS = ±4.5 V, VD = ∓4.5 V; see Figure 28

or VDD

GND

= 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see

R

L

Figure 37

Rev. A | Page 6 of 20

ADG1406/ADG1407

−40°C to

Parameter +25°C

+85°C

POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD 1 μA max ISS 0.002 μA typ Digital inputs = 0 V, 5 V, or VDD 1 μA max VDD/VSS ±4.5/±16.5 V min/max

1

Temperature range for B version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

CONTINUOUS CURRENT PER CHANNEL

Table 5. ADG1406

Parameter 25°C 85°C 125°C Unit Test Conditions/Comments

CONTINUOUS CURRENT PER CHANNEL

15 V Dual Supply VDD = +13.5 V, VSS = −13.5 V

28-Lead TSSOP 180 100 50 mA max 32-Lead LFCSP 300 150 60 mA max

12 V Single Supply VDD = 10.8 V, VSS = 0 V

28-Lead TSSOP 150 90 50 mA max 32-Lead LFCSP 260 130 55 mA max

5 V Dual Supply VDD = +4.5 V, VSS = −4.5 V

28-Lead TSSOP 140 85 45 mA max 32-Lead LFCSP 245 130 55 mA max

1

Guaranteed by design, not subject to production test.

1

−40°C to +125°C

1

Unit Test Conditions/Comments

Table 6. ADG1407

Parameter 25°C 85°C 125°C Unit Test Conditions/Comments

CONTINUOUS CURRENT PER CHANNEL

1

15 V Dual Supply VDD = +13.5 V, VSS = −13.5 V

28-Lead TSSOP 135 85 45 mA max 32-Lead LFCSP 235 125 55 mA max

12 V Single Supply VDD = 10.8 V, VSS = 0 V

28-Lead TSSOP 110 70 40 mA max 32-Lead LFCSP 190 110 50 mA max

5 V Dual Supply VDD = +4.5 V, VSS = −4.5 V

28-Lead TSSOP 105 65 40 mA max 32-Lead LFCSP 180 100 50 mA max

1

Guaranteed by design, not subject to production test.

Rev. A | Page 7 of 20

ADG1406/ADG1407

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 7.

Parameter Rating

V

to VSS 35 V

DD

VDD to GND −0.3 V to +25 V V

to GND +0.3 V to −25 V

SS

Analog, Digital Inputs1

Continuous Current, Sx or Dx Pins

Peak Current, Sx or Dx Pins (Pulsed

at 1 ms, 10% Duty Cycle Maximum)

28-Lead TSSOP 300 mA 32-Lead LFCSP_VQ 550 mA

Operating Temperature Range

Industrial (B Version) –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C Reflow Soldering, Pb-Free

Peak Temperature 260 (+0/−5)°C

Time at Peak Temperature 10 sec to 40 sec

1

Overvoltages at the Ax, EN, Sx, or Dx pins are clamped by internal diodes.

Limit current to the maximum ratings given.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating may be applied at any one time.

− 0.3 V to VDD + 0.3 V

V

SS

or 30 mA, whichever occurs first

Table 5 and Tab l e 6 specifications + 15%

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 8. Thermal Resistance

Package Type θJA θ

28-Lead TSSOP 97.9 14 °C/W 32-Lead LFCSP_VQ 27.27 °C/W

Unit

JC

ESD CAUTION

Rev. A | Page 8 of 20

ADG1406/ADG1407

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

C

V

NC

S16

S15

S14

S13

S12

S11

S10

GND

NC

DD

S9

A3

1

2

3

4

5

6

ADG1406

7

(Not to Scale)

8

9

10

11

12

13

14

TOP VIEW

DD

NC

V

1S16 2S15 3S14 4S13 5S12 6S11 7S10 8S9

NC

30

31

32

PIN 1 INDICAT OR

ADG1406

TOP VIEW

(Not to Scale)

9

11

10

A3

A2

GND

28

D

27

V

SS

26

S8

25

S7

24

S6

23

S5

22

S4

21

S3

20

S2

19

S1

18

EN

17

A0

16

A1

15

A2

NOTES

1. NC = NO CONNECT .

2. EXPOSED PAD TIED TO SUBSTRATE, V

SS

N

NC

V

D

28

27

26

25

29

24 S8 23 S7 22 S6 21 S5 20 S4 19 S3 18 S2 17 S1

12

13

14

15

16

A1

A0

EN

NC

07419-004

.

SS

NC = NO CONNECT

Figure 3. ADG1406 TSSOP Pin Configuration

07419-003

Figure 4. ADG1406 LFCSP Pin Configuration

Table 9. ADG1406 Pin Function Descriptions

Pin No.

TSSOP LFCSP_VQ Mnemonic Description

1 31 VDD Most Positive Power Supply Potential. 2, 3, 13

12, 13, 26,

NC No Connect.

27, 28, 30, 32 4 1 S16 Source Terminal 16. This pin can be an input or an output. 5 2 S15 Source Terminal 15. This pin can be an input or an output. 6 3 S14 Source Terminal 14. This pin can be an input or an output. 7 4 S13 Source Terminal 13. This pin can be an input or an output. 8 5 S12 Source Terminal 12. This pin can be an input or an output. 9 6 S11 Source Terminal 11. This pin can be an input or an output. 10 7 S10 Source Terminal 10. This pin can be an input or an output. 11 8 S9 Source Terminal 9. This pin can be an input or an output. 12 9 GND Ground (0 V) Reference. 14 10 A3 Logic Control Input. 15 11 A2 Logic Control Input. 16 14 A1 Logic Control Input. 17 15 A0 Logic Control Input. 18 16 EN

Active High Digital Input. When this pin is low, the device is disabled and all switches are

turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 17 S1 Source Terminal 1. This pin can be an input or an output. 20 18 S2 Source Terminal 2. This pin can be an input or an output. 21 19 S3 Source Terminal 3. This pin can be an input or an output. 22 20 S4 Source Terminal 4. This pin can be an input or an output. 23 21 S5 Source Terminal 5. This pin can be an input or an output. 24 22 S6 Source Terminal 6. This pin can be an input or an output. 25 23 S7 Source Terminal 7. This pin can be an input or an output. 26 24 S8 Source Terminal 8. This pin can be an input or an output. 27 25 VSS

Most Negative Power Supply Potential. In single-supply applications, this pin can be

connected to ground. The exposed pad is tied to the substrate, V 28 29 D Drain Terminal. This pin can be an input or an output.

.

SS

Rev. A | Page 9 of 20

ADG1406/ADG1407

Table 10. ADG1406 Truth Table

A3 A2 A1 A0 EN On Switch

X X X X 0 None 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16

Rev. A | Page 10 of 20

ADG1406/ADG1407

V

DB

NC

S8B

S7B

S6B

S5B

S4B

S3B

S2B

S1B

GND

NC

DD

1

2

3

4

5

6

ADG1407

7

(Not to Scale)

8

9

10

11

12

13

14

TOP VIEW

DD

NC

V

1S8B 2S7B 3S6B 4S5B 5S4B 6S3B 7S2B 8S1B

DB

29

31

30

32

PIN 1 INDICATO R

ADG1407

TOP VIEW

(Not to Scale)

9

11

10

12

A2

NC

GND

28

DA

27

V

SS

26

S8A

25

S7A

24

S6A

23

S5A

22

S4A

21

S3A

20

S2A

19

S1A

18

EN

17

A0

16

A1

15

A2

NOTES

1. NC = NO CONNECT.

2. EXPOSED PAD TIED TO SUBSTRATE, V

SS

NC

DA

NC

V

25

28

27

26

24 S8A 23 S7A 22 S6A 21 S5A 20 S4A 19 S3A 18 S2A 17 S1A

13

14

15

16

A1

A0

EN

NC

07419-037

.

SS

NC = NO CONNECT

Figure 5. ADG1407 TSSOP Pin Configuration

07419-036

Figure 6. ADG1407 LFCSP_VQ Pin Configuration

Table 11. ADG1407 Pin Function Descriptions

Pin No.

TSSOP LFCSP_VQ Mnemonic Description

1 29 VDD Most Positive Power Supply Potential. 2 31 DB Drain Terminal B. This pin can be an input or an output. 3, 13, 14

11, 12, 13, 26,

NC No Connect.

28, 30, 32 4 1 S8B Source Terminal 8B. This pin can be an input or an output. 5 2 S7B Source Terminal 7B. This pin can be an input or an output. 6 3 S6B Source Terminal 6B. This pin can be an input or an output. 7 4 S5B Source Terminal 5B. This pin can be an input or an output. 8 5 S4B Source Terminal 4B. This pin can be an input or an output. 9 6 S3B Source Terminal 3B. This pin can be an input or an output. 10 7 S2B Source Terminal 2B. This pin can be an input or an output. 11 8 S1B Source Terminal 1B. This pin can be an input or an output. 12 9 GND Ground (0 V) Reference. 15 10 A2 Logic Control Input. 16 14 A1 Logic Control Input. 17 15 A0 Logic Control Input. 18 16 EN

Active High Digital Input. When this pin is low, the device is disabled and all switches are

turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 17 S1A Source Terminal 1A. This pin can be an input or an output. 20 18 S2A Source Terminal 2A. This pin can be an input or an output. 21 19 S3A Source Terminal 3A. This pin can be an input or an output. 22 20 S4A Source Terminal 4A. This pin can be an input or an output. 23 21 S5A Source Terminal 5A. This pin can be an input or an output. 24 22 S6A Source Terminal 6A. This pin can be an input or an output. 25 23 S7A Source Terminal 7A. This pin can be an input or an output. 26 24 S8A Source Terminal 8A. This pin can be an input or an output. 27 25 VSS

Most Negative Power Supply Potential. In single-supply applications, this pin can be

connected to ground. The exposed pad is tied to the substrate, V 28 27 DA Drain Terminal A. This pin can be an input or an output.

.

SS

Rev. A | Page 11 of 20

ADG1406/ADG1407

Table 12. ADG1407 Truth Table

A2 A1 A0 EN On Switch Pair

X X X 0 None 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8

Rev. A | Page 12 of 20

ADG1406/ADG1407

TYPICAL PERFORMANCE CHARACTERISTICS

16

14

12

10

VDD = +10V V

= –10V

SS

VDD = +12V V

= –12V

SS

VDD = +13.5V V

= –13.5V

SS

18

15

12

TA = +125°C

8

6

ON RESISTANCE (Ω)

4

2

TA = 25°C I

= –10mA

S

0

–16.5 –13.5 –4.5 4.5 16.5

–10.5 –1.5 7.5–7.5 1.5 10.5 13.5

VDD = +15V V

= –15V

SS

VS, VD (V)

VDD = +16.5V V

= –16.5V

SS

Figure 7. On Resistance as a Function of VD (VS), Dual Supply

35

30

25

20

15

ON RESISTANCE (Ω)

10

5

TA = 25°C I

= –10mA

S

0

–7 –1 7

Figure 8. On Resistance as a Function of V

40

35

30

25

20

15

ON RESISTANCE (Ω)

10

5

T

A

I

= –10mA

S

0

VDD = +3.V V

= –3.V

SS

VDD = +4.5V V

= –4.5V

SS

VDD = +5.0V V

= –5.0V

SS

VDD = +7V V

= –7V

SS

–5 1–3 3 5

= 25°C

1.50

3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5

VS, VD (V)

VDD = +5V V

= 0V

SS

VDD = +10.8V V

SS

VDD = +15V V

SS

VS, VD (V)

= 0V

(Vs), Dual Supply

D

VDD = +8V V

= 0V

SS

VDD = +12V V

SS

VDD = +13.2V V

VDD = +5.5V V

= –5.5V

SS

= 0V

SS

Figure 9. On Resistance as a Function of VD (VS), Single Supply

15.0

9

6

ON RESISTANCE (Ω)

3

VDD = +15V V

= –15V

07419-006

SS

0 –15 –10 –5 0 5 10 15

TA = +85°C

TA = +25°C

TA = –40°C

07419-009

VS, VD (V)

Figure 10. On Resistance as a Function of VD (VS)

for Different Temperatures, 15 V Dual Supply

30

25

20

15

10

ON RESISTANCE (Ω)

5

VDD = +5V V

= –5V

07419-007

SS

0

–5 –3–4 –2 0–1 3214

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

VS, VD (V)

07419-010

5

Figure 11. On Resistance as a Function of VD (VS)

for Different Temperatures, 5 V Dual Supply

25

20

15

10

ON RESISTANCE (Ω)

5

VDD = +12V V

= 0V

SS

07419-008

0

01108642

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

VS, VD (V)

07419-011

2

Figure 12. On Resistance as a Function of VD (VS)

for Different Temperatures, 12 V Single Supply

Rev. A | Page 13 of 20

ADG1406/ADG1407

1.0

VDD = +15V

0.8 V

= –15V

SS

V

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

LEAKAGE CURRENT (n A)

–0.8

–1.0

–1.2

–1.4

01020304050

Figure 13. Leakage Current as a Function of Temperature (up to 85°C),

8

6

4

2

0

–2

–4

LEAKAGE CURRENT (n A)

–6

–8

–10

0

Figure 14. Leakage Current as a Function of Temperature,

7

6

5

4

3

2

1

0

–1

LEAKAGE CURRENT (n A)

–2

–3

–4

0

Figure 15. Leakage Current as a Function of Temperature,

= +10V/–10V

BIAS

IS (OFF) +– I

(OFF) +–

D

I

(OFF) –+

S

I

(OFF) –+

D

I

, IS (ON) ++

D

I

, IS (ON) ––

D

VDD = +15V V

= –15V

SS

V

= +10V/–10V

BIAS

IS (OFF) +– I

(OFF) +–

D

I

(OFF) –+

S

I

(OFF) –+

D

I

, IS (ON) ++

D

I

, IS (ON) ––

D

VDD = +5V

= –5V

V

SS

= +4.5V/–4.5V

V

BIAS

IS (OFF) +–

(OFF) +–

I

D

(OFF) –+

I

S

(OFF) –+

I

D

, IS (ON) ++

I

D

, IS (ON) ––

I

D

TEMPERATURE ( °C)

60 70 80

15 V Dual Supply

TEMPERATURE ( °C)

15 V Dual Supply

TEMPERATURE ( °C)

5 V Dual Supply

14

VDD = +12V

12

V

= 0V

SS

V

= +1V/+10V

BIAS

10

8

IS (OFF) +– I

(OFF) +–

D

6

I

(OFF) –+

S

I

(OFF) –+

4

D

I

, IS (ON) ++

D

I

, IS (ON) ––

2

D

LEAKAGE CURRENT (n A)

0

–2

07419-012

–4

0

07419-015

12010080604020

TEMPERATURE ( °C)

Figure 16. Leakage Current as a Function of Temperature,

12 V Single Supply

160

T

= 25°C

140

A

I

PER LOGI C INPUT

DD

120

100

(µA)

80

DD

I

60

= +12V

V

40

20

07419-013

12010080604020

0

0 1.5 4.5 9.0 15.0

DD

V

= 0V

SS

= +5V

V

DD

V

= –5V

SS

3.0 7.5 12. 06.0 10.5 13.5

V V

DD

= –15V

SS

= +15V

07419-016

LOGIC LEVEL (Ax, EN) (V)

Figure 17. IDD vs. Logic Level

100

TA = 25°C

80

60

40

20

VDD = +5V V

= –5V

SS

0

–20

CHARGE INJECTI ON (pC)

–40

VDD = +15V V

= –15V

SS

VDD = +12V V

= 0V

SS

–60

07419-014

12010080604020

–80

–15 –10 –5 0 5 10 15

07419-017

VS (V)

Figure 18. Charge Injection vs. Source Voltage

Rev. A | Page 14 of 20

ADG1406/ADG1407

350

300

250

200

150

TIME (ns)

100

50

VDD = +12V V

VDD = +15V V

= –15V

SS

VDD = +5V V

= +5V

SS

= 0V

SS

CROSSTALK (d B)

–20

–40

–60

–80

–100

0

VDD = +15V V

SS

T

A

= –15V

= 25°C

ADJACENT CHANNELS

(S1A TO S2A)

ADJACENT SWITCHES (S1A TO S1B)

0 –40 0–20 4020 60 80 100 120

TEMPERATURE (° C)

Figure 19. Transition Time vs. Temperature

0

VDD = +15V V

= –15V

SS

T

= 25°C

–20

A

–40

–60

–80

OFF ISOLATIO N (dB)

–100

–120

10k

1k

100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 20. Off Isolation vs. Frequency

–10

VDD = +15V V

= –15V

SS

T

= 25°C

A

–30

–50

–70

–90

CROSSTALK (dB)

–110

–130

07419-018

–120

10k

1k

100k 1M 10M 100M 1G

FREQUENCY (Hz)

07419-021

Figure 22. ADG1407 Crosstalk vs. Frequency

0

–0.5

–1.0

–1.5

–2.0

–2.5

INSERTION LOSS (dB)

–3.0

VDD = +15V V

= –15V

SS

T

= 25°C

A

–3.5

–4.0

07419-019

100

10k1k

100k 1M 10M 100M

FREQUENCY (Hz)

07419-022

Figure 23. ADG1406 On Response vs. Frequency

0.14

0.12

0.10

0.08

0.06

THD + N (%)

0.04

0.02

VS = 20V p-p

VS = 15V p-p

VS = 10V p-p

VDD = +15V

= –15V

V

SS

= 25°C

T

A

= 100Ω

R

L

–150

10k

1k

100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 21. ADG1406 Crosstalk vs. Frequency

07419-020

Rev. A | Page 15 of 20

0

02 8 14 20

4101661218

FREQUENCY (kHz)

Figure 24. THD + N vs. Frequency, 15 V Dual Supply

07419-023

ADG1406/ADG1407

1.2

1.0

0.8

0.6

THD + N (%)

0.4

0.2

0

02 8 14 20

Figure 25. THD + N vs. Frequency, 5 V Dual Supply

VS = 10V p-p

VS = 5V p-p

VS = 2.5V p-p

4101661218

FREQUENCY (kHz)

VDD = +5V

= –5V

V

SS

= 25°C

T

A

=110Ω

R

L

0

VDD = +15V

= –15V

V

SS

= 25°C

T

A

–20

V p-p = 0.63V

–40

NO DECOUPLI NG

–60

ACPSRR (dB)

–80

–100

07419-024

–120

100

CAPACITORS

10k 100k

FREQUENCY (Hz)

DECOUPLING

CAPACITORS

ON SUPPLIES

1M

10M1k

07419-025

Figure 26. ACPSRR vs. Frequency

Rev. A | Page 16 of 20

ADG1406/ADG1407

TERMINOLOGY

t

RON

Ohmic resistance between the D and S terminals.

ΔR

ON

Difference between the R

FLAT(ON)

R

of any two channels.

ON

Flatness is defined as the difference between the maximum and minimum value of on resistance as measured.

I

(Off)

S

Source leakage current when the switch is off.

I

(Off)

D

Drain leakage current when the switch is off.

I

, IS (On)

D

Channel leakage current when the switch is on.

V

, VS

D

Analog voltage on Terminal D and Terminal S.

C

(Off)

S

Channel input capacitance for the off condition.

C

(Off)

D

Channel output capacitance for the off condition.

C

, CS (On)

D

On switch capacitance.

C

IN

Digital input capacitance.

t

(EN)

ON

Delay time between the 50% and 90% points of the digital input and the switch on condition.

t

(EN)

OFF

Delay time between the 50% and 90% points of the digital input and the switch off condition.

t

TRANSITION

Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another.

BBM

Off time measured between the 80% points of the switches when switching from one address state to another.

V

INL

Maximum input voltage for Logic 0.

V

INH

Minimum input voltage for Logic 1.

I

, I

INL

INH

Input current of the digital input.

I

DD

Positive supply current.

I

SS

Negative supply current.

Off Isolation

A measure of unwanted signal coupling through an off channel.

Charge Injection

A measure of the glitch impulse transferred from the digital input to the analog output during switching.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to the fundamental.

ACPSRR (AC Power Supply Rejection Ratio)

Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.

Rev. A | Page 17 of 20

ADG1406/ADG1407

TEST CIRCUITS

V

SD

V

S

Figure 27. On Resistance

3V

ADDRESS DRIVE (V

0V

t

TRANSITION

OUTPUT

)

IN

I

DS

07419-125

50% 50%

90%

IS(OFF) ID(OFF)

V

S

SD

A A

Figure 28. Off Leakage

t

< 20ns

r

t

< 20ns

f

V

IN

t

TRANSITION

90%

V

D

50Ω

2.4V EN

07419-026

V

DD

V

DD

A0

A1

A2

A3

ADG1406

GND

V

SS

V

SS

S2 TO S15

S16

1

SD

NC

NC = NO CONNECT

Figure 29. On Leakage

S1

D

OUTPUT

300Ω

V

S1

V

S16

35pF

ID(ON)

A

V

D

07419-027

ADDRESS DRIVE (V

OUTPUT

3V

ENABLE DRIVE (V

0V

OUTPUT

1

SIMILAR CO NNECTION F OR ADG1407.

Figure 30. Address to Output Switching Times, t

3V

)

IN

0V

80% 80%

t

BBM

V

IN

50Ω

Figure 31. Break-Before-Make Delay, t

)

IN

t

(EN)

ON

50% 50%

0.9V

OUT

0.9V

t

(EN)

OFF

OUT

V

IN

TRANSITION

V

DDVSS

V

DDVSS

A0

A1

A2

A3

ADG1406

2.4V EN

1

SIMILAR CO NNECTION F OR ADG1407.

BBM

A0

A1

A2

A3

EN

50Ω

S1

S2 TO S15

S16

1

GND

V

DD

V

DD

S2 TO S16

ADG1406

GND

D

SS

OUTPUT

S1

1

D

300Ω

OUTPUT

300Ω

V

S

35pF

07419-028

07419-029

Figure 32. Enable Delay, t

Rev. A | Page 18 of 20

ON

1

SIMILAR CO NNECTION F OR ADG1407.

(EN), t

(EN)

OFF

07419-030

ADG1406/ADG1407

3V

V

DD

SS

V

DD

A0

SS

A1

V

IN

A2

A3

ADG1406

S

EN

GND

1

D

C 1nF

V

OUT

L

07419-031

V

IN

R

S

V

OUT

Q

INJ

= CL × ΔV

OUT

ΔV

OUT

V

S

1

SIMILAR CO NNECTION F OR ADG1407.

Figure 33. Charge Injection

0.1µF

V

DD

V

SS

0.1µF

NETWORK

V

DD

SS

S

50Ω

D

GND

ANALYZER

50Ω

V

OUT

R

L

50Ω

S

NETWORK

ANALYZER

V

OUT

R

L

50Ω

V

S

V

0.1µF

S1

V

DD

SS

0.1µF

V

S2

V

DD

SS

D

R 50Ω

GND

0.1µF

V

OFF ISOLATION = 20 log

OUT

V

S

07419-032

Figure 34. Off Isolation

V

DD

V

SS

0.1µF

NETWORK

V

DD

SS

S

D

GND

ANALYZER

50Ω

V

OUT

R

L

50Ω

S

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

Figure 36. Channel-to-Channel Crosstalk

V

0.1µF

IN

V

IN

V

DD

V

SS

0.1µF

V

DD

SS

S

D

GND

WITH SWITCH

V

INSERTION LOSS = 20 log

Figure 35. Bandwidth

OUT

WITHOUT SWITCH

V

OUT

07419-033

Figure 37. THD + Noise

R

L

10kΩ

V

OUT

V

S

AUDIO PRECISION

R

S

V

S

V p-p

V

OUT

07419-034

07419-035

Rev. A | Page 19 of 20

ADG1406/ADG1407

C

Y

C

OUTLINE DIMENSIONS

9.80

9.70

9.60

INDI

1.00

0.85

0.80

PIN 1

ATO R

12° MAX

SEATING PLANE

PIN 1

0.15

0.05

OPLANARIT

0.10

28

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

141

Figure 38. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

0.08

0.60 MAX

25

24

(BOTTOM VIEW)

17

16

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARIT Y

Figure 39. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

8° 0°

0.75

0.60

0.45

PIN 1

32

EXPOSED

PAD

9

3.50 REF

FOR PROPER CONNECTION O F THE EXPOSED PAD, REFER TO THE PIN CONF IGURATIO N AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

INDICATOR

1

3.25

3.10 SQ

2.95

8

0.25 MIN

011708-A

ORDERING GUIDE

Model Temperature Range Description Package Option

ADG1406BRUZ ADG1406BRUZ-REEL71 −40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ADG1406BCPZ-REEL71 −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2 ADG1407BRUZ ADG1407BRUZ-REEL7 ADG1407BCPZ-REEL7

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28

1

−40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28

1

−40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28

1

−40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

Rev. A | Page 20 of 20

Datasheet ADG1406, ADG1407 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

±15 V DUAL SUPPLY

12 V SINGLE SUPPLY

±5 V DUAL SUPPLY

CONTINUOUS CURRENT PER CHANNEL

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

TEST CIRCUITS

OUTLINE DIMENSIONS

ORDERING GUIDE