Datasheet ADG1404 Datasheet (ANALOG DEVICES)

1.5 Ω On Resistance,

www.BDTIC.com/ADI

FEATURES

1.5 Ω on resistance

0.3 Ω on-resistance flatness

0.1 Ω on-resistance match between channels Up to 400 mA continuous current Fully specified at +12 V, ±15 V, and ±5 V No V

supply required

L

3 V logic-compatible inputs Rail-to-rail operation 14-lead TSSOP and 4 mm × 4 mm, 16-lead LFCSP

APPLICATIONS

Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Communication systems Relay replacement

±15 V/12 V/±5 V, 4:1, iCMOS Multiplexer

ADG1404

FUNCTIONAL BLOCK DIAGRAM

ADG1404

S1

S2

S3

S4

1 OF 4

DECODER

A0 A1 EN

Figure 1.

D

06816-001

GENERAL DESCRIPTION

The ADG1404 is a complementary metal-oxide semiconductor (CMOS) analog multiplexer, comprising four single channels designed on an iCMOS® process. iCMOS (industrial CMOS) is a modular manufacturing process that combines high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.

The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals.

iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments.

The ADG1404 switches one of four inputs to a common output, D, as determined by the 3-bit binary address lines, A0, A1, and EN. Logic 0 on the EN pin disables the device. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.

PRODUCT HIGHLIGHTS

1. 2.6 Ω maximum on resistance over temperature.

2. Minimum distortion.

3. Ultralow power dissipation: <0.03 μW.

4. 14-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP package.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADG1404

www.BDTIC.com/ADI

REVISION HISTORY

7/08—Revision 0: Initial Version

Continuous Current, S or D .........................................................6

Absolute Maximum Ratings ............................................................7

ESD Caution...................................................................................7

Pin Configurations and Function Descriptions ............................8

Truth Table .....................................................................................8

Typical Performance Characteristics ..............................................9

Terminology .................................................................................... 12

Test Circuits ..................................................................................... 13

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

Rev. 0 | Page 2 of 16

ADG1404

www.BDTIC.com/ADI

SPECIFICATIONS

15 V DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Para meter 25°C −40°C to +85°C −40°C to +125°C Unit Test Con ditions/Com ments

ANALOG SWITCH

Analog Signal Range VDD to VSS V On Resistance (RON) 1.5 Ω typ VS = ±10 V, IS = −10 mA; see Figure 22

1.8 2.3 2.6 Ω max VDD = +13.5 V, VSS = −13.5 V On-Resistance Match

Between Channels (ΔR

0.18 0.19 0.21 Ω max On-Resistance Flatness (R

0.36 0.4 0.45 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.03 nA typ

±0.55 ±2 ±12.5 nA max Drain Off Leakage, ID (Off) ±0.04 nA typ

±0.55 ±4 ±30 nA max Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 24 ±2 ±4 ±30 nA max

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I ±0.1 μA max Digital Input Capacitance, CIN 3.5 pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t 180 220 250 ns max VS = +10 V; see Figure 29 tON (EN) 100 ns typ RL = 300 Ω, CL = 35 pF 120 145 165 ns max VS = +10 V; see Figure 31 t

(EN) 110 ns typ RL = 300 Ω, CL = 35 pF

OFF

135 165 185 ns max VS = +10 V; see Figure 31 Break-Before-Make Time Delay, t 10 ns min VS1 = VS2 = 10 V; see Figure 30 Charge Injection −20 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 25 Channel-to-Channel Crosstalk 82 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27 Total Harmonic Distortion + Noise 0.011 % ty p RL = 110 Ω, 10 V p-p, f = 20 Hz to 20 kHz; see

−3 dB Bandwidth 55 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 Insertion Loss −0.17 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 CS (Off) 23 pF typ f = 1 MHz, VS = 0 V CD (Off) 90 pF typ f = 1 MHz, VS = 0 V CD, CS (On) 170 pF typ f = 1 MHz, VS = 0 V

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 170 μA typ Digital inputs = 5 V 280 μA max ISS 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max VDD/VSS ±4.5/±16.5 V min/max GND = 0 V

1

Guaranteed by design, not subject to production test.

or INH 0.005 μA typ VIN = V

INL

TRANSITION

)

ON

) 0.3 Ω typ VS = ±10 V, IS = −10 mA

FLAT(ON)

2.0 V min

INH

0.8 V max

INL

1

150 ns typ RL = 300 Ω, CL = 35 pF

0.1 Ω typ V

35 ns typ RL = 300 Ω, CL = 35 pF

BBM

= ±10 V, IS = −10 mA

S

V

= ±10 V, Vs = ∓10 V; see Figure 23

S

V

= ±10 V, Vs = ∓10 V; see Figure 23

S

or VDD

GND

Figure 28

Rev. 0 | Page 3 of 16

ADG1404

www.BDTIC.com/ADI

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance (RON) 2.8 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 22

3.5 4.3 4.8 Ω max VDD = 10.8 V, VSS = 0 V On-Resistance Match

Between Channels (ΔR

)

ON

0.21 0.23 0.25 Ω max On-Resistance Flatness (R

FLAT(ON)

1.1 1.2 1.3 Ω max

LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 ±0.55 Drain Off Leakage, ID (Off) ±0.03 ±0.55 Channel On Leakage, ID, IS (On) ±0.1 ±1.5 DIGITAL INPUTS Input High Voltage, V Input Low Voltage, V Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INL

INH

±0.1 μA max Digital Input Capacitance, CIN 3.5 pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANSITION

1

230 ns typ RL = 300 Ω, CL = 35 pF 300 375 430 ns max VS = 8 V; see Figure 29 tON (EN) 180 ns typ RL = 300 Ω, CL = 35 pF 240 295 335 ns max VS = 8 V; see Figure 31 t

(EN) 115 ns typ RL = 300 Ω, CL = 35 pF

OFF

160 190 220 ns max VS = 8 V; see Figure 31 Break-Before-Make Time Delay, t 10 ns min VS1 = VS2 = 8 V; see Figure 30 Charge Injection 30 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 100kHz; see Figure 25 Channel-to-Channel Crosstalk 82 dB typ RL = 50 Ω, CL = 5 pF, f = 100kHz; see Figure 27

−3 dB Bandwidth 35 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 Insertion Loss −0.3 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 CS (Off) 39 pF typ f = 1 MHz, VS = 6 V CD (Off) 150 pF typ f = 1 MHz, VS = 6 V CD, CS (On) 217 pF typ f = 1 MHz, VS = 6 V

POWER REQUIREMENTS VDD = 13.2 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max IDD 170 μA typ Digital inputs = 5 V 260 μA max VDD 5/16.5 V min/max GND = 0 V, VSS = 0 V

1

Guaranteed by design, not subject to production test.

0.13 Ω typ V

= 0 V to 10 V, IS = −10 mA

S

) 0.6 Ω typ VS = 0V to 10 V, IS = −10 mA

±2 ±12.5

±4 ±30

nA max nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 nA max nA typ VS = VD = 1 V or 10 V; see Figure 24 nA max

or VDD

GND

100 ns typ RL = 300 Ω, CL = 35 pF

BBM

Rev. 0 | Page 4 of 16

ADG1404

www.BDTIC.com/ADI

5 V DUAL SUPPLY

VDD = 5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

VDD to V

On Resistance (RON) 3.3 Ω typ 4 4.9 5.4 Ω max VDD = +4.5 V, VSS = −4.5 V On-Resistance Match

Between Channels (∆R

)

ON

0.13 Ω typ V

0.22 0.23 0.25 Ω max On-Resistance Flatness (R

) 0.9 Ω typ VS = ±4.5 V, IS = −10 mA

FLAT(ON)

1.1 1.24 1.31 Ω max

LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V

Source Off Leakage, IS (Off) ±0.02 nA typ

±0.2 Drain Off Leakage, ID (Off) ±0.02

±0.25 Channel On Leakage, ID, IS (On) ±0.05 ±0.25

±1 ±12.5

±1.2 ±15

±1.5 ±20

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INL

INH

±0.1 μA max Digital Input Capacitance, CIN 3 5 pF typ

DYNAMIC CHARACTERISTICS1

Transition Time, t

340 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

470 560 615 ns max VS = 3 V; Figure 29 tON (EN) 260 ns typ RL = 300 Ω, CL = 35 pF 355 430 480 ns max t

(EN) 220 ns typ RL = 300 Ω, CL = 35 pF

OFF

315 365 400 ns max Break-Before-Make Time Delay, t

100 ns typ RL = 300 Ω, CL = 35 pF

BBM

50 ns min VS1 = VS2 = 3 V; see Figure 30 Charge Injection 30 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;

Channel-to-Channel Crosstalk 82 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;

−3 dB Bandwidth 40 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26 Insertion Loss 0.27 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 Total Harmonic Distortion + Noise 0.03 % typ RL = 110 Ω, 2.5 V p-p, f = 20 Hz to 20 kHz;

CS (Off) 33 pF typ VS = 0 V, f = 1 MHz CD (Off) 128 pF typ VS = 0 V, f = 1 MHz CD, CS (On) 210 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = 5.5 V, VSS = −5.5 V

IDD 0.001 μA typ Digital inputs = 0 V, 5 V, or VDD 1 μA max

ISS 0.001 μA typ Digital inputs = 0 V or VDD 1 μA max

VDD/VSS ±4.5/±16.5 V min/max GND = 0 V

1

Guaranteed by design, not subject to production test.

Rev. 0 | Page 5 of 16

SS

V

= ±4.5 V, IS = −10 mA; see Figure 22

S

= ±4.5 V, IS = −10 mA

S

= ±4.5 V, VD = ∓4.5 V; see Figure 23

V

S

nA max nA typ

= ±4.5 V, VD = ∓4.5 V; see Figure 23

V

S

nA max nA typ VS = VD = ±4.5 V; see Figure 24 nA max

or VDD

GND

V

= 3 V; Figure 31

S

V

= 3 V; Figure 31

S

see Figure 25

see Figure 27

see Figure 28

ADG1404

www.BDTIC.com/ADI

CONTINUOUS CURRENT, S OR D

Table 4.

Parameter 25°C 85°C 125°C Unit Test Conditions/Comments

CONTINUOUS CURRENT, S or D

15 V Dual Supply VDD = +13.5 V, VSS = −13.5 V

ADG1404 TSSOP 350 220 100 mA max ADG1404 LFCSP 450 300 140 mA max

12 V Single Supply VDD = 10.8 V, VSS = 0 V

ADG1404 TSSOP 300 220 100 mA max ADG1404 LFCSP 400 300 140 mA max

5 V Dual Supply VDD = +4.5 V, VSS = −4.5 V

ADG1404 TSSOP 300 220 100 mA max ADG1404 LFCSP 400 300 140 mA max

1

Guaranteed by design, not subject to production test.

1

Rev. 0 | Page 6 of 16

ADG1404

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to VSS 35 V VDD to GND −0.3 V to +25 V VSS to GND +0.3 V to −25 V Analog Inputs

Digital Inputs

Peak Current, S or D

Continuous Current, S or D Operating Temperature Range

Automotive (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 14-Lead TSSOP, θJA Thermal

Impedance (4-layer board) 16-Lead LFCSP, θJA Thermal

Impedance Reflow Soldering Peak

Temperature, Pb free

1

Overvoltages at IN, S, and D are clamped by internal diodes. Current should

be limited to the maximum ratings given.

2

See data given in Table 4.

1

2

VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first

GND − 0.3 V to V 30 mA, whichever occurs first

600 mA (pulsed at 1 ms, 10% duty cycle maximum)

Data + 15%

112°C/W

30.4°C/W

260(+0/−5)°C

+ 0.3 V or

DD

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Only one absolute maximum rating may be applied at any one time.

ESD CAUTION

Rev. 0 | Page 7 of 16

ADG1404

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

0 A

EN

A1

NC

14

13

15

16

1

A0

2

EN

3

V

ADG1404

SS

TOP VIEW

4

S1

(Not to Scale)

5

S2

6

D

7

NC

NC = NO CONNECT

Figure 2. TSSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 15 A0 Logic Control Input. 2 16 EN

3 1 VSS Most Negative Power Supply Potential. 4 3 S1 Source Terminal. Can be an input or an output. 5 4 S2 Source Terminal. Can be an input or an output. 6 6 D Drain Terminal. Can be an input or an output. 7 to 9 2, 5, 7, 8, 13 NC No Connection. 10 9 S4 Source Terminal. Can be an input or an output. 11 10 S3 Source Terminal. Can be an input or an output. 12 11 VDD Most Positive Power Supply Potential. 13 12 GND Ground (0 V) Reference. 14 14 A1 Logic Control Input.

14

A1

13

GND

12

V

DD

11

S3

10

S4

9

NC

8

NC

06816-002

SS

NOTES

1. EXPOSE D PAD TIED TO SUBSTRATE, V

2. NC = NO CONNECT .

1V

2NC

3S1

4S2

PIN 1 INDICATO R

ADG1404

TOP VIEW

(Not to Scale)

7

5

6

D

NC

12 GND

11 V

DD

10 S3

9S4

8

NC

SS

Figure 3. LFCSP Pin Configuration

Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the Ax logic inputs determine the on switches.

.

06816-003

TRUTH TABLE

Table 7.

EN A1 A0 S1 S2 S3 S4

0 X X Off Off Off Off 1 0 0 On Off Off Off 1 0 1 Off On Off Off 1 1 0 Off Off On Off 1 1 1 Off Off Off On

Rev. 0 | Page 8 of 16

ADG1404

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

2.5

2.0

1.5

1.0

ON RESISTANCE (Ω)

0.5

T

= 25°C

A

I

= –10mA

S

0

–16.5 –12.5 –8. 5 –4.5 –0.5 3.5 7.5 15.5

V

DD

V

SS

V

= +10V,

DD

V

= –10V

SS

= +13.5V, = –13.5V

V

= +12V,

DD

V

= –12V

SS

V

DD

V

SS

VS OR VD (V)

= +15V, = –15V

VDD = +16.5V, V

= –16.5V

SS

11.5

Figure 4. On Resistance as a Function of VD (VS), Dual Supply

06816-004

3.0

2.5

2.0

1.5

1.0

ON RESISTANCE (Ω)

0.5 VDD = +15V

V

= –15V

SS

I

= –10mA

S

0

–15 151050–5–10

TA = +125°C

= +85°C

T

A

TA = +25°C

T

= –40°C

A

VS OR VD (V)

06816-007

Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,

15 V Dual Supply

4.0

3.5

3.0

2.5

2.0

1.5

ON RESISTANCE ( Ω)

1.0

0.5 TA = 25°C

I

= –10mA

S

0

–7 –6 –5 –3 –1–4 –2 0 1 6

V V

= +4.5V,

DD

= –4.5V

SS

V

= +5V,

DD

V

= –5V

SS

V

DD

V

SS

VS OR VD (V)

= +5.5V, = –5.5V

34 752

VDD = +7V, V

SS

Figure 5. On Resistance as a Function of VD (VS), Dual Supply

7

6

5

4

3

ON RESISTANCE ( Ω)

2

1

TA = 25°C I

= –10mA

S

0

01412108642

V

= 5V,

DD

V

= 0V

SS

= 10.8V,

V

= 8V,

V

DD

V

= 0V

SS

DD

V

SS

V

DD

V

SS

VS OR VD (V)

= 0V

= 13.2V, = 0V

V

= 12V,

DD

V

= 0V

SS

VDD = 15V, V

= 0V

SS

Figure 6. On Resistance as a Function of VD (VS), Single Supply

= –7V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

ON RESISTANCE ( Ω)

1.5

1.0

VDD = +5V

0.5

V

= –5V

SS

I

= –10mA

S

0

–5 –4 –3 –2 –1 0 1 2 3 4 5

06816-005

= +125°C

T

A

T

= +85°C

A

TA = +25°C

= –40°C

T

A

VS OR VD (V)

06815-108

Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,

5 V Dual Supply

4.5

4.0

= +125°C

3.5

3.0

2.5

2.0

1.5

ON RESISTANCE ( Ω)

1.0

VDD = 12V

0.5 V

= 0V

SS

I

= –10mA

S

0

01108642

06816-006

T

A

T

= +85°C

A

TA = +25°C

= –40°C

T

A

VS OR VD (V)

2

06815-109

Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,

Single Supply

Rev. 0 | Page 9 of 16

ADG1404

www.BDTIC.com/ADI

6

4

2

0

–2

–4

–6

LEAKAGE (nA)

–8

–10

–12

–14

IS (OFF) + – ID (OFF) + – IS (OFF) – + ID (OFF) – + ID, IS (ON) + + ID, IS (ON) – –

VDD = +15V V

= –15V

SS

V

= +10V/–10V

BIAS

0 20406080100120

TEMPERATURE (°C)

06816-111

Figure 10. Leakage Currents as a Function of Temperature,15 V Dual Supply

80

70

60

50

40

(µA)

DD

I

30

20

10

0

0112108642

V

= +12V

DD

V

= 0V

SS

V

= +5V

DD

V

= –5V

SS

LOGIC, Ax (V)

TA = 25°C I

PER LOGI C INPUT

DD

VDD = +15V V

= –15V

SS

4

06815-008

Figure 13. IDD vs. Logic Level

4

IS (OFF) + – ID (OFF) + –

3

IS (OFF) – + ID (OFF) – +

2

ID, IS (ON) + + ID, IS (ON) – –

1

0

–1

LEAKAGE (nA)

–2

VDD = +5V

–3

V

= –5V

SS

V

= +4.5V/–4. 5V

BIAS

–4

0 20406080100120

TEMPERATURE (°C)

06816-112

Figure 11. Leakage Currents as a Function of Temperature, 5 V Dual Supply

14

12

10

LEAKAGE (nA)

–2

–4

IS (OFF) + – ID (OFF) + – IS (OFF) – + ID (OFF) – + ID, IS (ON) + + ID, IS (ON) – –

8

6

4

2

0

VDD = 12V V

= 0V

SS

V

= 1V/10V

BIAS

0 20406080100120

TEMPERATURE (°C)

06816-113

Figu re 12. Leakage Currents as a Function of Temperature, 12 V Single Supply

600

= 25°C

T

A

400

200

= +5V, VSS = –5V

V

DD

0

–200

CHARGE INJECTI ON (pC)

–400

–600

–15 –10 –5 0 5 10 15

VDD = +15V, VSS = –15V

= +12V, VSS = 0V

V

DD

VS (V)

Figure 14. Charge Injection vs. Source Voltage

500

450

400

350

300

250

TIME (ns)

200

150

100

50

0

–40 –20 0 20 40 60 80 120

V

DD

V

= +12V, VSS = 0V

DD

TEMPERATURE (°C)

= +5V, VSS = –5V

VDD = +15V, VSS = –15V

Figure 15. Transition Times vs. Temperature

06816-012

100

06816-013

Rev. 0 | Page 10 of 16

ADG1404

www.BDTIC.com/ADI

0

TA = 25°C

–5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65

OFF ISOLATION (dB)

–70 –75 –80 –85 –90 –95

–100

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 16. Off Isolation vs. Frequency

06816-014

0.024

0.022

VDD = +15V V

= –15V

SS

0.020 T

= 25°C

A

0.018

0.016

0.014

0.012

THD + N (%)

0.010

0.008

0.006

0.004

0.002

10 100 1k 10k 100k

VS = 20V p-p

= 15V p-p

V

S

VS = 10V p-p

FREQUENCY (Hz)

Figure 19. THD + N vs. Frequency at ±15 V

06816-017

0

TA = 25°C

–10

–20

–30

–40

–50

–60

–70

CROSSTALK (dB)

–80

–90

–100

–110

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 17. Crosstalk vs. Frequency

0

VDD = +15V

–1

V

= –15V

SS

T

= 25°C

A

–2

–3

–4

INSERTION LOSS (dB)

–5

–6

–7

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 18. On Response vs. Frequency

1

VDD = +5V V

= –5V

SS

T

= 25°C

A

0.1

THD + N (%)

0.01

0.001

10 100 1k 10k 100k

06816-015

V

= 10V p-p

S

V

= 5V p-p

S

V

= 2.5V p-p

S

FREQUENCY (Hz)

06816-018

Figure 20. THD + N vs. Frequency at ±5 V

0

VDD = +15V V

= –15V

–10

SS

V p-p = 0.63V T

= 25°C

–20

A

–30

–40

–50

–60

ACPSRR (dB)

–70

–80

–90

–100

1k 10k 100k 1M 10M

06816-016

NO DECOUPLING

CAPACITORS

FREQUENCY (Hz)

DECOUPLING CAPACIT ORS

ON SUPPLIES

06815-017

Figure 21. ACPSRR vs. Frequency

Rev. 0 | Page 11 of 16

ADG1404

www.BDTIC.com/ADI

TERMINOLOGY

IDD

The positive supply current.

I

SS

The negative supply current.

V

(VS)

D

The analog voltage on Terminal D and Terminal S.

R

ON

The ohmic resistance between Terminal D and Terminal S.

R

FLAT(ON)

Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range.

I

(Off)

S

The source leakage current with the switch off.

I

(Off)

D

The drain leakage current with the switch off.

I

, IS (On)

D

The channel leakage current with the switch on.

V

INL

The maximum input voltage for Logic 0.

V

INH

The minimum input voltage for Logic 1.

I

(I

)

INL

INH

The input current of the digital input.

C

(Off)

S

The off switch source capacitance, which is measured with reference to ground.

C

(Off)

D

The off switch drain capacitance, which is measured with reference to ground.

C

, CS (On)

D

The on switch capacitance, which is measured with reference to ground.

C

IN

The digital input capacitance.

t

TRANSITION

The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another.

t

(EN)

ON

The delay between applying the digital control input and the output switching on. See Figure 29, Test Circuit 4.

t

(EN)

OFF

The delay between applying the digital control input and the output switching off.

Charge Injection

A measure of the glitch impulse transferred from the digital input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to the fundamental.

ACPSRR (AC Power Supply Rejection Ratio)

The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the part’s ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p.

Rev. 0 | Page 12 of 16

ADG1404

www.BDTIC.com/ADI

TEST CIRCUITS

V

DD

SS

0.1µF

50Ω

D

OFF ISOLATION = 20 log

Figure 25. Off Isolation

V

SS

0.1µF

D

NETWORK

ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

V

OUT

V

S

NETWORK

ANALYZER

50Ω

V

OUT

R

L

50Ω

V

S

06816-027

V

Sx D

V

S

Figure 22. On Resistance

IS (OFF) ID (OFF)

Sx D

A A

0.1µF

V

DDVSS

Sx

GND

I

DS

06816-020

V

DD

0.1µF

V

DDVSS

Sx

GND

ID (ON)

A

V

D

V

D

06816-021

INSERTION LOSS = 20 log

WITH SWITCH

V

OUT

V

WITHOUT SWITCH

OUT

06816-028

Figure 26. Bandwidth

V

DD

0.1µF

NETWO RK

ANALYZER

V

OUT

R

L

50Ω

V

S

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

06816-022

V

DD

S1

S2

GND

V

OUT

V

SS

0.1µF

V

SS

D

R

L

50Ω

S

06816-029

Figure 27. Channel-to-Channel Crosstalk

V

S

NC

Figure 23. Off Leakage

Sx D

NC = NO CONNECT

Figure 24. On Leakage

Rev. 0 | Page 13 of 16

ADG1404

www.BDTIC.com/ADI

V

0.1µF

IN

V

IN

V

DD

V

SS

0.1µF

R

L

110Ω

AUDIO PRECISIO N

R

S

V

S

V p-p

V

OUT

06816-030

V

DD

SS

Sx

D

GND

Figure 28. THD + Noise

V

SS

DD

0.1µF

A1

V

IN

2.4V

A0

EN

0.1µF

V

SS

DD

GND

S1

S2

S3

S4

D

R

L

300Ω

V

S1

V

S4

C 35pF

ADDRESS

DRIVE (V

V

OUT

L

3V

)

IN

0V

V

OUT

50% 50%

90%

t

TRANSITI ON

t

TRANSITION

90%

06816-023

Figure 29. Address to Output Switching Times

V

SS

DD

0.1µF

V

SS

DD

GND

S1

S2

S3

S4

D

R 300Ω

A1

V

IN

300Ω

2.4V

A0

EN

V

S1

V

OUT

C

L

35pF

ADDRESS

DRIVE (V

3V

)

IN

0V

V

OUT

80%

t

BBM

80%

06816-024

Figure 30. Break-Before-Make Time Delay

Rev. 0 | Page 14 of 16

ADG1404

www.BDTIC.com/ADI

0.1µF

V

IN

300Ω

A1

A0

EN

V

DD

SS

0.1µF

3V

V

SS

DD

GND

S1

S2

S3

S4

D

R

L

300Ω

V

S

C

L

35pF

ENABLE

OUTPUT

)

IN

0V

V

OUT

0V

DRIVE (V

V

OUT

50% 50%

0.9V

OUT

t

(EN)

ON

t

OFF

0.9V

(EN)

OUT

06816-025

Figure 31. Enable-to-Output Switching Delay

V

R

S

V

S

GND

DD

Sx D

DECODER

A2A1

SS

V

SS

V

OUT

C

L

1nF

EN

V

OUT

V

Q

= CL × ΔV

INJ

IN

SW OFF

SW ON

SW OFF

V

IN

OUT

ΔV

OUT

SW OFF

06816-026

Figure 32. Charge Injection

Rev. 0 | Page 15 of 16

ADG1404

C

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.10

5.00

4.90

1.05

1.00

0.80

4.50

4.40

4.30

PIN 1

14

0.65 BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

0.30

0.19

8

6.40

BSC

71

1.20 MAX

SEATING PLANE

0.20

0.09

COPLANARITY

0.10

8° 0°

0.75

0.60

0.45

Figure 33. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimension shown in millimeters

0.50

0.40

INDI

SEATING

PLANE

PIN 1

ATO R

1.00

0.85

0.80

12° MAX

4.00

BSC SQ

3.75

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.05 MAX

0.30

0.23

0.18

COMPLIANTTOJEDEC STANDARDS MO-220-VGGC.

0.02 NOM

0.20 REF

0.60 MAX

12

0.65

9

BSC

1.95 BCS

COPLANARITY

0.08

13

EXPOSED

8

BOTTOM VIEW

PAD

0.30

1

16

4

5

N

P

I

D

N

I

2.65

2.50 SQ

2.35

0.25 MIN

1

R

O

C

I

A

T

031006-A

Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1404YRUZ ADG1404YRUZ-REEL7 ADG1404YCPZ-REEL ADG1404YCPZ-REEL7

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-13

1

−40°C to +125°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14

1

−40°C to +125°C 14-Lead Thin Shrink Small Outline Package (TSSOP) RU-14

−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-13

Rev. 0 | Page 16 of 16

Datasheet ADG1404 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

15 V DUAL SUPPLY

12 V SINGLE SUPPLY

5 V DUAL SUPPLY

CONTINUOUS CURRENT, S OR D

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TRUTH TABLE

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

TEST CIRCUITS

OUTLINE DIMENSIONS

ORDERING GUIDE