ANALOG DEVICES ADG1311 Service Manual

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±15 V/12 V Quad SPST Switches

ADG1311/ADG1312/ADG1313

FEATURES FUNCTIONAL BLOCK DIAGRAM

33 V supply range Fully specified at +12 V, ±15 V 130 Ω on resistance

supply required

No V

L

3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead SOIC Typical power consumption: <0.03 μW

APPLICATIONS

Signal switching Battery-powered systems Communication systems Audio/video signal routing

IN1

IN2

ADG1311

IN3

IN4

S1

IN1

D1 S2

IN2

D2 S3

D3 S4

D4

SWITCHES SHOWN FOR A LOGIC 1 INPUT

ADG1312

IN3

IN4

Figure 1.

S1

IN1

D1 S2

IN2

D2 S3

IN3

D3 S4

IN4

D4

ADG1313

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The ADG1311/ADG1312/ADG1313 are monolithic CMOS

vices containing four independently selectable switches

de designed on a CMOS process.

1. 3 V logic-compatible digital inputs: V

logic power supply required.

V

2. No

3. 16-lead TSSO

L

P and SOIC packages.

= 2.0 V, VIL = 0.8 V.

IH

S1

D1 S2

D2 S3

D3 S4

D4

05676-001

The ADG1311/ADG1312/ADG1313 contain four independent s

ingle-pole/single-throw (SPST) switches. The ADG1311 and ADG1312 differ only in that the digital control logic is inverted. The ADG1311 switches are turned on with Logic 0 on the appropriate control input, while Logic 1 is required for the ADG1312. The ADG1313 has two switches with digital control logic similar to the ADG1311; the logic is inverted on the other two switches. The ADG1313 exhibits break-before-make switching action for use in multiplexer applications.

Each switch conducts equally well in both

directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADG1311/ADG1312/ADG1313

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TABLE OF CONTENTS

Features.............................................................................................. 1

Absolute Maximum Ratings ............................................................5

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Specifications..................................................................................... 3

Dual Supply................................................................................... 3

Single Supply................................................................................. 4

REVISION HISTORY

10/05—Revision 0: Initial Version

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions..............................6

Terminology.......................................................................................7

Typical Performance Characteristics..............................................8

Test Circuits..................................................................................... 10

Outline Dimensions....................................................................... 12

Ordering Guide .......................................................................... 12

Rev. 0 | Page 2 of 12

ADG1311/ADG1312/ADG1313

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SPECIFICATIONS

DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Y Version Parameter 25°C −40°C to +105°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V On Resistance (RON) 130 230 Ω typ VS = ±10 V, IS = −1 mA; Figure 10 200 Ω max VDD = +13.5 V, VSS = −13.5 V On Resistance Match Between

Channels (∆R

)

ON

5 Ω typ V

10 Ω max On Resistance Flatness (R

) 25 Ω typ VS = −5 V/0 V/+5 V; IS = −1 mA

FLAT(ON)

65 Ω max LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±10 nA typ

Drain Off Leakage, ID (Off) ±10 nA typ

Channel On Leakage, ID, IS (On) ±10 nA typ VS = VD = ±10 V; Figure 12

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.005 μA typ VIN = V

INH

±0.1 μA max Digital Input Capacitance, CIN 2.5 pF typ

DYNAMIC CHARACTERISTICS2

tON 105 ns typ RL = 300 Ω, CL = 35 pF 125 180 ns max VS = +10 V; Figure 13 t

40 ns typ RL = 300 Ω, CL = 35 pF

OFF

50 60 ns max VS = +10 V; Figure 13 Break-Before-Make Time Delay, tD 25 ns typ RL = 300 Ω, CL = 35 pF

(ADG1313 Only) 10 ns min VS1 = VS2 = 10 V; Figure 14 Charge Injection 2 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 15 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 16 Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 17

−3 dB Bandwidth 600 MHz typ RL = 50 Ω, CL = 5 pF; Figure 18 CS (Off) 5 pF typ CD (Off) 5 pF typ CD, CS (On) 10 pF typ

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max IDD 220 μA typ Digital inputs = 5 V 320 μA max ISS 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max ISS 0.001 μA typ Digital inputs = 5 V

1.0 μA max

1

Temperature range for Y Version is −40°C to +105°C.

2

Guaranteed by design, not subject to production test.

1

= ±10 V, IS = −1 mA

S

VS = ±10 V, VD = ∓10 V; Figure 11

V

= ±10V, VD = ∓10 V; Figure 11

S

or V

INH

INL

Rev. 0 | Page 3 of 12

ADG1311/ADG1312/ADG1313

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SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Y Version Parameter 25°C −40°C to +105°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V On Resistance (RON) 325 520 Ω typ VS = 0 V − 10 V, IS = −1 mA; Figure 10 500 Ω max VDD = 10.8 V, VSS = 0 V On Resistance Match Between

Channels (∆R

)

ON

10 Ω typ V

15 Ω max On Resistance Flatness (R

) 65 Ω typ VS = +3 V/+6 V/+9 V, IS = −1 mA

FLAT(ON)

LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) ±10 nA typ VS = +1 V/+10 V, VD = +10 V/+1 V; Figure 11 Drain Off Leakage, ID (Off) ±10 nA typ VS = +1 V/+10 V, VD = +10 V/+1 V Figure 11 Channel On Leakage, ID, IS (On) ±10 nA typ VS = VD = +1 V or +10 V; Figure 12

DIGITAL INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

0.001 μA typ VIN = V

INH

±0.1 μA max Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS2

tON 120 ns typ RL = 300 Ω, CL = 35 pF 155 210 ns max VS = 8 V; Figure 13 t

45 ns typ RL = 300 Ω, CL = 35 pF

OFF

65 80 ns max VS = 8 V; Figure 13 Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF

(ADG1313 Only) 10 ns min VS1 = VS2 = 8 V; Figure 14 Charge Injection 2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 15 Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 16 Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 17

−3 dB Bandwidth 500 MHz typ RL = 50 Ω, CL = 5 pF; Figure 18 CS (Off) 5 pF typ CD (Off) 5 pF typ CD, CS (On) 10 pF typ

POWER REQUIREMENTS VDD = 13.2 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max IDD 220 μA typ Digital inputs = 5 V

320 μA max

1

Temperature range for Y Version is −40°C to +105°C.

2

Guaranteed by design, not subject to production test.

1

= 0 V − 10 V, IS = −1 mA

S

or V

INL

INH

Rev. 0 | Page 4 of 12