Analog Devices ADG1236 prd Datasheet

2 pF Off Capacitance, 1 pC Charge Injection,

±15 V/12 V iCMOS™ Dual SPDT Switch

Preliminary Technical Data

FEATURES

2 pF off capacitance
1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at +12 V, ±15 V

supply required

No V

L

3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 12-lead LFCSP packages
Typical power consumption: <0.03 µW

APPLICATIONS

Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems

GENERAL DESCRIPTION

The ADG1236 is a monolithic CMOS device containing two
independently selectable SPDT switches. It is designed on an
iCMOS process. iCMOS (industrial-CMOS) is a modular
manufacturing process combining high voltage CMOS
(complementary metal-oxide semiconductor) and bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 30 V operation in a footprint
that no previous generation of high voltage parts has been able
to achieve. Unlike analog ICs using conventional CMOS proc­esses, iCMOS components can tolerate high supply voltages,
while providing increased performance, dramatically lower
power consumption, and reduced package size.

The ultralow capacitance and charge injection of the part make
it an ideal solution for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make the
part suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the part ideally
suited for portable and battery-powered instruments.

ADG1236

FUNCTIONAL BLOCK DIAGRAM

S1A

S1B

IN1

IN2

S2A

S2B

SWITCHES SHOWN FOR A LOGIC 1 INPUT

Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.

PRODUCT HIGHLIGHTS

1. 2 pF off capacitance (±15 V supply).

2. 1 pC charge injection.

3. 3 V logic-compatible digital inputs: V

4. No V

5. Ultralow power dissipation: <0.03 µW.

6. 16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP

logic power supply required.

L

packages.

ADG1236

Figure 1.

D1

D2

04776-0-001

= 2.0 V, VIL = 0.8 V.

IH

Rev. PrD

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Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADG1236 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Pin Configurations and Function Descriptions ............................7

Dual Supply ................................................................................... 3

Single Supply ................................................................................. 4

Absolute Maximum Ratings............................................................ 6

Truth Table For Switches............................................................. 6

ESD Caution.................................................................................. 6

REVISION HISTORY

11/04—Revision PrD: Preliminary Version

Te r m in o l o g y .......................................................................................8

Typical Performanc e C h aracter i s t ics ..............................................9

Tes t Ci r cu it s..................................................................................... 12

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. PrD | Page 2 of 16

Preliminary Technical Data ADG1236

SPECIFICATIONS

DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Parameters 25°C 85°C Y Version1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to V
On Resistance (RON) Ω typ V
120 220 260 Ω max
On Resistance Match between

Channels (∆R

)

ON

5 Ω typ V

Ω max

On Resistance Flatness (R

) 25 Ω typ VS = −5 V/0 V/+5 V; IS = −10 mA

FLAT(ON)

50 Ω max
LEAKAGE CURRENTS VDD = +10 V, VSS = −10 V

Source Off Leakage, IS (Off) ±0.01 nA typ VS = 0 V/10 V, VD = 10 V/0 V; Figure 22
±0.5 ±1 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = 0 V/10 V, VD = 10 V/0 V; Figure 22
±0.5 ±1 ±5 nA max
Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = 0 V or 10 V; Figure 23
±1 ±2 ±5 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

or I

INL

INH

INL

INH

2.0 V min

0.8 V max

0.005 µA typ VIN = V
±0.5 µA max
Digital Input Capacitance, C

DYNAMIC CHARACTERISTICS

t

ON

IN

2

5 pF typ

50 ns typ RL = 50 Ω, CL = 35 pF
ns max VS = ±10 V; Figure 24
t

OFF

20 100 ns typ RL = 50 Ω, CL = 35 pF

ns max V

Break-before-Make Time Delay, t

15 40 ns typ RL = 50 Ω, CL = 35 pF

D

1 ns min VS1 = VS2 = 10 V; Figure 25

Charge Injection 1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
Off Isolation 75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
Total Harmonic Distortion + Noise 0.002 % typ RL = 600 Ω, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 700 MHz typ RL = 50 Ω, CL = 5 pF; Figure 29
CS (Off) 2 pF typ
CD(Off) 2 pF typ
CD, CS (On) 5 pF typ

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

I

DD

0.001 µA typ Digital Inputs = 0 V or V

5.0 µA max
I

DD

150 µA typ Digital Input = 5 V
300 µA max
I

SS

0.001 µA typ Digital Inputs = 0 V or V

5.0 µA max

V

SS

= ±10 V, IS = −10 mA; Figure 21

S

= ±10 V, IS = −10 mA

S

or V

INL

INH

= ±10 V; Figure 24

S

DD

DD

Rev. PrD | Page 3 of 16

ADG1236 Preliminary Technical Data

Parameters 25°C 85°C Y Version1Unit Test Conditions/Comments

I

GND

5.0 µA max
I

GND

300 µA max

1

Temperature range for Y Version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Parameters 25°C 85°C Y Version1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range
On Resistance (RON)

On Resistance Match between

Channels (∆R

On Resistance Flatness (R

LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.01

Drain Off Leakage, ID (Off) ±0.01

Channel On Leakage, ID, IS (On) ±0.04

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

Input Current, I

Digital Input Capacitance, C

DYNAMIC CHARACTERISTICS

t

ON

t

OFF

Break-before-Make Time Delay, t

Charge Injection 5

Off Isolation 75
Channel-to-Channel Crosstalk 85

−3 dB Bandwidth 700
CS (Off) 2
CD (Off) 2
CD, CS (On) 5

)

ON

FLAT(ON)

INH

INL

or I

INL

INH

IN

2

) 40

0.001 µA typ Digital Inputs = 0 V or V

150 µA typ Digital Input = 5 V

0 V to V

220

10

V

DD

Ω typ VS = +10 V, IS = −10 mA; Figure 21
Ω max
Ω typ V

Ω max

= +10 V, IS = −10 mA

S

Ω typ VS = +3 V/+6 V/+9 V, IS = −10 mA

VDD = 12 V

nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 22

±0.5 ±1 ±5 nA max

nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 22

±0.5 ±1 ±5 nA max

±1 ±2 ±5 nA max

nA typ VS = VD = 1 V or 10 V, Figure 23

0.001

5

2.0

0.8

±0.5 µA max

V min
V max
µA typ VIN = V

pF typ

INL

50

15

15

D

1 ns min V

ns typ RL = 50 Ω, CL = 35 pF
ns max V

= 8 V; Figure 24

S

ns typ RL = 50 Ω, CL = 35 pF
ns max V

= 8 V; Figure 24

S

ns typ RL = 50 Ω, CL = 35 pF

= VS2 = 8 V; Figure 25

S1

pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
pC typ
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27;
dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
MHz typ RL = 50 Ω, CL = 5 pF; Figure 29
pF typ
pF typ
pF typ

or V

DD

INH

Rev. PrD | Page 4 of 16

Preliminary Technical Data ADG1236

Parameters 25°C 85°C Y Version1Unit Test Conditions/Comments

POWER REQUIREMENTS

I

DD

I

DD

0.001

5.0 µA max

150

300 µA max

1

Temperature range for Y Version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

µA typ Digital Inputs = 0 V or V

µA typ Digital Inputs = 5 V

VDD = 13.2 V

DD

Rev. PrD | Page 5 of 16